Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11687:b3d5f0e9e258 ) new ( 11731:c473ca7cc650 )

full compact

4,5c4,5
< sim_ticks 20299000 # Number of ticks simulated
< final_tick 20299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 20302000 # Number of ticks simulated
> final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 98455 # Simulator instruction rate (inst/s)
< host_op_rate 115276 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 434998330 # Simulator tick rate (ticks/s)
< host_mem_usage 266116 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 10367 # Simulator instruction rate (inst/s)
> host_op_rate 12141 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 45828431 # Simulator tick rate (ticks/s)
> host_mem_usage 248616 # Number of bytes of host memory used
> host_seconds 0.44 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
27,36c27,36
< system.physmem.bw_read::cpu.inst 914330755 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 400413813 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 85127346 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1399871915 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 914330755 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 914330755 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 914330755 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 400413813 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 85127346 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1399871915 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 914195646 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 400354645 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1399665058 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 914195646 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 914195646 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 914195646 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 400354645 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1399665058 # Total bandwidth to/from this memory (bytes/s)
83c83
< system.physmem.totGap 20257500 # Total gap between requests
---
> system.physmem.totGap 20260500 # Total gap between requests
99c99
< system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
101c101
< system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
196,197c196,197
< system.physmem.bytesPerActivate::gmean 295.342416 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 353.563376 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 295.844737 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 352.802892 # Bytes accessed per row activation
208,209c208,209
< system.physmem.totQLat 6110750 # Total ticks spent queuing
< system.physmem.totMemAccLat 14454500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6124000 # Total ticks spent queuing
> system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM
211c211
< system.physmem.avgQLat 13732.02 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst
213,214c213,214
< system.physmem.avgMemAccLat 32482.02 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1403.02 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s
216c216
< system.physmem.avgRdBWSys 1403.02 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s
222c222
< system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
228c228
< system.physmem.avgGap 45522.47 # Average gap between requests
---
> system.physmem.avgGap 45529.21 # Average gap between requests
235c235
< system.physmem_0.actBackEnergy 3572760 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ)
237c237
< system.physmem_0.actPowerDownEnergy 5648700 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ)
240,242c240,242
< system.physmem_0.totalEnergy 13335915 # Total energy per rank (pJ)
< system.physmem_0.averagePower 656.941626 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 12232500 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ)
> system.physmem_0.averagePower 656.916882 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank
247,248c247,248
< system.physmem_0.memoryStateTime::ACT 7376750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 12380750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states
254,257c254,257
< system.physmem_1.actBackEnergy 1468320 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 69120 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 7424250 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 237600 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ)
259,261c259,261
< system.physmem_1.totalEnergy 11499825 # Total energy per rank (pJ)
< system.physmem_1.averagePower 566.493842 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 16895250 # Total Idle time Per DRAM Rank
---
> system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ)
> system.physmem_1.averagePower 566.475803 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 16880000 # Total Idle time Per DRAM Rank
265,270c265,270
< system.physmem_1.memoryStateTime::PRE_PDN 618500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 2773750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 16276750 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 2441 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1444 # Number of conditional branches predicted
---
> system.physmem_1.memoryStateTime::PRE_PDN 620500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 2792000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 2438 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted
272c272
< system.cpu.branchPred.BTBLookups 916 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups
275c275
< system.cpu.branchPred.BTBHitPct 49.017467 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage
283c283
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
313c313
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
343c343
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
373c373
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
404,405c404,405
< system.cpu.pwrStateResidencyTicks::ON 20299000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 40599 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 20302000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 40605 # number of cpu cycles simulated
408,410c408,410
< system.cpu.fetch.icacheStallCycles 6170 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 11468 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2441 # Number of branches that fetch encountered
---
> system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered
412c412
< system.cpu.fetch.Cycles 8322 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked
414c414
< system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
416,417c416,417
< system.cpu.fetch.IcacheWaitRetryStallCycles 434 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 3907 # Number of cache lines fetched
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched
419,421c419,421
< system.cpu.fetch.rateDist::samples 15916 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.856748 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.206522 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total)
423,426c423,426
< system.cpu.fetch.rateDist::0 9525 59.85% 59.85% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2508 15.76% 75.60% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 3362 21.12% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total)
430,435c430,435
< system.cpu.fetch.rateDist::total 15916 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.060125 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.282470 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 5812 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 4409 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 5179 # Number of cycles decode is running
---
> system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 5174 # Number of cycles decode is running
440,441c440,441
< system.cpu.decode.DecodedInsts 10178 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 1683 # Number of squashed instructions handled by decode
---
> system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode
443c443
< system.cpu.rename.IdleCycles 6925 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle
446,450c446,450
< system.cpu.rename.RunCycles 4188 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 9100 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 467 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full
---
> system.cpu.rename.RunCycles 4185 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full
454,456c454,456
< system.cpu.rename.RenamedOperands 9458 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 41150 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 10006 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups
459c459
< system.cpu.rename.UndoneMaps 3964 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing
462,464c462,464
< system.cpu.rename.skidInsts 330 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1289 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit.
467c467
< system.cpu.iq.iqInstsAdded 8513 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec)
469,472c469,472
< system.cpu.iq.iqInstsIssued 7228 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 182 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 3173 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 8254 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph
474,476c474,476
< system.cpu.iq.issued_per_cycle::samples 15916 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.454134 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.844472 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle
478,482c478,482
< system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1992 12.52% 85.73% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1620 10.18% 95.91% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 608 3.82% 99.73% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle
490c490
< system.cpu.iq.issued_per_cycle::total 15916 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle
492,526c492,526
< system.cpu.iq.fu_full::IntAlu 416 28.75% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 475 32.83% 61.58% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 539 37.25% 98.83% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.83% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemWrite 17 1.17% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available
530,562c530,562
< system.cpu.iq.FU_type_0::IntAlu 4533 62.71% 62.71% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.78% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1605 22.21% 85.03% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1066 14.75% 99.78% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued
567,573c567,573
< system.cpu.iq.FU_type_0::total 7228 # Type of FU issued
< system.cpu.iq.rate 0.178034 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1447 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.200194 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 31952 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 11715 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 6617 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 7222 # Type of FU issued
> system.cpu.iq.rate 0.177860 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses
577c577
< system.cpu.iq.int_alu_accesses 8642 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses
581c581
< system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed
584c584
< system.cpu.iew.lsq.thread0.squashedStores 351 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed
593c593
< system.cpu.iew.iewDispatchedInsts 8564 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ
595,596c595,596
< system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1289 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions
604,605c604,605
< system.cpu.iew.iewExecutedInsts 6821 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1422 # Number of load instructions executed
---
> system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed
609,614c609,614
< system.cpu.iew.exec_refs 2447 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1298 # Number of branches executed
< system.cpu.iew.exec_stores 1025 # Number of stores executed
< system.cpu.iew.exec_rate 0.168009 # Inst execution rate
< system.cpu.iew.wb_sent 6677 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 6633 # cumulative count of insts written-back
---
> system.cpu.iew.exec_refs 2442 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1297 # Number of branches executed
> system.cpu.iew.exec_stores 1024 # Number of stores executed
> system.cpu.iew.exec_rate 0.167836 # Inst execution rate
> system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 6631 # cumulative count of insts written-back
616,619c616,619
< system.cpu.iew.wb_consumers 5419 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.163378 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.550101 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit
---
> system.cpu.iew.wb_consumers 5426 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit
622,624c622,624
< system.cpu.commit.committed_per_cycle::samples 15349 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.350381 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 0.988718 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle
626,634c626,634
< system.cpu.commit.committed_per_cycle::0 12681 82.62% 82.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1407 9.17% 91.78% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 599 3.90% 95.69% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 298 1.94% 97.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 170 1.11% 98.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 79 0.51% 99.25% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 44 0.29% 99.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle
638c638
< system.cpu.commit.committed_per_cycle::total 15349 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle
688,692c688,692
< system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 23233 # The number of ROB reads
< system.cpu.rob.rob_writes 16740 # The number of ROB writes
< system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 24683 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 23226 # The number of ROB reads
> system.cpu.rob.rob_writes 16730 # The number of ROB writes
> system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling
695,700c695,700
< system.cpu.cpi 8.841246 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 8.841246 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.113106 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.113106 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 6772 # number of integer regfile reads
< system.cpu.int_regfile_writes 3788 # number of integer regfile writes
---
> system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 6765 # number of integer regfile reads
> system.cpu.int_regfile_writes 3787 # number of integer regfile writes
702c702
< system.cpu.cc_regfile_reads 24220 # number of cc regfile reads
---
> system.cpu.cc_regfile_reads 24202 # number of cc regfile reads
704c704
< system.cpu.misc_regfile_reads 2559 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 2558 # number of misc regfile reads
706c706
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
708,709c708,709
< system.cpu.dcache.tags.tagsinuse 84.063183 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks.
711c711
< system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks.
713,715c713,715
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.063183 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.164186 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.164186 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy
720,724c720,724
< system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits
731,734c731,734
< system.cpu.dcache.demand_hits::cpu.data 1910 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits
< system.cpu.dcache.overall_hits::total 1910 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits
> system.cpu.dcache.overall_hits::total 1906 # number of overall hits
745,748c745,748
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12032500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12032500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8019500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8019500 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles
751,756c751,756
< system.cpu.dcache.demand_miss_latency::cpu.data 20052000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20052000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20052000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20052000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses)
763,768c763,768
< system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2264 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses
773,780c773,780
< system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72050.898204 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 72050.898204 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41986.910995 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 41986.910995 # average WriteReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency
783,786c783,786
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 56011.173184 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 56011.173184 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency
813,822c813,822
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7984500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7984500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2595500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2595500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10580000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10580000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10580000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10580000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses
825,837c825,837
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77519.417476 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77519.417476 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63304.878049 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63304.878049 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
839,840c839,840
< system.cpu.icache.tags.tagsinuse 137.515573 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks.
842c842
< system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks.
844,846c844,846
< system.cpu.icache.tags.occ_blocks::cpu.inst 137.515573 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.268585 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.268585 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy
851,859c851,859
< system.cpu.icache.tags.tag_accesses 8109 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 8109 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits
< system.cpu.icache.overall_hits::total 3540 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 8101 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits
> system.cpu.icache.overall_hits::total 3536 # number of overall hits
866,890c866,890
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25051490 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25051490 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25051490 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25051490 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25051490 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25051490 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 3905 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 3905 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 3905 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 3905 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 3905 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 3905 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093470 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.093470 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.093470 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.093470 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.093470 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.093470 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68634.219178 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68634.219178 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68634.219178 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68634.219178 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 9850 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 9833 # number of cycles access was blocked
892c892
< system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked
894c894
< system.cpu.icache.avg_blocked_cycles::no_mshrs 102.604167 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 # average number of cycles each access was blocked
910,928c910,928
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22011990 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22011990 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22011990 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22011990 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22011990 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22011990 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076569 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.076569 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.076569 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73618.695652 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73618.695652 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
935c935
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
937c937
< system.cpu.l2cache.tags.tagsinuse 17.353048 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use
942,943c942,943
< system.cpu.l2cache.tags.occ_blocks::writebacks 9.225603 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.127445 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor
957c957
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
982,993c982,993
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2461000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2461000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21652500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 21652500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7825000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7825000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21652500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10286000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31938500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21652500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10286000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31938500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles
1020,1031c1020,1031
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82033.333333 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82033.333333 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74407.216495 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74407.216495 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75970.873786 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75970.873786 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75326.650943 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75326.650943 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency
1065,1075c1065,1075
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2281000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2281000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19850000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19850000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6909500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6909500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19850000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9190500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29040500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19850000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9190500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles
1077c1077
< system.cpu.l2cache.overall_mshr_miss_latency::total 30807426 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles
1095,1105c1095,1105
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76033.333333 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76033.333333 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68448.275862 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68448.275862 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70505.102041 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70505.102041 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.880383 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency
1107c1107
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65408.547771 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency
1114c1114
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
1153c1153
< system.membus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
1174,1176c1174,1176
< system.membus.reqLayer0.occupancy 564444 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2334750 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks)