3,5c3,5
< sim_seconds 0.000019 # Number of seconds simulated
< sim_ticks 19046000 # Number of ticks simulated
< final_tick 19046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000020 # Number of seconds simulated
> sim_ticks 20299000 # Number of ticks simulated
> final_tick 20299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 51970 # Simulator instruction rate (inst/s)
< host_op_rate 60857 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 215490046 # Simulator tick rate (ticks/s)
< host_mem_usage 266056 # Number of bytes of host memory used
< host_seconds 0.09 # Real time elapsed on the host
---
> host_inst_rate 44590 # Simulator instruction rate (inst/s)
> host_op_rate 52212 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 197038809 # Simulator tick rate (ticks/s)
> host_mem_usage 265156 # Number of bytes of host memory used
> host_seconds 0.10 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
18c18
< system.physmem.bytes_read::cpu.data 8192 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 8128 # Number of bytes read from this memory
20c20
< system.physmem.bytes_read::total 28480 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 28416 # Number of bytes read from this memory
24c24
< system.physmem.num_reads::cpu.data 128 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 127 # Number of read requests responded to by this memory
26,36c26,36
< system.physmem.num_reads::total 445 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 974482831 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 430116560 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 90727712 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1495327103 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 974482831 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 974482831 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 974482831 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 430116560 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 90727712 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1495327103 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.num_reads::total 444 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 914330755 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 400413813 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 85127346 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1399871915 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 914330755 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 914330755 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 914330755 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 400413813 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 85127346 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1399871915 # Total bandwidth to/from this memory (bytes/s)
83c83
< system.physmem.totGap 19004500 # Total gap between requests
---
> system.physmem.totGap 20257500 # Total gap between requests
98,103c98,103
< system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
194,209c194,209
< system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 429.714286 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 289.613657 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 357.341954 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 8 12.70% 12.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17 26.98% 39.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 6 9.52% 66.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.76% 71.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 3.17% 74.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 3.17% 77.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
< system.physmem.totQLat 4296708 # Total ticks spent queuing
< system.physmem.totMemAccLat 12640458 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 435.612903 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 295.342416 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 353.563376 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
> system.physmem.totQLat 6110750 # Total ticks spent queuing
> system.physmem.totMemAccLat 14454500 # Total ticks spent from burst creation until serviced by the DRAM
211c211
< system.physmem.avgQLat 9655.52 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13732.02 # Average queueing delay per DRAM burst
213,214c213,214
< system.physmem.avgMemAccLat 28405.52 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1495.33 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 32482.02 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1403.02 # Average DRAM read bandwidth in MiByte/s
216c216
< system.physmem.avgRdBWSys 1495.33 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1403.02 # Average system read bandwidth in MiByte/s
219,220c219,220
< system.physmem.busUtil 11.68 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.96 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads
222c222
< system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing
228c228
< system.physmem.avgGap 42706.74 # Average gap between requests
---
> system.physmem.avgGap 45522.47 # Average gap between requests
230,232c230,232
< system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 2152800 # Energy for read commands per rank (pJ)
---
> system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 170775 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ)
234,239c234,243
< system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 10689210 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 123000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 14426160 # Total energy per rank (pJ)
< system.physmem_0.averagePower 911.173851 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 148750 # Time in different power states
---
> system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 3572760 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 5648700 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 13335915 # Total energy per rank (pJ)
> system.physmem_0.averagePower 656.941626 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 12232500 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states
241,246c245,251
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 15177500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ)
---
> system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 7376750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 12380750 # Time in different power states
> system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ)
248,253c253,262
< system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 10733670 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 84000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 12844635 # Total energy per rank (pJ)
< system.physmem_1.averagePower 811.282804 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1145250 # Time in different power states
---
> system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1468320 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 69120 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 7424250 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 237600 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 11499825 # Total energy per rank (pJ)
> system.physmem_1.averagePower 566.493842 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 16895250 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 110000 # Time in different power states
255,263c264,273
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 15228250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 2439 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1443 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 448 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 618500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 2773750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 16276750 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 2441 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1444 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 916 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 449 # Number of BTB hits
265c275
< system.cpu.branchPred.BTBHitPct 48.961749 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 49.017467 # BTB Hit Percentage
271c281
< system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches.
---
> system.cpu.branchPredindirectMispredicted 59 # Number of mispredicted indirect branches.
273c283
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
303c313
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
333c343
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
363c373
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
394,395c404,405
< system.cpu.pwrStateResidencyTicks::ON 19046000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 38093 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 20299000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 40599 # number of cpu cycles simulated
398c408
< system.cpu.fetch.icacheStallCycles 6117 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 6170 # Number of cycles fetch is stalled on an Icache miss
400,406c410,416
< system.cpu.fetch.Branches 2439 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 8723 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 274 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 416 # Number of stall cycles due to full MSHR
---
> system.cpu.fetch.Branches 2441 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 8322 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 434 # Number of stall cycles due to full MSHR
408,411c418,421
< system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 16246 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.839530 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.200509 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 15916 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.856748 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.206522 # Number of instructions fetched each cycle (Total)
413,416c423,426
< system.cpu.fetch.rateDist::0 9855 60.66% 60.66% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2507 15.43% 76.09% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 520 3.20% 79.29% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 3364 20.71% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 9525 59.85% 59.85% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2508 15.76% 75.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3362 21.12% 100.00% # Number of instructions fetched each cycle (Total)
420,428c430,438
< system.cpu.fetch.rateDist::total 16246 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.064028 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.301053 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 5842 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 4705 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 5178 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 375 # Number of times decode resolved a branch
---
> system.cpu.fetch.rateDist::total 15916 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.060125 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.282470 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 5812 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 4409 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 5179 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch
430,435c440,445
< system.cpu.decode.DecodedInsts 10177 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 1679 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 6957 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 1136 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 2347 # count of cycles rename stalled for serializing inst
---
> system.cpu.decode.DecodedInsts 10178 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1683 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 6925 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst
437,439c447,449
< system.cpu.rename.UnblockCycles 1232 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 9097 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 461 # Number of squashed instructions processed by rename
---
> system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 9100 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 467 # Number of squashed instructions processed by rename
443,446c453,456
< system.cpu.rename.SQFullEvents 1125 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 9457 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 41127 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 9458 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 41150 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 10006 # Number of integer rename lookups
449c459
< system.cpu.rename.UndoneMaps 3963 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3964 # Number of HB maps that are undone due to squashing
452,454c462,464
< system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 330 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1289 # Number of stores inserted to the mem dependence unit.
457c467
< system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 8513 # Number of instructions added to the IQ (excludes non-spec)
459,461c469,471
< system.cpu.iq.iqInstsIssued 7229 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling
---
> system.cpu.iq.iqInstsIssued 7228 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 182 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 3173 # Number of squashed instructions iterated over during squash; mainly for profiling
464,466c474,476
< system.cpu.iq.issued_per_cycle::samples 16246 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.444971 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.838160 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15916 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.454134 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.844472 # Number of insts issued each cycle
468,472c478,482
< system.cpu.iq.issued_per_cycle::0 11980 73.74% 73.74% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1997 12.29% 86.03% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1618 9.96% 95.99% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 608 3.74% 99.74% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 43 0.26% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1992 12.52% 85.73% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1620 10.18% 95.91% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 608 3.82% 99.73% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle
480c490
< system.cpu.iq.issued_per_cycle::total 16246 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15916 # Number of insts issued each cycle
482,512c492,522
< system.cpu.iq.fu_full::IntAlu 416 28.89% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 475 32.99% 61.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 549 38.12% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 416 28.85% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 475 32.94% 61.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 551 38.21% 100.00% # attempts to use FU when none available
516,540c526,550
< system.cpu.iq.FU_type_0::IntAlu 4534 62.72% 62.72% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.79% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4533 62.71% 62.71% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.78% # Type of FU issued
545,546c555,556
< system.cpu.iq.FU_type_0::MemRead 1606 22.22% 85.05% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1081 14.95% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 1605 22.21% 85.03% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1082 14.97% 100.00% # Type of FU issued
549,555c559,565
< system.cpu.iq.FU_type_0::total 7229 # Type of FU issued
< system.cpu.iq.rate 0.189772 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1440 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.199198 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 32277 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 6614 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 7228 # Type of FU issued
> system.cpu.iq.rate 0.178034 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.199502 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 31952 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 11715 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 6617 # Number of integer instruction queue wakeup accesses
559c569
< system.cpu.iq.int_alu_accesses 8641 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8642 # Number of integer alu accesses
563c573
< system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed
566c576
< system.cpu.iew.lsq.thread0.squashedStores 346 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 351 # Number of stores squashed
572,573c582,583
< system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 339 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking
575c585
< system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 8564 # Number of instructions dispatched to IQ
577,578c587,588
< system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1289 # Number of dispatched store instructions
583,584c593,594
< system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly
---
> system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly
586,588c596,598
< system.cpu.iew.iewExecutedInsts 6820 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1423 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 6821 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1422 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute
591,592c601,602
< system.cpu.iew.exec_refs 2448 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1296 # Number of branches executed
---
> system.cpu.iew.exec_refs 2447 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1298 # Number of branches executed
594,601c604,611
< system.cpu.iew.exec_rate 0.179036 # Inst execution rate
< system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 6630 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 2985 # num instructions producing a value
< system.cpu.iew.wb_consumers 5422 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.174048 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.550535 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 2710 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_rate 0.168009 # Inst execution rate
> system.cpu.iew.wb_sent 6677 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 6633 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 2981 # num instructions producing a value
> system.cpu.iew.wb_consumers 5419 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.163378 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.550101 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit
603,606c613,616
< system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 15677 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.343050 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 0.979995 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 15349 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.350381 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 0.988718 # Number of insts commited each cycle
608,616c618,626
< system.cpu.commit.committed_per_cycle::0 13011 82.99% 82.99% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1405 8.96% 91.96% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 598 3.81% 95.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 299 1.91% 97.68% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 169 1.08% 98.76% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 80 0.51% 99.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 44 0.28% 99.55% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 28 0.18% 99.73% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 43 0.27% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 12681 82.62% 82.62% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1407 9.17% 91.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 599 3.90% 95.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 298 1.94% 97.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 170 1.11% 98.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 79 0.51% 99.25% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 44 0.29% 99.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle
620c630
< system.cpu.commit.committed_per_cycle::total 15677 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 15349 # Number of insts commited each cycle
667,670c677,680
< system.cpu.rob.rob_reads 23565 # The number of ROB reads
< system.cpu.rob.rob_writes 16751 # The number of ROB writes
< system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 21847 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 23233 # The number of ROB reads
> system.cpu.rob.rob_writes 16740 # The number of ROB writes
> system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 24683 # Total number of cycles that the CPU has spent unscheduled due to idling
673,676c683,686
< system.cpu.cpi 8.295514 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 8.295514 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.120547 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.120547 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 8.841246 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 8.841246 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.113106 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.113106 # IPC: Total IPC of All Threads
680c690
< system.cpu.cc_regfile_reads 24217 # number of cc regfile reads
---
> system.cpu.cc_regfile_reads 24220 # number of cc regfile reads
684c694
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
686c696
< system.cpu.dcache.tags.tagsinuse 84.349867 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.063183 # Cycle average of tags in use
691,693c701,703
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.349867 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.164746 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.164746 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.063183 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.164186 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.164186 # Average percentage of cache occupancy
695,696c705,706
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
698,700c708,710
< system.cpu.dcache.tags.tag_accesses 4725 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4725 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
713,714c723,724
< system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses
---
> system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
719,734c729,744
< system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses
< system.cpu.dcache.overall_misses::total 359 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 10937500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 10937500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9601000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9601000 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 127000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 20538500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20538500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20538500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20538500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1356 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1356 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses
> system.cpu.dcache.overall_misses::total 358 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12032500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12032500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8019500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8019500 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 20052000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20052000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20052000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20052000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses)
741,746c751,756
< system.cpu.dcache.demand_accesses::cpu.data 2269 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2269 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2269 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2269 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123894 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.123894 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses
751,764c761,774
< system.cpu.dcache.demand_miss_rate::cpu.data 0.158219 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.158219 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.158219 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.158219 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65104.166667 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 65104.166667 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50267.015707 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 50267.015707 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 57210.306407 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 57210.306407 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72050.898204 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 72050.898204 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41986.910995 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41986.910995 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 56011.173184 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 56011.173184 # average overall miss latency
766c776
< system.cpu.dcache.blocked_cycles::no_targets 1304 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked
770c780
< system.cpu.dcache.avg_blocked_cycles::no_targets 72.444444 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked
773,774c783,784
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
779,782c789,792
< system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits
791,800c801,810
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7149000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7149000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9849500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9849500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9849500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9849500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075959 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075959 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7984500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7984500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2595500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2595500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10580000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10580000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10580000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10580000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses
803,815c813,825
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69407.766990 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69407.766990 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65865.853659 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65865.853659 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77519.417476 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77519.417476 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63304.878049 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63304.878049 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
817,818c827,828
< system.cpu.icache.tags.tagsinuse 137.872552 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 3542 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 137.515573 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks.
820c830
< system.cpu.icache.tags.avg_refs 11.846154 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks.
822,824c832,834
< system.cpu.icache.tags.occ_blocks::cpu.inst 137.872552 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.269282 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.269282 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 137.515573 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.268585 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.268585 # Average percentage of cache occupancy
826,827c836,837
< system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
829,870c839,880
< system.cpu.icache.tags.tag_accesses 8107 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 8107 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 3542 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 3542 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 3542 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 3542 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 3542 # number of overall hits
< system.cpu.icache.overall_hits::total 3542 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses
< system.cpu.icache.overall_misses::total 362 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 22563992 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 22563992 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 22563992 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 22563992 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 22563992 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 22563992 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 3904 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 3904 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 3904 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 3904 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 3904 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 3904 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092725 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.092725 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.092725 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.092725 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.092725 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.092725 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62331.469613 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 62331.469613 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 62331.469613 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 62331.469613 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 8558 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 35 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 8109 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 8109 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits
> system.cpu.icache.overall_hits::total 3540 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
> system.cpu.icache.overall_misses::total 365 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25051490 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25051490 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25051490 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25051490 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25051490 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25051490 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 3905 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 3905 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 3905 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 3905 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 3905 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 3905 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093470 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.093470 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.093470 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.093470 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.093470 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.093470 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68634.219178 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 68634.219178 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 68634.219178 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 68634.219178 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 9850 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked
872,873c882,883
< system.cpu.icache.avg_blocked_cycles::no_mshrs 90.084211 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 102.604167 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked
876,881c886,891
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits
888,906c898,916
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19836992 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19836992 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19836992 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19836992 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19836992 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19836992 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076588 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076588 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076588 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.076588 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076588 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.076588 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66344.454849 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66344.454849 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66344.454849 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 66344.454849 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66344.454849 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 66344.454849 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22011990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22011990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22011990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22011990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22011990 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22011990 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076569 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.076569 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.076569 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73618.695652 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73618.695652 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
913c923
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
915c925
< system.cpu.l2cache.tags.tagsinuse 17.395386 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 17.353048 # Cycle average of tags in use
920,924c930,934
< system.cpu.l2cache.tags.occ_blocks::writebacks 9.233331 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.162055 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000498 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.001062 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9.225603 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.127445 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy
935c945
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
938,939c948,949
< system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits
943,944c953,954
< system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 18 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 11 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 19 # number of demand (read+write) hits
946,949c956,959
< system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
< system.cpu.l2cache.overall_hits::total 18 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 31 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 31 # number of ReadExReq misses
---
> system.cpu.l2cache.overall_hits::cpu.data 11 # number of overall hits
> system.cpu.l2cache.overall_hits::total 19 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses
955,956c965,966
< system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 425 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 133 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 424 # number of demand (read+write) misses
958,971c968,981
< system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
< system.cpu.l2cache.overall_misses::total 425 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2572500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2572500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19478500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 19478500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6989500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 6989500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19478500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9562000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 29040500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19478500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9562000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 29040500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.data 133 # number of overall misses
> system.cpu.l2cache.overall_misses::total 424 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2461000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2461000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21652500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 21652500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7825000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7825000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21652500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10286000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31938500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21652500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10286000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31938500 # number of overall miss cycles
986,987c996,997
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.756098 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.756098 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses
993,994c1003,1004
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.930556 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.959368 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.923611 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.957111 # miss rate for demand accesses
996,1009c1006,1019
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.930556 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.959368 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82983.870968 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82983.870968 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66936.426117 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66936.426117 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67859.223301 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67859.223301 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66936.426117 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71358.208955 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68330.588235 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66936.426117 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71358.208955 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68330.588235 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82033.333333 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82033.333333 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74407.216495 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74407.216495 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75970.873786 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75970.873786 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75326.650943 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75326.650943 # average overall miss latency
1016,1017d1025
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
1023,1024c1031,1032
< system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
1026,1027c1034,1035
< system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
1043,1057c1051,1065
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 3053926 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2154000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2154000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17682000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17682000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6104000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6104000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17682000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8258000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 25940000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17682000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8258000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 28993926 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2281000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2281000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19850000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19850000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6909500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6909500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19850000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9190500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29040500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19850000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9190500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30807426 # number of overall MSHR miss cycles
1073,1087c1081,1095
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 57621.245283 # average HardPFReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71800 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71800 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60972.413793 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60972.413793 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62285.714286 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62285.714286 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62057.416268 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61558.229299 # average overall mshr miss latency
---
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76033.333333 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76033.333333 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68448.275862 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68448.275862 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70505.102041 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70505.102041 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.880383 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65408.547771 # average overall mshr miss latency
1094c1102
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
1122c1130
< system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
---
> system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%)
1124c1132
< system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
1133c1141
< system.membus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states
1154,1157c1162,1165
< system.membus.reqLayer0.occupancy 562944 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2340257 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.3 # Layer utilization (%)
---
> system.membus.reqLayer0.occupancy 564444 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2334750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 11.5 # Layer utilization (%)