4,5c4,5
< sim_ticks 17777000 # Number of ticks simulated
< final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 17778000 # Number of ticks simulated
> final_tick 17778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 63242 # Simulator instruction rate (inst/s)
< host_op_rate 74054 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 244740900 # Simulator tick rate (ticks/s)
< host_mem_usage 307828 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 58925 # Simulator instruction rate (inst/s)
> host_op_rate 69000 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 228057572 # Simulator tick rate (ticks/s)
> host_mem_usage 310616 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
26,35c26,35
< system.physmem.bw_read::cpu.inst 975642684 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 388817011 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 97204253 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1461663948 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 975642684 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 975642684 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 975642684 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 388817011 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 97204253 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1461663948 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 975587805 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 388795140 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 97198785 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1461581730 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 975587805 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 975587805 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 975587805 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 388795140 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 97198785 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1461581730 # Total bandwidth to/from this memory (bytes/s)
82c82
< system.physmem.totGap 17763500 # Total gap between requests
---
> system.physmem.totGap 17764500 # Total gap between requests
207,208c207,208
< system.physmem.totQLat 3130500 # Total ticks spent queuing
< system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3121500 # Total ticks spent queuing
> system.physmem.totMemAccLat 10752750 # Total ticks spent from burst creation until serviced by the DRAM
210c210
< system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7669.53 # Average queueing delay per DRAM burst
212,213c212,213
< system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 26419.53 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1465.18 # Average DRAM read bandwidth in MiByte/s
215c215
< system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1465.18 # Average system read bandwidth in MiByte/s
227c227
< system.physmem.avgGap 43644.96 # Average gap between requests
---
> system.physmem.avgGap 43647.42 # Average gap between requests
234c234
< system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 10769580 # Energy for active background per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ)
< system.physmem_0.averagePower 905.346375 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states
---
> system.physmem_0.totalEnergy 14349765 # Total energy per rank (pJ)
> system.physmem_0.averagePower 905.276555 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 315250 # Time in different power states
241c241
< system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 15294250 # Time in different power states
248,252c248,252
< system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ)
< system.physmem_1.averagePower 805.767883 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states
---
> system.physmem_1.actBackEnergy 10147140 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 598500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 12757005 # Total energy per rank (pJ)
> system.physmem_1.averagePower 805.747987 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 956000 # Time in different power states
255c255
< system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 14370250 # Time in different power states
384c384
< system.cpu.numCycles 35555 # number of cpu cycles simulated
---
> system.cpu.numCycles 35557 # number of cpu cycles simulated
387,388c387,388
< system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed
---
> system.cpu.fetch.icacheStallCycles 6181 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 11260 # Number of instructions fetch has processed
391c391
< system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 7643 # Number of cycles fetch has run and was not squashing or blocked
395,400c395,400
< system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 3826 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 175 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 15133 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.869491 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.207772 # Number of instructions fetched each cycle (Total)
402,405c402,405
< system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 8934 59.04% 59.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2459 16.25% 75.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 521 3.44% 78.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3219 21.27% 100.00% # Number of instructions fetched each cycle (Total)
409,414c409,414
< system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 5038 # Number of cycles decode is running
---
> system.cpu.fetch.rateDist::total 15133 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.065697 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.316675 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 5932 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 3662 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 5040 # Number of cycles decode is running
417,420c417,420
< system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode
---
> system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 9865 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1623 # Number of squashed instructions handled by decode
422,425c422,425
< system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 4094 # Number of cycles rename is running
---
> system.cpu.rename.IdleCycles 7001 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 962 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 1967 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 4096 # Number of cycles rename is running
427,428c427,428
< system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename
---
> system.cpu.rename.RenamedInsts 8887 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename
433,435c433,435
< system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 9238 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 40311 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 9765 # Number of integer rename lookups
438c438
< system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3744 # Number of HB maps that are undone due to squashing
442c442
< system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 1809 # Number of loads inserted to the mem dependence unit.
446c446
< system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 8352 # Number of instructions added to the IQ (excludes non-spec)
448,451c448,451
< system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 3013 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 7853 # Number of squashed operands that are examined and possibly removed from graph
453,455c453,455
< system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15133 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.472345 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.858310 # Number of insts issued each cycle
457,461c457,461
< system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10931 72.23% 72.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1952 12.90% 85.13% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1600 10.57% 95.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 604 3.99% 99.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 46 0.30% 100.00% # Number of insts issued each cycle
469c469
< system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15133 # Number of insts issued each cycle
471,501c471,501
< system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 412 28.91% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 465 32.63% 61.54% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 548 38.46% 100.00% # attempts to use FU when none available
505,535c505,535
< system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4470 62.53% 62.53% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.65% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.65% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.65% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.65% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.88% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1081 15.12% 100.00% # Type of FU issued
538,544c538,544
< system.cpu.iq.FU_type_0::total 7146 # Type of FU issued
< system.cpu.iq.rate 0.200984 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 7148 # Type of FU issued
> system.cpu.iq.rate 0.201029 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1425 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.199356 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30998 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 11395 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 6553 # Number of integer instruction queue wakeup accesses
548c548
< system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8545 # Number of integer alu accesses
552c552
< system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 782 # Number of loads squashed
564c564
< system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 8405 # Number of instructions dispatched to IQ
566c566
< system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 1809 # Number of dispatched load instructions
575c575
< system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions
---
> system.cpu.iew.iewExecutedInsts 6744 # Number of executed instructions
583,587c583,587
< system.cpu.iew.exec_rate 0.189622 # Inst execution rate
< system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 6567 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 2975 # num instructions producing a value
< system.cpu.iew.wb_consumers 5372 # num instructions consuming a value
---
> system.cpu.iew.exec_rate 0.189667 # Inst execution rate
> system.cpu.iew.wb_sent 6611 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 6569 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 2977 # num instructions producing a value
> system.cpu.iew.wb_consumers 5378 # num instructions consuming a value
589,590c589,590
< system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.184746 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.553552 # average fanout of values written-back
592c592
< system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 2574 # The number of squashed insts skipped by commit
595,597c595,597
< system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 14591 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.368583 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.017117 # Number of insts commited each cycle
599,601c599,601
< system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11942 81.84% 81.84% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1388 9.51% 91.36% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 601 4.12% 95.48% # Number of insts commited each cycle
603,607c603,607
< system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 167 1.14% 98.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 78 0.53% 99.16% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 46 0.32% 99.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 33 0.23% 99.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle
611c611
< system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 14591 # Number of insts commited each cycle
658,661c658,661
< system.cpu.rob.rob_reads 22320 # The number of ROB reads
< system.cpu.rob.rob_writes 16439 # The number of ROB writes
< system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 22343 # The number of ROB reads
> system.cpu.rob.rob_writes 16451 # The number of ROB writes
> system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 20424 # Total number of cycles that the CPU has spent unscheduled due to idling
664,669c664,669
< system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 6718 # number of integer regfile reads
< system.cpu.int_regfile_writes 3745 # number of integer regfile writes
---
> system.cpu.cpi 7.743249 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.743249 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.129145 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.129145 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 6720 # number of integer regfile reads
> system.cpu.int_regfile_writes 3747 # number of integer regfile writes
671c671
< system.cpu.cc_regfile_reads 23959 # number of cc regfile reads
---
> system.cpu.cc_regfile_reads 23965 # number of cc regfile reads
676c676
< system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.271040 # Cycle average of tags in use
681,683c681,683
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.271040 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.164592 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.164592 # Average percentage of cache occupancy
712,713c712,713
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9210000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9210000 # number of ReadReq miss cycles
716,721c716,721
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles
---
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 125500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 16927500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16927500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 16927500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16927500 # number of overall miss cycles
744,745c744,745
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55149.700599 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55149.700599 # average ReadReq miss latency
748,753c748,753
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency
---
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62750 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62750 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 47283.519553 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 47283.519553 # average overall miss latency
780,781c780,781
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5839000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5839000 # number of ReadReq MSHR miss cycles
784,787c784,787
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8293500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8293500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8293500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8293500 # number of overall MSHR miss cycles
796,797c796,797
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57245.098039 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57245.098039 # average ReadReq mshr miss latency
800,803c800,803
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency
806,807c806,807
< system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 136.212207 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 3460 # Total number of references to valid blocks.
809c809
< system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 11.728814 # Average number of references to valid blocks.
811,813c811,813
< system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 136.212207 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.266039 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.266039 # Average percentage of cache occupancy
818,825c818,825
< system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 7941 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits
< system.cpu.icache.overall_hits::total 3459 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 7943 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 7943 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 3460 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 3460 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 3460 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 3460 # number of overall hits
> system.cpu.icache.overall_hits::total 3460 # number of overall hits
832,856c832,856
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21574493 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21574493 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21574493 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21574493 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21574493 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21574493 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 3824 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 3824 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 3824 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 3824 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 3824 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 3824 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095188 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.095188 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.095188 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.095188 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.095188 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.095188 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59270.585165 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 59270.585165 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 59270.585165 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 59270.585165 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 8439 # number of cycles access was blocked
860c860
< system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 94.820225 # average number of cycles each access was blocked
876,893c876,893
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18788993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 18788993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18788993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 18788993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18788993 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 18788993 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077406 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.077406 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.077406 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63476.327703 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63476.327703 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency
902c902
< system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 192.769134 # Cycle average of tags in use
907,910c907,910
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.484820 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 45.082970 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.201345 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008452 # Average percentage of cache occupancy
913c913
< system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.011766 # Average percentage of cache occupancy
950,951c950,951
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18323500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 18323500 # number of ReadCleanReq miss cycles
954c954
< system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 18323500 # number of demand (read+write) miss cycles
956,957c956,957
< system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 26192500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 18323500 # number of overall miss cycles
959c959
< system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 26192500 # number of overall miss cycles
986,987c986,987
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67119.047619 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67119.047619 # average ReadCleanReq miss latency
990c990
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency
992,993c992,993
< system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 67856.217617 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency
995c995
< system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 67856.217617 # average overall miss latency
1033,1041c1033,1041
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16642000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16642000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16642000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23570000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16642000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928000 # number of overall MSHR miss cycles
1043c1043
< system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 25195926 # number of overall MSHR miss cycles
1063,1071c1063,1071
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61183.823529 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61183.823529 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61384.615385 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61384.615385 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62026.315789 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency
1073c1073
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58868.985981 # average overall mshr miss latency
1074a1075,1080
> system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 21 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 21 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1090,1091c1096,1097
< system.cpu.toL2Bus.snoop_fanout::mean 1.117216 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.321973 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.133700 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.340641 # Request fanout histogram
1093,1095c1099,1101
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 482 88.28% 88.28% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 64 11.72% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 473 86.63% 86.63% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 73 13.37% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1097,1098c1103,1104
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1125c1131
< system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 514944 # Layer occupancy (ticks)
1127c1133
< system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2135000 # Layer occupancy (ticks)
< sim_ticks 17777000 # Number of ticks simulated
< final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 17778000 # Number of ticks simulated
> final_tick 17778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 63242 # Simulator instruction rate (inst/s)
< host_op_rate 74054 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 244740900 # Simulator tick rate (ticks/s)
< host_mem_usage 307828 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 58925 # Simulator instruction rate (inst/s)
> host_op_rate 69000 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 228057572 # Simulator tick rate (ticks/s)
> host_mem_usage 310616 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
26,35c26,35
< system.physmem.bw_read::cpu.inst 975642684 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 388817011 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 97204253 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1461663948 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 975642684 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 975642684 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 975642684 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 388817011 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 97204253 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1461663948 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 975587805 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 388795140 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 97198785 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1461581730 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 975587805 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 975587805 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 975587805 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 388795140 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 97198785 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1461581730 # Total bandwidth to/from this memory (bytes/s)
82c82
< system.physmem.totGap 17763500 # Total gap between requests
---
> system.physmem.totGap 17764500 # Total gap between requests
207,208c207,208
< system.physmem.totQLat 3130500 # Total ticks spent queuing
< system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3121500 # Total ticks spent queuing
> system.physmem.totMemAccLat 10752750 # Total ticks spent from burst creation until serviced by the DRAM
210c210
< system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7669.53 # Average queueing delay per DRAM burst
212,213c212,213
< system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 26419.53 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1465.18 # Average DRAM read bandwidth in MiByte/s
215c215
< system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1465.18 # Average system read bandwidth in MiByte/s
227c227
< system.physmem.avgGap 43644.96 # Average gap between requests
---
> system.physmem.avgGap 43647.42 # Average gap between requests
234c234
< system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 10769580 # Energy for active background per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ)
< system.physmem_0.averagePower 905.346375 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states
---
> system.physmem_0.totalEnergy 14349765 # Total energy per rank (pJ)
> system.physmem_0.averagePower 905.276555 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 315250 # Time in different power states
241c241
< system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 15294250 # Time in different power states
248,252c248,252
< system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ)
< system.physmem_1.averagePower 805.767883 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states
---
> system.physmem_1.actBackEnergy 10147140 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 598500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 12757005 # Total energy per rank (pJ)
> system.physmem_1.averagePower 805.747987 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 956000 # Time in different power states
255c255
< system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 14370250 # Time in different power states
384c384
< system.cpu.numCycles 35555 # number of cpu cycles simulated
---
> system.cpu.numCycles 35557 # number of cpu cycles simulated
387,388c387,388
< system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed
---
> system.cpu.fetch.icacheStallCycles 6181 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 11260 # Number of instructions fetch has processed
391c391
< system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 7643 # Number of cycles fetch has run and was not squashing or blocked
395,400c395,400
< system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 3826 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 175 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 15133 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.869491 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.207772 # Number of instructions fetched each cycle (Total)
402,405c402,405
< system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 8934 59.04% 59.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2459 16.25% 75.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 521 3.44% 78.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3219 21.27% 100.00% # Number of instructions fetched each cycle (Total)
409,414c409,414
< system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 5038 # Number of cycles decode is running
---
> system.cpu.fetch.rateDist::total 15133 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.065697 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.316675 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 5932 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 3662 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 5040 # Number of cycles decode is running
417,420c417,420
< system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode
---
> system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 9865 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1623 # Number of squashed instructions handled by decode
422,425c422,425
< system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 4094 # Number of cycles rename is running
---
> system.cpu.rename.IdleCycles 7001 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 962 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 1967 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 4096 # Number of cycles rename is running
427,428c427,428
< system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename
---
> system.cpu.rename.RenamedInsts 8887 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename
433,435c433,435
< system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 9238 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 40311 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 9765 # Number of integer rename lookups
438c438
< system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3744 # Number of HB maps that are undone due to squashing
442c442
< system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 1809 # Number of loads inserted to the mem dependence unit.
446c446
< system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 8352 # Number of instructions added to the IQ (excludes non-spec)
448,451c448,451
< system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 3013 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 7853 # Number of squashed operands that are examined and possibly removed from graph
453,455c453,455
< system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15133 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.472345 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.858310 # Number of insts issued each cycle
457,461c457,461
< system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10931 72.23% 72.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1952 12.90% 85.13% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1600 10.57% 95.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 604 3.99% 99.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 46 0.30% 100.00% # Number of insts issued each cycle
469c469
< system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15133 # Number of insts issued each cycle
471,501c471,501
< system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 412 28.91% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 465 32.63% 61.54% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 548 38.46% 100.00% # attempts to use FU when none available
505,535c505,535
< system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4470 62.53% 62.53% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.65% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.65% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.65% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.65% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.88% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1081 15.12% 100.00% # Type of FU issued
538,544c538,544
< system.cpu.iq.FU_type_0::total 7146 # Type of FU issued
< system.cpu.iq.rate 0.200984 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 7148 # Type of FU issued
> system.cpu.iq.rate 0.201029 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1425 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.199356 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30998 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 11395 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 6553 # Number of integer instruction queue wakeup accesses
548c548
< system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8545 # Number of integer alu accesses
552c552
< system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 782 # Number of loads squashed
564c564
< system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 8405 # Number of instructions dispatched to IQ
566c566
< system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 1809 # Number of dispatched load instructions
575c575
< system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions
---
> system.cpu.iew.iewExecutedInsts 6744 # Number of executed instructions
583,587c583,587
< system.cpu.iew.exec_rate 0.189622 # Inst execution rate
< system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 6567 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 2975 # num instructions producing a value
< system.cpu.iew.wb_consumers 5372 # num instructions consuming a value
---
> system.cpu.iew.exec_rate 0.189667 # Inst execution rate
> system.cpu.iew.wb_sent 6611 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 6569 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 2977 # num instructions producing a value
> system.cpu.iew.wb_consumers 5378 # num instructions consuming a value
589,590c589,590
< system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.184746 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.553552 # average fanout of values written-back
592c592
< system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 2574 # The number of squashed insts skipped by commit
595,597c595,597
< system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 14591 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.368583 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.017117 # Number of insts commited each cycle
599,601c599,601
< system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11942 81.84% 81.84% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1388 9.51% 91.36% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 601 4.12% 95.48% # Number of insts commited each cycle
603,607c603,607
< system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 167 1.14% 98.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 78 0.53% 99.16% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 46 0.32% 99.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 33 0.23% 99.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle
611c611
< system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 14591 # Number of insts commited each cycle
658,661c658,661
< system.cpu.rob.rob_reads 22320 # The number of ROB reads
< system.cpu.rob.rob_writes 16439 # The number of ROB writes
< system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 22343 # The number of ROB reads
> system.cpu.rob.rob_writes 16451 # The number of ROB writes
> system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 20424 # Total number of cycles that the CPU has spent unscheduled due to idling
664,669c664,669
< system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 6718 # number of integer regfile reads
< system.cpu.int_regfile_writes 3745 # number of integer regfile writes
---
> system.cpu.cpi 7.743249 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.743249 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.129145 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.129145 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 6720 # number of integer regfile reads
> system.cpu.int_regfile_writes 3747 # number of integer regfile writes
671c671
< system.cpu.cc_regfile_reads 23959 # number of cc regfile reads
---
> system.cpu.cc_regfile_reads 23965 # number of cc regfile reads
676c676
< system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.271040 # Cycle average of tags in use
681,683c681,683
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.271040 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.164592 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.164592 # Average percentage of cache occupancy
712,713c712,713
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9210000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9210000 # number of ReadReq miss cycles
716,721c716,721
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles
---
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 125500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 16927500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16927500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 16927500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16927500 # number of overall miss cycles
744,745c744,745
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55149.700599 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55149.700599 # average ReadReq miss latency
748,753c748,753
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency
---
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62750 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62750 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 47283.519553 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 47283.519553 # average overall miss latency
780,781c780,781
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5839000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5839000 # number of ReadReq MSHR miss cycles
784,787c784,787
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8293500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8293500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8293500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8293500 # number of overall MSHR miss cycles
796,797c796,797
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57245.098039 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57245.098039 # average ReadReq mshr miss latency
800,803c800,803
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency
806,807c806,807
< system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 136.212207 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 3460 # Total number of references to valid blocks.
809c809
< system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 11.728814 # Average number of references to valid blocks.
811,813c811,813
< system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 136.212207 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.266039 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.266039 # Average percentage of cache occupancy
818,825c818,825
< system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 7941 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits
< system.cpu.icache.overall_hits::total 3459 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 7943 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 7943 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 3460 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 3460 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 3460 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 3460 # number of overall hits
> system.cpu.icache.overall_hits::total 3460 # number of overall hits
832,856c832,856
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21574493 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21574493 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21574493 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21574493 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21574493 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21574493 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 3824 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 3824 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 3824 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 3824 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 3824 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 3824 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095188 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.095188 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.095188 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.095188 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.095188 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.095188 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59270.585165 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 59270.585165 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 59270.585165 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 59270.585165 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 8439 # number of cycles access was blocked
860c860
< system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 94.820225 # average number of cycles each access was blocked
876,893c876,893
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18788993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 18788993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18788993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 18788993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18788993 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 18788993 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077406 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.077406 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.077406 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63476.327703 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63476.327703 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency
902c902
< system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 192.769134 # Cycle average of tags in use
907,910c907,910
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.484820 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 45.082970 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.201345 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008452 # Average percentage of cache occupancy
913c913
< system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.011766 # Average percentage of cache occupancy
950,951c950,951
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18323500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 18323500 # number of ReadCleanReq miss cycles
954c954
< system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 18323500 # number of demand (read+write) miss cycles
956,957c956,957
< system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 26192500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 18323500 # number of overall miss cycles
959c959
< system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 26192500 # number of overall miss cycles
986,987c986,987
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67119.047619 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67119.047619 # average ReadCleanReq miss latency
990c990
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency
992,993c992,993
< system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 67856.217617 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency
995c995
< system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 67856.217617 # average overall miss latency
1033,1041c1033,1041
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16642000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16642000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16642000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23570000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16642000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928000 # number of overall MSHR miss cycles
1043c1043
< system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 25195926 # number of overall MSHR miss cycles
1063,1071c1063,1071
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61183.823529 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61183.823529 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61384.615385 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61384.615385 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62026.315789 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency
1073c1073
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58868.985981 # average overall mshr miss latency
1074a1075,1080
> system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 21 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 21 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1090,1091c1096,1097
< system.cpu.toL2Bus.snoop_fanout::mean 1.117216 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.321973 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.133700 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.340641 # Request fanout histogram
1093,1095c1099,1101
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 482 88.28% 88.28% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 64 11.72% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 473 86.63% 86.63% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 73 13.37% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1097,1098c1103,1104
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1125c1131
< system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 514944 # Layer occupancy (ticks)
1127c1133
< system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2135000 # Layer occupancy (ticks)