7,10c7,10
< host_inst_rate 63568 # Simulator instruction rate (inst/s)
< host_op_rate 74435 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 246000775 # Simulator tick rate (ticks/s)
< host_mem_usage 307848 # Number of bytes of host memory used
---
> host_inst_rate 63242 # Simulator instruction rate (inst/s)
> host_op_rate 74054 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 244740900 # Simulator tick rate (ticks/s)
> host_mem_usage 307828 # Number of bytes of host memory used
97c97
< system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see
100c100
< system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
103c103
< system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
106c106
< system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see
207,208c207,208
< system.physmem.totQLat 3256492 # Total ticks spent queuing
< system.physmem.totMemAccLat 10887742 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3130500 # Total ticks spent queuing
> system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM
210c210
< system.physmem.avgQLat 8001.21 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst
212c212
< system.physmem.avgMemAccLat 26751.21 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst
221c221
< system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing
234c234
< system.physmem_0.actBackEnergy 10756755 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 14336940 # Total energy per rank (pJ)
< system.physmem_0.averagePower 905.538607 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 334000 # Time in different power states
---
> system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ)
> system.physmem_0.averagePower 905.346375 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states
241c241
< system.physmem_0.memoryStateTime::ACT 15275500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states
248,252c248,252
< system.physmem_1.actBackEnergy 10156545 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 590250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 12758160 # Total energy per rank (pJ)
< system.physmem_1.averagePower 805.820938 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 942000 # Time in different power states
---
> system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ)
> system.physmem_1.averagePower 805.767883 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states
255c255
< system.physmem_1.memoryStateTime::ACT 14384250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states
387c387
< system.cpu.fetch.icacheStallCycles 6172 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss
391c391
< system.cpu.fetch.Cycles 7501 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked
398,400c398,400
< system.cpu.fetch.rateDist::samples 14978 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.878021 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.210560 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total)
402,405c402,405
< system.cpu.fetch.rateDist::0 8782 58.63% 58.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2458 16.41% 75.04% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 521 3.48% 78.52% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 3217 21.48% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total)
409c409
< system.cpu.fetch.rateDist::total 14978 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total)
413,414c413,414
< system.cpu.decode.BlockedCycles 3520 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 5039 # Number of cycles decode is running
---
> system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 5038 # Number of cycles decode is running
419,420c419,420
< system.cpu.decode.DecodedInsts 9859 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 1620 # Number of squashed instructions handled by decode
---
> system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode
423c423
< system.cpu.rename.BlockCycles 960 # Number of cycles rename is blocking
---
> system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking
425,428c425,428
< system.cpu.rename.RunCycles 4095 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 601 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 8880 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 409 # Number of squashed instructions processed by rename
---
> system.cpu.rename.RunCycles 4094 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename
432,435c432,435
< system.cpu.rename.SQFullEvents 527 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 9231 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 40283 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 9759 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups
438c438
< system.cpu.rename.UndoneMaps 3737 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing
442c442
< system.cpu.memDep0.insertedLoads 1806 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit.
446c446
< system.cpu.iq.iqInstsAdded 8347 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec)
448c448
< system.cpu.iq.iqInstsIssued 7144 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued
450,451c450,451
< system.cpu.iq.iqSquashedInstsExamined 3008 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 7841 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph
453,455c453,455
< system.cpu.iq.issued_per_cycle::samples 14978 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.476966 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.861224 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle
457,460c457,460
< system.cpu.iq.issued_per_cycle::0 10780 71.97% 71.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1947 13.00% 84.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1601 10.69% 95.66% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 605 4.04% 99.70% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle
469c469
< system.cpu.iq.issued_per_cycle::total 14978 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle
471,501c471,501
< system.cpu.iq.fu_full::IntAlu 411 28.90% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 464 32.63% 61.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 547 38.47% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available
505,529c505,529
< system.cpu.iq.FU_type_0::IntAlu 4467 62.53% 62.53% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued
534c534
< system.cpu.iq.FU_type_0::MemRead 1588 22.23% 84.87% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued
538,544c538,544
< system.cpu.iq.FU_type_0::total 7144 # Type of FU issued
< system.cpu.iq.rate 0.200928 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1422 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.199048 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30828 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 11385 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 7146 # Type of FU issued
> system.cpu.iq.rate 0.200984 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses
548c548
< system.cpu.iq.int_alu_accesses 8538 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses
552c552
< system.cpu.iew.lsq.thread0.squashedLoads 779 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed
562c562
< system.cpu.iew.iewBlockCycles 356 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking
564c564
< system.cpu.iew.iewDispatchedInsts 8400 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ
566c566
< system.cpu.iew.iewDispLoadInsts 1806 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions
575c575
< system.cpu.iew.iewExecutedInsts 6741 # Number of executed instructions
---
> system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions
577c577
< system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
583,587c583,587
< system.cpu.iew.exec_rate 0.189594 # Inst execution rate
< system.cpu.iew.wb_sent 6608 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 6566 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 2973 # num instructions producing a value
< system.cpu.iew.wb_consumers 5368 # num instructions consuming a value
---
> system.cpu.iew.exec_rate 0.189622 # Inst execution rate
> system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 6567 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 2975 # num instructions producing a value
> system.cpu.iew.wb_consumers 5372 # num instructions consuming a value
589,590c589,590
< system.cpu.iew.wb_rate 0.184672 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.553838 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back
592c592
< system.cpu.commit.commitSquashedInsts 2565 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit
595,597c595,597
< system.cpu.commit.committed_per_cycle::samples 14437 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.372515 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.021269 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle
599,605c599,605
< system.cpu.commit.committed_per_cycle::0 11787 81.64% 81.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1388 9.61% 91.26% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 602 4.17% 95.43% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 293 2.03% 97.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 168 1.16% 98.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 78 0.54% 99.16% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 45 0.31% 99.47% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle
611c611
< system.cpu.commit.committed_per_cycle::total 14437 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle
658,659c658,659
< system.cpu.rob.rob_reads 22180 # The number of ROB reads
< system.cpu.rob.rob_writes 16432 # The number of ROB writes
---
> system.cpu.rob.rob_reads 22320 # The number of ROB reads
> system.cpu.rob.rob_writes 16439 # The number of ROB writes
661c661
< system.cpu.idleCycles 20577 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling
668c668
< system.cpu.int_regfile_reads 6717 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 6718 # number of integer regfile reads
671,672c671,672
< system.cpu.cc_regfile_reads 23956 # number of cc regfile reads
< system.cpu.cc_regfile_writes 2895 # number of cc regfile writes
---
> system.cpu.cc_regfile_reads 23959 # number of cc regfile reads
> system.cpu.cc_regfile_writes 2898 # number of cc regfile writes
676c676
< system.cpu.dcache.tags.tagsinuse 84.382295 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use
681,683c681,683
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.382295 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.164809 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.164809 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy
714,715c714,715
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 7245500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 7245500 # number of WriteReq miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles
718,721c718,721
< system.cpu.dcache.demand_miss_latency::cpu.data 16445000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16445000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16445000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16445000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles
746,747c746,747
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37934.554974 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37934.554974 # average WriteReq miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency
750,753c750,753
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 45935.754190 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 45935.754190 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency
755c755
< system.cpu.dcache.blocked_cycles::no_targets 731 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked
759c759
< system.cpu.dcache.avg_blocked_cycles::no_targets 40.611111 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 46.055556 # average number of cycles each access was blocked
782,787c782,787
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2385500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2385500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8215000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8215000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8215000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8215000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles
798,803c798,803
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58182.926829 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58182.926829 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
806c806
< system.cpu.icache.tags.tagsinuse 136.424572 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use
811,813c811,813
< system.cpu.icache.tags.occ_blocks::cpu.inst 136.424572 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.266454 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.266454 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy
815,816c815,816
< system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
832,837c832,837
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21691493 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21691493 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21691493 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21691493 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21691493 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21691493 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles
850,856c850,856
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59592.013736 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 59592.013736 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 59592.013736 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 59592.013736 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 8521 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked
860c860
< system.cpu.icache.avg_blocked_cycles::no_mshrs 95.741573 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked
876,881c876,881
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18899993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 18899993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18899993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 18899993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18899993 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 18899993 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles
888,893c888,893
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63851.327703 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63851.327703 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
902c902
< system.cpu.l2cache.tags.tagsinuse 193.028614 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use
907,913c907,913
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.716720 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 45.124038 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.187855 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008467 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.002754 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000561 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.011782 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002752 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy
918,919c918,919
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id
948,951c948,951
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2251000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2251000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18451000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 18451000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2320000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2320000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles
954,959c954,959
< system.cpu.l2cache.demand_miss_latency::cpu.inst 18451000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7800000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 26251000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 18451000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7800000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 26251000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7869000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7869000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles
984,987c984,987
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75033.333333 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75033.333333 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67586.080586 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67586.080586 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency
990,995c990,995
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68007.772021 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68007.772021 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency
1029,1034c1029,1034
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1697924 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16769500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16769500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles
1037,1043c1037,1043
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16769500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6859500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23629000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16769500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6859500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 25326924 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles
1059,1064c1059,1064
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35373.416667 # average HardPFReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69033.333333 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69033.333333 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61652.573529 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61652.573529 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency
1067,1073c1067,1073
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62181.578947 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59175.056075 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency
1125c1125
< system.membus.reqLayer0.occupancy 510442 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks)
1127c1127
< system.membus.respLayer1.occupancy 2136258 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks)
< host_inst_rate 63568 # Simulator instruction rate (inst/s)
< host_op_rate 74435 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 246000775 # Simulator tick rate (ticks/s)
< host_mem_usage 307848 # Number of bytes of host memory used
---
> host_inst_rate 63242 # Simulator instruction rate (inst/s)
> host_op_rate 74054 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 244740900 # Simulator tick rate (ticks/s)
> host_mem_usage 307828 # Number of bytes of host memory used
97c97
< system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see
100c100
< system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
103c103
< system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
106c106
< system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see
207,208c207,208
< system.physmem.totQLat 3256492 # Total ticks spent queuing
< system.physmem.totMemAccLat 10887742 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3130500 # Total ticks spent queuing
> system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM
210c210
< system.physmem.avgQLat 8001.21 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst
212c212
< system.physmem.avgMemAccLat 26751.21 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst
221c221
< system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing
234c234
< system.physmem_0.actBackEnergy 10756755 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 14336940 # Total energy per rank (pJ)
< system.physmem_0.averagePower 905.538607 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 334000 # Time in different power states
---
> system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ)
> system.physmem_0.averagePower 905.346375 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states
241c241
< system.physmem_0.memoryStateTime::ACT 15275500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states
248,252c248,252
< system.physmem_1.actBackEnergy 10156545 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 590250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 12758160 # Total energy per rank (pJ)
< system.physmem_1.averagePower 805.820938 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 942000 # Time in different power states
---
> system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ)
> system.physmem_1.averagePower 805.767883 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states
255c255
< system.physmem_1.memoryStateTime::ACT 14384250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states
387c387
< system.cpu.fetch.icacheStallCycles 6172 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss
391c391
< system.cpu.fetch.Cycles 7501 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked
398,400c398,400
< system.cpu.fetch.rateDist::samples 14978 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.878021 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.210560 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total)
402,405c402,405
< system.cpu.fetch.rateDist::0 8782 58.63% 58.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2458 16.41% 75.04% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 521 3.48% 78.52% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 3217 21.48% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total)
409c409
< system.cpu.fetch.rateDist::total 14978 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total)
413,414c413,414
< system.cpu.decode.BlockedCycles 3520 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 5039 # Number of cycles decode is running
---
> system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 5038 # Number of cycles decode is running
419,420c419,420
< system.cpu.decode.DecodedInsts 9859 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 1620 # Number of squashed instructions handled by decode
---
> system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode
423c423
< system.cpu.rename.BlockCycles 960 # Number of cycles rename is blocking
---
> system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking
425,428c425,428
< system.cpu.rename.RunCycles 4095 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 601 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 8880 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 409 # Number of squashed instructions processed by rename
---
> system.cpu.rename.RunCycles 4094 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename
432,435c432,435
< system.cpu.rename.SQFullEvents 527 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 9231 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 40283 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 9759 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups
438c438
< system.cpu.rename.UndoneMaps 3737 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing
442c442
< system.cpu.memDep0.insertedLoads 1806 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit.
446c446
< system.cpu.iq.iqInstsAdded 8347 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec)
448c448
< system.cpu.iq.iqInstsIssued 7144 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued
450,451c450,451
< system.cpu.iq.iqSquashedInstsExamined 3008 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 7841 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph
453,455c453,455
< system.cpu.iq.issued_per_cycle::samples 14978 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.476966 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.861224 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle
457,460c457,460
< system.cpu.iq.issued_per_cycle::0 10780 71.97% 71.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1947 13.00% 84.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1601 10.69% 95.66% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 605 4.04% 99.70% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle
469c469
< system.cpu.iq.issued_per_cycle::total 14978 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle
471,501c471,501
< system.cpu.iq.fu_full::IntAlu 411 28.90% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 464 32.63% 61.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 547 38.47% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available
505,529c505,529
< system.cpu.iq.FU_type_0::IntAlu 4467 62.53% 62.53% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued
534c534
< system.cpu.iq.FU_type_0::MemRead 1588 22.23% 84.87% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued
538,544c538,544
< system.cpu.iq.FU_type_0::total 7144 # Type of FU issued
< system.cpu.iq.rate 0.200928 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1422 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.199048 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30828 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 11385 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 7146 # Type of FU issued
> system.cpu.iq.rate 0.200984 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses
548c548
< system.cpu.iq.int_alu_accesses 8538 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses
552c552
< system.cpu.iew.lsq.thread0.squashedLoads 779 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed
562c562
< system.cpu.iew.iewBlockCycles 356 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking
564c564
< system.cpu.iew.iewDispatchedInsts 8400 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ
566c566
< system.cpu.iew.iewDispLoadInsts 1806 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions
575c575
< system.cpu.iew.iewExecutedInsts 6741 # Number of executed instructions
---
> system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions
577c577
< system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
583,587c583,587
< system.cpu.iew.exec_rate 0.189594 # Inst execution rate
< system.cpu.iew.wb_sent 6608 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 6566 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 2973 # num instructions producing a value
< system.cpu.iew.wb_consumers 5368 # num instructions consuming a value
---
> system.cpu.iew.exec_rate 0.189622 # Inst execution rate
> system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 6567 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 2975 # num instructions producing a value
> system.cpu.iew.wb_consumers 5372 # num instructions consuming a value
589,590c589,590
< system.cpu.iew.wb_rate 0.184672 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.553838 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back
592c592
< system.cpu.commit.commitSquashedInsts 2565 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit
595,597c595,597
< system.cpu.commit.committed_per_cycle::samples 14437 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.372515 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.021269 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle
599,605c599,605
< system.cpu.commit.committed_per_cycle::0 11787 81.64% 81.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1388 9.61% 91.26% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 602 4.17% 95.43% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 293 2.03% 97.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 168 1.16% 98.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 78 0.54% 99.16% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 45 0.31% 99.47% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle
611c611
< system.cpu.commit.committed_per_cycle::total 14437 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle
658,659c658,659
< system.cpu.rob.rob_reads 22180 # The number of ROB reads
< system.cpu.rob.rob_writes 16432 # The number of ROB writes
---
> system.cpu.rob.rob_reads 22320 # The number of ROB reads
> system.cpu.rob.rob_writes 16439 # The number of ROB writes
661c661
< system.cpu.idleCycles 20577 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling
668c668
< system.cpu.int_regfile_reads 6717 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 6718 # number of integer regfile reads
671,672c671,672
< system.cpu.cc_regfile_reads 23956 # number of cc regfile reads
< system.cpu.cc_regfile_writes 2895 # number of cc regfile writes
---
> system.cpu.cc_regfile_reads 23959 # number of cc regfile reads
> system.cpu.cc_regfile_writes 2898 # number of cc regfile writes
676c676
< system.cpu.dcache.tags.tagsinuse 84.382295 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use
681,683c681,683
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.382295 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.164809 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.164809 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy
714,715c714,715
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 7245500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 7245500 # number of WriteReq miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles
718,721c718,721
< system.cpu.dcache.demand_miss_latency::cpu.data 16445000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16445000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16445000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16445000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles
746,747c746,747
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37934.554974 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37934.554974 # average WriteReq miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency
750,753c750,753
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 45935.754190 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 45935.754190 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency
755c755
< system.cpu.dcache.blocked_cycles::no_targets 731 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked
759c759
< system.cpu.dcache.avg_blocked_cycles::no_targets 40.611111 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 46.055556 # average number of cycles each access was blocked
782,787c782,787
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2385500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2385500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8215000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8215000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8215000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8215000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles
798,803c798,803
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58182.926829 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58182.926829 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
806c806
< system.cpu.icache.tags.tagsinuse 136.424572 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use
811,813c811,813
< system.cpu.icache.tags.occ_blocks::cpu.inst 136.424572 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.266454 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.266454 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy
815,816c815,816
< system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
832,837c832,837
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21691493 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21691493 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21691493 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21691493 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21691493 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21691493 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles
850,856c850,856
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59592.013736 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 59592.013736 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 59592.013736 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 59592.013736 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 8521 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked
860c860
< system.cpu.icache.avg_blocked_cycles::no_mshrs 95.741573 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked
876,881c876,881
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18899993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 18899993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18899993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 18899993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18899993 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 18899993 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles
888,893c888,893
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63851.327703 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63851.327703 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
902c902
< system.cpu.l2cache.tags.tagsinuse 193.028614 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use
907,913c907,913
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.716720 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 45.124038 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.187855 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008467 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.002754 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000561 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.011782 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002752 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy
918,919c918,919
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id
948,951c948,951
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2251000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2251000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18451000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 18451000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2320000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2320000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles
954,959c954,959
< system.cpu.l2cache.demand_miss_latency::cpu.inst 18451000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7800000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 26251000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 18451000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7800000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 26251000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7869000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7869000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles
984,987c984,987
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75033.333333 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75033.333333 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67586.080586 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67586.080586 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency
990,995c990,995
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68007.772021 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68007.772021 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency
1029,1034c1029,1034
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1697924 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16769500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16769500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles
1037,1043c1037,1043
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16769500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6859500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23629000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16769500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6859500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 25326924 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles
1059,1064c1059,1064
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35373.416667 # average HardPFReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69033.333333 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69033.333333 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61652.573529 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61652.573529 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency
1067,1073c1067,1073
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62181.578947 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59175.056075 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency
1125c1125
< system.membus.reqLayer0.occupancy 510442 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks)
1127c1127
< system.membus.respLayer1.occupancy 2136258 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks)