3,5c3,5
< sim_seconds 0.000016 # Number of seconds simulated
< sim_ticks 16223000 # Number of ticks simulated
< final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000012 # Number of seconds simulated
> sim_ticks 11859500 # Number of ticks simulated
> final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 35590 # Simulator instruction rate (inst/s)
< host_op_rate 41676 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 125719954 # Simulator tick rate (ticks/s)
< host_mem_usage 252016 # Number of bytes of host memory used
< host_seconds 0.13 # Real time elapsed on the host
---
> host_inst_rate 50616 # Simulator instruction rate (inst/s)
> host_op_rate 59274 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 130716325 # Simulator tick rate (ticks/s)
> host_mem_usage 300356 # Number of bytes of host memory used
> host_seconds 0.09 # Real time elapsed on the host
16,32c16,36
< system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
< system.physmem.bytes_read::total 25408 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 397 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 397 # Number of read requests accepted
---
> system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory
> system.physmem.bytes_read::total 46848 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 732 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 733 # Number of read requests accepted
34c38
< system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue
36c40
< system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM
39c43
< system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side
44,57c48,61
< system.physmem.perBankRdBursts::0 90 # Per bank write bursts
< system.physmem.perBankRdBursts::1 46 # Per bank write bursts
< system.physmem.perBankRdBursts::2 20 # Per bank write bursts
< system.physmem.perBankRdBursts::3 43 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18 # Per bank write bursts
< system.physmem.perBankRdBursts::5 32 # Per bank write bursts
< system.physmem.perBankRdBursts::6 35 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10 # Per bank write bursts
< system.physmem.perBankRdBursts::8 4 # Per bank write bursts
< system.physmem.perBankRdBursts::9 8 # Per bank write bursts
< system.physmem.perBankRdBursts::10 28 # Per bank write bursts
< system.physmem.perBankRdBursts::11 42 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9 # Per bank write bursts
< system.physmem.perBankRdBursts::13 6 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 143 # Per bank write bursts
> system.physmem.perBankRdBursts::1 90 # Per bank write bursts
> system.physmem.perBankRdBursts::2 40 # Per bank write bursts
> system.physmem.perBankRdBursts::3 73 # Per bank write bursts
> system.physmem.perBankRdBursts::4 58 # Per bank write bursts
> system.physmem.perBankRdBursts::5 88 # Per bank write bursts
> system.physmem.perBankRdBursts::6 52 # Per bank write bursts
> system.physmem.perBankRdBursts::7 18 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12 # Per bank write bursts
> system.physmem.perBankRdBursts::9 28 # Per bank write bursts
> system.physmem.perBankRdBursts::10 34 # Per bank write bursts
> system.physmem.perBankRdBursts::11 47 # Per bank write bursts
> system.physmem.perBankRdBursts::12 17 # Per bank write bursts
> system.physmem.perBankRdBursts::13 19 # Per bank write bursts
59c63
< system.physmem.perBankRdBursts::15 6 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 14 # Per bank write bursts
78c82
< system.physmem.totGap 16156000 # Total gap between requests
---
> system.physmem.totGap 11846500 # Total gap between requests
85c89
< system.physmem.readPktSize::6 397 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 733 # Read request sizes (log2)
93,108c97,112
< system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
189,205c193,210
< system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
< system.physmem.totQLat 2970000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation
> system.physmem.totQLat 17284989 # Total ticks spent queuing
> system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst
207,208c212,213
< system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s
210c215
< system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s
213,214c218,219
< system.physmem.busUtil 12.24 # Data bus utilization in percentage
< system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 30.90 # Data bus utilization in percentage
> system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads
216c221
< system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing
218c223
< system.physmem.readRowHits 331 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 662 # Number of row buffer hits during reads
220c225
< system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads
222,225c227,230
< system.physmem.avgGap 40695.21 # Average gap between requests
< system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
< system.physmem.memoryStateTime::REF 520000 # Time in different power states
---
> system.physmem.avgGap 16161.66 # Average gap between requests
> system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 6500 # Time in different power states
> system.physmem.memoryStateTime::REF 260000 # Time in different power states
227c232
< system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 7800750 # Time in different power states
229,243c234,256
< system.membus.throughput 1566171485 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 355 # Transaction distribution
< system.membus.trans_dist::ReadResp 355 # Transaction distribution
< system.membus.trans_dist::ReadExReq 42 # Transaction distribution
< system.membus.trans_dist::ReadExResp 42 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 25408 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 22.8 # Layer utilization (%)
---
> system.membus.trans_dist::ReadReq 704 # Transaction distribution
> system.membus.trans_dist::ReadResp 702 # Transaction distribution
> system.membus.trans_dist::ReadExReq 29 # Transaction distribution
> system.membus.trans_dist::ReadExResp 29 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 733 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 733 # Request fanout histogram
> system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 6.8 # Layer utilization (%)
> system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 55.9 # Layer utilization (%)
245,249c258,262
< system.cpu.branchPred.lookups 2638 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 783 # Number of BTB hits
---
> system.cpu.branchPred.lookups 2560 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 497 # Number of BTB hits
251,253c264,266
< system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions.
339c352
< system.cpu.numCycles 32447 # number of cpu cycles simulated
---
> system.cpu.numCycles 23720 # number of cpu cycles simulated
342,355c355,368
< system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total)
357,365c370,373
< system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total)
368,394c376,404
< system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2145 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2064 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename
< system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 5106 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 4105 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups
396,413c406,423
< system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 43 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle
415,423c425,433
< system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
426,427c436,437
< system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle
429,459c439,469
< system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available
463,493c473,503
< system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued
496,508c506,518
< system.cpu.iq.FU_type_0::total 8358 # Type of FU issued
< system.cpu.iq.rate 0.257589 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 169 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 7242 # Type of FU issued
> system.cpu.iq.rate 0.305312 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores
510,513c520,523
< system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed
516,517c526,527
< system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked
519,535c529,545
< system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute
537,545c547,555
< system.cpu.iew.exec_nop 11 # number of nop insts executed
< system.cpu.iew.exec_refs 3148 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1457 # Number of branches executed
< system.cpu.iew.exec_stores 1240 # Number of stores executed
< system.cpu.iew.exec_rate 0.248498 # Inst execution rate
< system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 7601 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 3572 # num instructions producing a value
< system.cpu.iew.wb_consumers 6998 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 14 # number of nop insts executed
> system.cpu.iew.exec_refs 2449 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1283 # Number of branches executed
> system.cpu.iew.exec_stores 1021 # Number of stores executed
> system.cpu.iew.exec_rate 0.287858 # Inst execution rate
> system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 6654 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 3045 # num instructions producing a value
> system.cpu.iew.wb_consumers 5519 # num instructions consuming a value
547,548c557,558
< system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back
550c560
< system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit
552,555c562,565
< system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle
557,565c567,575
< system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle
569c579
< system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle
615c625
< system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached
617,620c627,630
< system.cpu.rob.rob_reads 22692 # The number of ROB reads
< system.cpu.rob.rob_writes 21719 # The number of ROB writes
< system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 24066 # The number of ROB reads
> system.cpu.rob.rob_writes 16749 # The number of ROB writes
> system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling
623,632c633,642
< system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 7944 # number of integer regfile reads
< system.cpu.int_regfile_writes 4420 # number of integer regfile writes
< system.cpu.fp_regfile_reads 31 # number of floating regfile reads
< system.cpu.cc_regfile_reads 28734 # number of cc regfile reads
< system.cpu.cc_regfile_writes 3302 # number of cc regfile writes
< system.cpu.misc_regfile_reads 3189 # number of misc regfile reads
---
> system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 6786 # number of integer regfile reads
> system.cpu.int_regfile_writes 3839 # number of integer regfile writes
> system.cpu.fp_regfile_reads 16 # number of floating regfile reads
> system.cpu.cc_regfile_reads 24301 # number of cc regfile reads
> system.cpu.cc_regfile_writes 2919 # number of cc regfile writes
> system.cpu.misc_regfile_reads 2642 # number of misc regfile reads
634,657c644,681
< system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
< system.cpu.icache.tags.replacements 1 # number of replacements
< system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks.
---
> system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 1026 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%)
> system.cpu.icache.tags.replacements 47 # number of replacements
> system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks.
659,704c683,728
< system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4430 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits
< system.cpu.icache.overall_hits::total 1666 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses
< system.cpu.icache.overall_misses::total 402 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 138.950029 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.271387 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.271387 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 8536 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 8536 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 3784 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 3784 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 3784 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 3784 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 3784 # number of overall hits
> system.cpu.icache.overall_hits::total 3784 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 332 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 332 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 332 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 332 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 332 # number of overall misses
> system.cpu.icache.overall_misses::total 332 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 7426247 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 7426247 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 7426247 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 7426247 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 7426247 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 7426247 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 4116 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 4116 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 4116 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 4116 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 4116 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 4116 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080661 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.080661 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.080661 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.080661 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.080661 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.080661 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22368.213855 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 22368.213855 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 22368.213855 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 22368.213855 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 1112 # number of cycles access was blocked
706c730
< system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked
708c732
< system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 16.848485 # average number of cycles each access was blocked
712,741c736,765
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 28 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6489997 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 6489997 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6489997 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 6489997 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6489997 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 6489997 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.073858 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.073858 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.073858 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21348.674342 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21348.674342 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency
742a767,775
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 2346 # number of hwpf identified
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 489 # number of hwpf that were already in mshr
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 1139 # number of hwpf that were already in the cache
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86 # number of hwpf that were already in the prefetch queue
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 29 # number of hwpf removed because MSHR allocated
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 603 # number of hwpf issued
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 198 # number of hwpf spanning a virtual page
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
744,747c777,780
< system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 370.948422 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 270 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 691 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.390738 # Average number of references to valid blocks.
749,824c782,865
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
< system.cpu.l2cache.overall_hits::total 39 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 360 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
< system.cpu.l2cache.overall_misses::total 402 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19251250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6010750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19251250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9112500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19251250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9112500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935374 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.449811 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 36.598805 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 303.899806 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001859 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002234 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.018549 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.022641 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 570 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 121 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 471 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 99 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.034790 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007385 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 7899 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 7899 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 234 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 35 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 269 # number of ReadReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 234 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 46 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 280 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 234 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 46 # number of overall hits
> system.cpu.l2cache.overall_hits::total 280 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 70 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 69 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 139 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 29 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 29 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 70 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 98 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 168 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 70 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 98 # number of overall misses
> system.cpu.l2cache.overall_misses::total 168 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 4724750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5170750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 9895500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2577500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2577500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 4724750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7748250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12473000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 4724750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7748250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12473000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 40 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 40 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 448 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 448 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.230263 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.663462 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.340686 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.725000 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.725000 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.230263 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.680556 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.375000 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.230263 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.680556 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.375000 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67496.428571 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74938.405797 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 71190.647482 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88879.310345 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88879.310345 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74244.047619 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74244.047619 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 388 # number of cycles access was blocked
826c867
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked
828c869
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.823529 # average number of cycles each access was blocked
832,881c873,937
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 59 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 603 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 603 # number of HardPFReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 29 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 59 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 92 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 59 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 92 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 603 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 754 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 3978500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4478500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8457000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 49457864 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2337500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2337500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 3978500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6816000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10794500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 3978500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6816000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 60252364 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.605769 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299020 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
> system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency
883,887c939,943
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 1 # number of replacements
> system.cpu.dcache.tags.tagsinuse 82.309019 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1894 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 13.244755 # Average number of references to valid blocks.
889,903c945,959
< system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
906,913c962,969
< system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits
< system.cpu.dcache.overall_hits::total 2146 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits
> system.cpu.dcache.overall_hits::total 1873 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses
916,931c972,987
< system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses
< system.cpu.dcache.overall_misses::total 521 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses
> system.cpu.dcache.overall_misses::total 392 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses)
934,935c990,991
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
938,967c994,1023
< system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked
970,973c1026,1029
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits
976,1011c1032,1067
< system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency