4,5c4,5
< sim_ticks 17056000 # Number of ticks simulated
< final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 16955000 # Number of ticks simulated
> final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 53685 # Simulator instruction rate (inst/s)
< host_op_rate 66982 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 199380443 # Simulator tick rate (ticks/s)
< host_mem_usage 308976 # Number of bytes of host memory used
---
> host_inst_rate 52426 # Simulator instruction rate (inst/s)
> host_op_rate 65410 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 193552438 # Simulator tick rate (ticks/s)
> host_mem_usage 308400 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 16998500 # Total gap between requests
---
> system.physmem.totGap 16897500 # Total gap between requests
93,95c93,95
< system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
189,202c189,204
< system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation
< system.physmem.totQLat 4223500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
> system.physmem.totQLat 3795000 # Total ticks spent queuing
> system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM
204,206c206
< system.physmem.totBankLat 5431250 # Total ticks spent accessing banks
< system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 11.49 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.56 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads
217c217
< system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing
223c223
< system.physmem.avgGap 43363.52 # Average gap between requests
---
> system.physmem.avgGap 43105.87 # Average gap between requests
225,226c225,230
< system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1467166979 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15324750 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1475906812 # Throughput (bytes/s)
238,240c242,244
< system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 21.4 # Layer utilization (%)
---
> system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
> system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
336c340
< system.cpu.numCycles 34113 # number of cpu cycles simulated
---
> system.cpu.numCycles 33911 # number of cpu cycles simulated
339c343
< system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss
345c349
< system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked
348,350c352,354
< system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total)
352,360c356,364
< system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total)
364,368c368,372
< system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked
---
> system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked
377c381
< system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle
379c383
< system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst
---
> system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst
406,408c410,412
< system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle
410,413c414,417
< system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle
415,416c419,420
< system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle
422c426
< system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle
492c496
< system.cpu.iq.rate 0.261513 # Inst issue rate
---
> system.cpu.iq.rate 0.263071 # Inst issue rate
495c499
< system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads
528,530c532,534
< system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
533c537
< system.cpu.iew.exec_refs 3299 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
536c540
< system.cpu.iew.exec_rate 0.249846 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.251364 # Inst execution rate
540c544
< system.cpu.iew.wb_consumers 7788 # num instructions consuming a value
---
> system.cpu.iew.wb_consumers 7789 # num instructions consuming a value
542,543c546,547
< system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back
548,550c552,554
< system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle
552,554c556,558
< system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle
556c560
< system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle
559,560c563,564
< system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle
564c568
< system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle
574a579,613
> system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 5729 # Class of committed instruction
577c616
< system.cpu.rob.rob_reads 23225 # The number of ROB reads
---
> system.cpu.rob.rob_reads 23248 # The number of ROB reads
579,580c618,619
< system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling
584,588c623,627
< system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 39210 # number of integer regfile reads
---
> system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 39214 # number of integer regfile reads
593c632
< system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s)
608c647
< system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks)
610,611c649,650
< system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
613c652
< system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use
618,620c657,659
< system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy
622,623c661,662
< system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
639,644c678,683
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles
657,662c696,701
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency
683,688c722,727
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles
695,700c734,739
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
703c742
< system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use
708,712c747,751
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy
714,715c753,754
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
739,741c778,780
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles
744,749c783,788
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles
772,774c811,813
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency
777,782c816,821
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency
808,810c847,849
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles
813,818c852,857
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles
830,832c869,871
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency
835,840c874,879
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
843,844c882,883
< system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
846c885
< system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks.
848,850c887,889
< system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy
855,856c894,895
< system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses
861,862c900,901
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
---
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
879,880c918,919
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles
885,888c924,927
< system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles
893,894c932,933
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
905,906c944,945
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
911,912c950,951
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency
917,920c956,959
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency
947,948c986,987
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles
951,954c990,993
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles
963,964c1002,1003
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency
967,970c1006,1009
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
< sim_ticks 17056000 # Number of ticks simulated
< final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 16955000 # Number of ticks simulated
> final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 53685 # Simulator instruction rate (inst/s)
< host_op_rate 66982 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 199380443 # Simulator tick rate (ticks/s)
< host_mem_usage 308976 # Number of bytes of host memory used
---
> host_inst_rate 52426 # Simulator instruction rate (inst/s)
> host_op_rate 65410 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 193552438 # Simulator tick rate (ticks/s)
> host_mem_usage 308400 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 16998500 # Total gap between requests
---
> system.physmem.totGap 16897500 # Total gap between requests
93,95c93,95
< system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
189,202c189,204
< system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation
< system.physmem.totQLat 4223500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
> system.physmem.totQLat 3795000 # Total ticks spent queuing
> system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM
204,206c206
< system.physmem.totBankLat 5431250 # Total ticks spent accessing banks
< system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 11.49 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.56 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads
217c217
< system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing
223c223
< system.physmem.avgGap 43363.52 # Average gap between requests
---
> system.physmem.avgGap 43105.87 # Average gap between requests
225,226c225,230
< system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1467166979 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15324750 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1475906812 # Throughput (bytes/s)
238,240c242,244
< system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 21.4 # Layer utilization (%)
---
> system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
> system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
336c340
< system.cpu.numCycles 34113 # number of cpu cycles simulated
---
> system.cpu.numCycles 33911 # number of cpu cycles simulated
339c343
< system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss
345c349
< system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked
348,350c352,354
< system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total)
352,360c356,364
< system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total)
364,368c368,372
< system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked
---
> system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked
377c381
< system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle
379c383
< system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst
---
> system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst
406,408c410,412
< system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle
410,413c414,417
< system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle
415,416c419,420
< system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle
422c426
< system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle
492c496
< system.cpu.iq.rate 0.261513 # Inst issue rate
---
> system.cpu.iq.rate 0.263071 # Inst issue rate
495c499
< system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads
528,530c532,534
< system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
533c537
< system.cpu.iew.exec_refs 3299 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
536c540
< system.cpu.iew.exec_rate 0.249846 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.251364 # Inst execution rate
540c544
< system.cpu.iew.wb_consumers 7788 # num instructions consuming a value
---
> system.cpu.iew.wb_consumers 7789 # num instructions consuming a value
542,543c546,547
< system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back
548,550c552,554
< system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle
552,554c556,558
< system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle
556c560
< system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle
559,560c563,564
< system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle
564c568
< system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle
574a579,613
> system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 5729 # Class of committed instruction
577c616
< system.cpu.rob.rob_reads 23225 # The number of ROB reads
---
> system.cpu.rob.rob_reads 23248 # The number of ROB reads
579,580c618,619
< system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling
584,588c623,627
< system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 39210 # number of integer regfile reads
---
> system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 39214 # number of integer regfile reads
593c632
< system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s)
608c647
< system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks)
610,611c649,650
< system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
613c652
< system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use
618,620c657,659
< system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy
622,623c661,662
< system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
639,644c678,683
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles
657,662c696,701
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency
683,688c722,727
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles
695,700c734,739
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
703c742
< system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use
708,712c747,751
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy
714,715c753,754
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
739,741c778,780
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles
744,749c783,788
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles
772,774c811,813
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency
777,782c816,821
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency
808,810c847,849
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles
813,818c852,857
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles
830,832c869,871
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency
835,840c874,879
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
843,844c882,883
< system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
846c885
< system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks.
848,850c887,889
< system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy
855,856c894,895
< system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses
861,862c900,901
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
---
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
879,880c918,919
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles
885,888c924,927
< system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles
893,894c932,933
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
905,906c944,945
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
911,912c950,951
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency
917,920c956,959
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency
947,948c986,987
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles
951,954c990,993
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles
963,964c1002,1003
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency
967,970c1006,1009
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency