7,11c7,11
< host_inst_rate 34743 # Simulator instruction rate (inst/s)
< host_op_rate 43351 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 128481440 # Simulator tick rate (ticks/s)
< host_mem_usage 246872 # Number of bytes of host memory used
< host_seconds 0.13 # Real time elapsed on the host
---
> host_inst_rate 45620 # Simulator instruction rate (inst/s)
> host_op_rate 56920 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 168691831 # Simulator tick rate (ticks/s)
> host_mem_usage 267756 # Number of bytes of host memory used
> host_seconds 0.10 # Real time elapsed on the host
229a230,250
> system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
250a272,292
> system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
324c366
< system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made
---
> system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made
341c383
< system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
528c570
< system.cpu.misc_regfile_reads 2977 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 3239 # number of misc regfile reads
< host_inst_rate 34743 # Simulator instruction rate (inst/s)
< host_op_rate 43351 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 128481440 # Simulator tick rate (ticks/s)
< host_mem_usage 246872 # Number of bytes of host memory used
< host_seconds 0.13 # Real time elapsed on the host
---
> host_inst_rate 45620 # Simulator instruction rate (inst/s)
> host_op_rate 56920 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 168691831 # Simulator tick rate (ticks/s)
> host_mem_usage 267756 # Number of bytes of host memory used
> host_seconds 0.10 # Real time elapsed on the host
229a230,250
> system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
250a272,292
> system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
324c366
< system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made
---
> system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made
341c383
< system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
528c570
< system.cpu.misc_regfile_reads 2977 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 3239 # number of misc regfile reads