12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 443 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 986132512 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 428457574 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 91812337 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 1506402423 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 986132512 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 986132512 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 986132512 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 428457574 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 91812337 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 1506402423 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 443 # Number of read requests accepted 37system.physmem.writeReqs 0 # Number of write requests accepted 38system.physmem.readBursts 443 # Number of DRAM read bursts, including those serviced by the write queue 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 40system.physmem.bytesReadDRAM 28352 # Total number of bytes read from DRAM 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 43system.physmem.bytesReadSys 28352 # Total read bytes from the system interface side 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 101 # Per bank write bursts 49system.physmem.perBankRdBursts::1 48 # Per bank write bursts 50system.physmem.perBankRdBursts::2 19 # Per bank write bursts 51system.physmem.perBankRdBursts::3 45 # Per bank write bursts 52system.physmem.perBankRdBursts::4 19 # Per bank write bursts 53system.physmem.perBankRdBursts::5 37 # Per bank write bursts 54system.physmem.perBankRdBursts::6 46 # Per bank write bursts 55system.physmem.perBankRdBursts::7 10 # Per bank write bursts 56system.physmem.perBankRdBursts::8 4 # Per bank write bursts 57system.physmem.perBankRdBursts::9 8 # Per bank write bursts 58system.physmem.perBankRdBursts::10 27 # Per bank write bursts 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts 60system.physmem.perBankRdBursts::12 17 # Per bank write bursts 61system.physmem.perBankRdBursts::13 8 # Per bank write bursts 62system.physmem.perBankRdBursts::14 0 # Per bank write bursts 63system.physmem.perBankRdBursts::15 7 # Per bank write bursts 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 82system.physmem.totGap 18779500 # Total gap between requests 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) 89system.physmem.readPktSize::6 443 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) 97system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 193system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 427.682540 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 292.140083 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 354.445538 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 18 28.57% 39.68% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 1 1.59% 69.84% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 4 6.35% 76.19% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 207system.physmem.totQLat 3401243 # Total ticks spent queuing 208system.physmem.totMemAccLat 11707493 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 2215000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 7677.75 # Average queueing delay per DRAM burst 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 212system.physmem.avgMemAccLat 26427.75 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 1506.40 # Average DRAM read bandwidth in MiByte/s 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 215system.physmem.avgRdBWSys 1506.40 # Average system read bandwidth in MiByte/s 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 11.77 # Data bus utilization in percentage 219system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 371 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes 225system.physmem.readRowHitRate 83.75 # Row buffer hit rate for reads 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 227system.physmem.avgGap 42391.65 # Average gap between requests 228system.physmem.pageHitRate 83.75 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 234system.physmem_0.actBackEnergy 10755900 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 64500 # Energy for precharge background per rank (pJ) 236system.physmem_0.totalEnergy 14453835 # Total energy per rank (pJ) 237system.physmem_0.averagePower 912.921838 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 51750 # Time in different power states 239system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 241system.physmem_0.memoryStateTime::ACT 15274500 # Time in different power states 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 248system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ) 251system.physmem_1.averagePower 811.289436 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states 253system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 2438 # Number of BP lookups 258system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 449 # Number of BTB hits 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 263system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 266system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. 267system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 268system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. 269system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. 270system.cpu_clk_domain.clock 500 # Clock period in ticks 271system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 280system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 281system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 282system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 283system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 284system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 285system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 286system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 287system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 288system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 289system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 290system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 291system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 292system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 293system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 294system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 295system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 296system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 297system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 298system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 299system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.inst_hits 0 # ITB inst hits 309system.cpu.dtb.inst_misses 0 # ITB inst misses 310system.cpu.dtb.read_hits 0 # DTB read hits 311system.cpu.dtb.read_misses 0 # DTB read misses 312system.cpu.dtb.write_hits 0 # DTB write hits 313system.cpu.dtb.write_misses 0 # DTB write misses 314system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 315system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 316system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 317system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 318system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 319system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 320system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses 329system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 338system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 339system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 340system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 341system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 342system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 343system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 344system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 345system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 346system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 347system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 348system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 349system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 350system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 351system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 352system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 353system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 354system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 355system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 356system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 357system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 358system.cpu.itb.walker.walks 0 # Table walker walks requested 359system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.inst_hits 0 # ITB inst hits 367system.cpu.itb.inst_misses 0 # ITB inst misses 368system.cpu.itb.read_hits 0 # DTB read hits 369system.cpu.itb.read_misses 0 # DTB read misses 370system.cpu.itb.write_hits 0 # DTB write hits 371system.cpu.itb.write_misses 0 # DTB write misses 372system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 373system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 374system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 375system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 376system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 377system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 378system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 379system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 380system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 381system.cpu.itb.read_accesses 0 # DTB read accesses 382system.cpu.itb.write_accesses 0 # DTB write accesses 383system.cpu.itb.inst_accesses 0 # ITB inst accesses 384system.cpu.itb.hits 0 # DTB hits 385system.cpu.itb.misses 0 # DTB misses 386system.cpu.itb.accesses 0 # DTB accesses 387system.cpu.workload.num_syscalls 13 # Number of system calls 388system.cpu.numCycles 37643 # number of cpu cycles simulated 389system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 390system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 391system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss 392system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed 393system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered 394system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken 395system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked 396system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing 397system.cpu.fetch.MiscStallCycles 169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 398system.cpu.fetch.PendingTrapStallCycles 272 # Number of stall cycles due to pending traps 399system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR 400system.cpu.fetch.CacheLines 3904 # Number of cache lines fetched 401system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed 402system.cpu.fetch.rateDist::samples 15772 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::mean 0.863365 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::stdev 1.208800 # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::0 9389 59.53% 59.53% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::1 2507 15.90% 75.42% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::2 518 3.28% 78.71% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::3 3358 21.29% 100.00% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::total 15772 # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.branchRate 0.064766 # Number of branch fetches per cycle 415system.cpu.fetch.rate 0.304280 # Number of inst fetches per cycle 416system.cpu.decode.IdleCycles 5832 # Number of cycles decode is idle 417system.cpu.decode.BlockedCycles 4243 # Number of cycles decode is blocked 418system.cpu.decode.RunCycles 5178 # Number of cycles decode is running 419system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking 420system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing 421system.cpu.decode.BranchResolved 373 # Number of times decode resolved a branch 422system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction 423system.cpu.decode.DecodedInsts 10169 # Number of instructions handled by decode 424system.cpu.decode.SquashedInsts 1675 # Number of squashed instructions handled by decode 425system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing 426system.cpu.rename.IdleCycles 6945 # Number of cycles rename is idle 427system.cpu.rename.BlockCycles 1086 # Number of cycles rename is blocking 428system.cpu.rename.serializeStallCycles 2318 # count of cycles rename stalled for serializing inst 429system.cpu.rename.RunCycles 4187 # Number of cycles rename is running 430system.cpu.rename.UnblockCycles 850 # Number of cycles rename is unblocking 431system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename 432system.cpu.rename.SquashedInsts 454 # Number of squashed instructions processed by rename 433system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full 434system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 435system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full 436system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full 437system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed 438system.cpu.rename.RenameLookups 41158 # Number of register rename lookups that rename has made 439system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups 440system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 441system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 442system.cpu.rename.UndoneMaps 3956 # Number of HB maps that are undone due to squashing 443system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 444system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 445system.cpu.rename.skidInsts 331 # count of insts added to the skid buffer 446system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. 447system.cpu.memDep0.insertedStores 1291 # Number of stores inserted to the mem dependence unit. 448system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 449system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 450system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec) 451system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ 452system.cpu.iq.iqInstsIssued 7234 # Number of instructions issued 453system.cpu.iq.iqSquashedInstsIssued 175 # Number of squashed instructions issued 454system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling 455system.cpu.iq.iqSquashedOperandsExamined 8237 # Number of squashed operands that are examined and possibly removed from graph 456system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed 457system.cpu.iq.issued_per_cycle::samples 15772 # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::mean 0.458661 # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::stdev 0.847067 # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::0 11502 72.93% 72.93% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::1 1999 12.67% 85.60% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::2 1621 10.28% 95.88% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::3 607 3.85% 99.73% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::total 15772 # Number of insts issued each cycle 474system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 475system.cpu.iq.fu_full::IntAlu 415 28.78% 28.78% # attempts to use FU when none available 476system.cpu.iq.fu_full::IntMult 0 0.00% 28.78% # attempts to use FU when none available 477system.cpu.iq.fu_full::IntDiv 0 0.00% 28.78% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.78% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.78% # attempts to use FU when none available 480system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.78% # attempts to use FU when none available 481system.cpu.iq.fu_full::FloatMult 0 0.00% 28.78% # attempts to use FU when none available 482system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.78% # attempts to use FU when none available 483system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.78% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.78% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.78% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.78% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.78% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.78% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.78% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdMult 0 0.00% 28.78% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.78% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdShift 0 0.00% 28.78% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.78% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.78% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.78% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.78% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.78% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.78% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.78% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.78% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.78% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.78% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.78% # attempts to use FU when none available 504system.cpu.iq.fu_full::MemRead 474 32.87% 61.65% # attempts to use FU when none available 505system.cpu.iq.fu_full::MemWrite 553 38.35% 100.00% # attempts to use FU when none available 506system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 507system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 508system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 509system.cpu.iq.FU_type_0::IntAlu 4534 62.68% 62.68% # Type of FU issued 510system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.75% # Type of FU issued 511system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.75% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.75% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.75% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.75% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.75% # Type of FU issued 516system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.75% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.75% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.75% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.75% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.75% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.75% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.75% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.75% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.75% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.75% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.75% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.75% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.75% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.75% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.75% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.75% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.75% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.75% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued 538system.cpu.iq.FU_type_0::MemRead 1605 22.19% 84.97% # Type of FU issued 539system.cpu.iq.FU_type_0::MemWrite 1087 15.03% 100.00% # Type of FU issued 540system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 541system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 542system.cpu.iq.FU_type_0::total 7234 # Type of FU issued 543system.cpu.iq.rate 0.192174 # Inst issue rate 544system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested 545system.cpu.iq.fu_busy_rate 0.199336 # FU busy rate (busy events/executed inst) 546system.cpu.iq.int_inst_queue_reads 31813 # Number of integer instruction queue reads 547system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes 548system.cpu.iq.int_inst_queue_wakeup_accesses 6621 # Number of integer instruction queue wakeup accesses 549system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads 550system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 551system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 552system.cpu.iq.int_alu_accesses 8648 # Number of integer alu accesses 553system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses 554system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores 555system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 556system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed 557system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 558system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 559system.cpu.iew.lsq.thread0.squashedStores 353 # Number of stores squashed 560system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 561system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 562system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 563system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 564system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 565system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing 566system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking 567system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking 568system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ 569system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 570system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions 571system.cpu.iew.iewDispStoreInsts 1291 # Number of dispatched store instructions 572system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 573system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 574system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 575system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 576system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly 577system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly 578system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 579system.cpu.iew.iewExecutedInsts 6824 # Number of executed instructions 580system.cpu.iew.iewExecLoadInsts 1421 # Number of load instructions executed 581system.cpu.iew.iewExecSquashedInsts 410 # Number of squashed instructions skipped in execute 582system.cpu.iew.exec_swp 0 # number of swp insts executed 583system.cpu.iew.exec_nop 13 # number of nop insts executed 584system.cpu.iew.exec_refs 2451 # number of memory reference insts executed 585system.cpu.iew.exec_branches 1299 # Number of branches executed 586system.cpu.iew.exec_stores 1030 # Number of stores executed 587system.cpu.iew.exec_rate 0.181282 # Inst execution rate 588system.cpu.iew.wb_sent 6681 # cumulative count of insts sent to commit 589system.cpu.iew.wb_count 6637 # cumulative count of insts written-back 590system.cpu.iew.wb_producers 2986 # num instructions producing a value 591system.cpu.iew.wb_consumers 5424 # num instructions consuming a value 592system.cpu.iew.wb_rate 0.176314 # insts written-back per cycle 593system.cpu.iew.wb_fanout 0.550516 # average fanout of values written-back 594system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit 595system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 596system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted 597system.cpu.commit.committed_per_cycle::samples 15204 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::mean 0.353723 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::stdev 0.993092 # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::0 12538 82.47% 82.47% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::1 1405 9.24% 91.71% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::2 597 3.93% 95.63% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::3 300 1.97% 97.61% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::4 170 1.12% 98.72% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::5 79 0.52% 99.24% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::total 15204 # Number of insts commited each cycle 614system.cpu.commit.committedInsts 4592 # Number of instructions committed 615system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 616system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 617system.cpu.commit.refs 1965 # Number of memory references committed 618system.cpu.commit.loads 1027 # Number of loads committed 619system.cpu.commit.membars 12 # Number of memory barriers committed 620system.cpu.commit.branches 1008 # Number of branches committed 621system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 622system.cpu.commit.int_insts 4624 # Number of committed integer instructions. 623system.cpu.commit.function_calls 82 # Number of function calls committed. 624system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 625system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 626system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 627system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 628system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 629system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 630system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 631system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 632system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 633system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 654system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 655system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 657system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 658system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 659system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached 660system.cpu.rob.rob_reads 23088 # The number of ROB reads 661system.cpu.rob.rob_writes 16743 # The number of ROB writes 662system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself 663system.cpu.idleCycles 21871 # Total number of cycles that the CPU has spent unscheduled due to idling 664system.cpu.committedInsts 4592 # Number of Instructions Simulated 665system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 666system.cpu.cpi 8.197517 # CPI: Cycles Per Instruction 667system.cpu.cpi_total 8.197517 # CPI: Total CPI of All Threads 668system.cpu.ipc 0.121988 # IPC: Instructions Per Cycle 669system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads 670system.cpu.int_regfile_reads 6777 # number of integer regfile reads 671system.cpu.int_regfile_writes 3787 # number of integer regfile writes 672system.cpu.fp_regfile_reads 16 # number of floating regfile reads 673system.cpu.cc_regfile_reads 24229 # number of cc regfile reads 674system.cpu.cc_regfile_writes 2921 # number of cc regfile writes
| 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 443 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 986132512 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 428457574 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 91812337 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 1506402423 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 986132512 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 986132512 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 986132512 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 428457574 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 91812337 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 1506402423 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 443 # Number of read requests accepted 37system.physmem.writeReqs 0 # Number of write requests accepted 38system.physmem.readBursts 443 # Number of DRAM read bursts, including those serviced by the write queue 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 40system.physmem.bytesReadDRAM 28352 # Total number of bytes read from DRAM 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 43system.physmem.bytesReadSys 28352 # Total read bytes from the system interface side 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 101 # Per bank write bursts 49system.physmem.perBankRdBursts::1 48 # Per bank write bursts 50system.physmem.perBankRdBursts::2 19 # Per bank write bursts 51system.physmem.perBankRdBursts::3 45 # Per bank write bursts 52system.physmem.perBankRdBursts::4 19 # Per bank write bursts 53system.physmem.perBankRdBursts::5 37 # Per bank write bursts 54system.physmem.perBankRdBursts::6 46 # Per bank write bursts 55system.physmem.perBankRdBursts::7 10 # Per bank write bursts 56system.physmem.perBankRdBursts::8 4 # Per bank write bursts 57system.physmem.perBankRdBursts::9 8 # Per bank write bursts 58system.physmem.perBankRdBursts::10 27 # Per bank write bursts 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts 60system.physmem.perBankRdBursts::12 17 # Per bank write bursts 61system.physmem.perBankRdBursts::13 8 # Per bank write bursts 62system.physmem.perBankRdBursts::14 0 # Per bank write bursts 63system.physmem.perBankRdBursts::15 7 # Per bank write bursts 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 82system.physmem.totGap 18779500 # Total gap between requests 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) 89system.physmem.readPktSize::6 443 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) 97system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 193system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 427.682540 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 292.140083 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 354.445538 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 18 28.57% 39.68% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 1 1.59% 69.84% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 4 6.35% 76.19% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 207system.physmem.totQLat 3401243 # Total ticks spent queuing 208system.physmem.totMemAccLat 11707493 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 2215000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 7677.75 # Average queueing delay per DRAM burst 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 212system.physmem.avgMemAccLat 26427.75 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 1506.40 # Average DRAM read bandwidth in MiByte/s 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 215system.physmem.avgRdBWSys 1506.40 # Average system read bandwidth in MiByte/s 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 11.77 # Data bus utilization in percentage 219system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 371 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes 225system.physmem.readRowHitRate 83.75 # Row buffer hit rate for reads 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 227system.physmem.avgGap 42391.65 # Average gap between requests 228system.physmem.pageHitRate 83.75 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 234system.physmem_0.actBackEnergy 10755900 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 64500 # Energy for precharge background per rank (pJ) 236system.physmem_0.totalEnergy 14453835 # Total energy per rank (pJ) 237system.physmem_0.averagePower 912.921838 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 51750 # Time in different power states 239system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 241system.physmem_0.memoryStateTime::ACT 15274500 # Time in different power states 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 248system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ) 251system.physmem_1.averagePower 811.289436 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states 253system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 2438 # Number of BP lookups 258system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 449 # Number of BTB hits 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 263system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 266system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. 267system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 268system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. 269system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. 270system.cpu_clk_domain.clock 500 # Clock period in ticks 271system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 280system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 281system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 282system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 283system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 284system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 285system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 286system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 287system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 288system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 289system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 290system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 291system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 292system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 293system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 294system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 295system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 296system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 297system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 298system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 299system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.inst_hits 0 # ITB inst hits 309system.cpu.dtb.inst_misses 0 # ITB inst misses 310system.cpu.dtb.read_hits 0 # DTB read hits 311system.cpu.dtb.read_misses 0 # DTB read misses 312system.cpu.dtb.write_hits 0 # DTB write hits 313system.cpu.dtb.write_misses 0 # DTB write misses 314system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 315system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 316system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 317system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 318system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 319system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 320system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses 329system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 338system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 339system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 340system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 341system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 342system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 343system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 344system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 345system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 346system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 347system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 348system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 349system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 350system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 351system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 352system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 353system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 354system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 355system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 356system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 357system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 358system.cpu.itb.walker.walks 0 # Table walker walks requested 359system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.inst_hits 0 # ITB inst hits 367system.cpu.itb.inst_misses 0 # ITB inst misses 368system.cpu.itb.read_hits 0 # DTB read hits 369system.cpu.itb.read_misses 0 # DTB read misses 370system.cpu.itb.write_hits 0 # DTB write hits 371system.cpu.itb.write_misses 0 # DTB write misses 372system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 373system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 374system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 375system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 376system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 377system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 378system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 379system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 380system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 381system.cpu.itb.read_accesses 0 # DTB read accesses 382system.cpu.itb.write_accesses 0 # DTB write accesses 383system.cpu.itb.inst_accesses 0 # ITB inst accesses 384system.cpu.itb.hits 0 # DTB hits 385system.cpu.itb.misses 0 # DTB misses 386system.cpu.itb.accesses 0 # DTB accesses 387system.cpu.workload.num_syscalls 13 # Number of system calls 388system.cpu.numCycles 37643 # number of cpu cycles simulated 389system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 390system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 391system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss 392system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed 393system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered 394system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken 395system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked 396system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing 397system.cpu.fetch.MiscStallCycles 169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 398system.cpu.fetch.PendingTrapStallCycles 272 # Number of stall cycles due to pending traps 399system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR 400system.cpu.fetch.CacheLines 3904 # Number of cache lines fetched 401system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed 402system.cpu.fetch.rateDist::samples 15772 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::mean 0.863365 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::stdev 1.208800 # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::0 9389 59.53% 59.53% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::1 2507 15.90% 75.42% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::2 518 3.28% 78.71% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::3 3358 21.29% 100.00% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::total 15772 # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.branchRate 0.064766 # Number of branch fetches per cycle 415system.cpu.fetch.rate 0.304280 # Number of inst fetches per cycle 416system.cpu.decode.IdleCycles 5832 # Number of cycles decode is idle 417system.cpu.decode.BlockedCycles 4243 # Number of cycles decode is blocked 418system.cpu.decode.RunCycles 5178 # Number of cycles decode is running 419system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking 420system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing 421system.cpu.decode.BranchResolved 373 # Number of times decode resolved a branch 422system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction 423system.cpu.decode.DecodedInsts 10169 # Number of instructions handled by decode 424system.cpu.decode.SquashedInsts 1675 # Number of squashed instructions handled by decode 425system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing 426system.cpu.rename.IdleCycles 6945 # Number of cycles rename is idle 427system.cpu.rename.BlockCycles 1086 # Number of cycles rename is blocking 428system.cpu.rename.serializeStallCycles 2318 # count of cycles rename stalled for serializing inst 429system.cpu.rename.RunCycles 4187 # Number of cycles rename is running 430system.cpu.rename.UnblockCycles 850 # Number of cycles rename is unblocking 431system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename 432system.cpu.rename.SquashedInsts 454 # Number of squashed instructions processed by rename 433system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full 434system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 435system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full 436system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full 437system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed 438system.cpu.rename.RenameLookups 41158 # Number of register rename lookups that rename has made 439system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups 440system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 441system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 442system.cpu.rename.UndoneMaps 3956 # Number of HB maps that are undone due to squashing 443system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 444system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 445system.cpu.rename.skidInsts 331 # count of insts added to the skid buffer 446system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. 447system.cpu.memDep0.insertedStores 1291 # Number of stores inserted to the mem dependence unit. 448system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 449system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 450system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec) 451system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ 452system.cpu.iq.iqInstsIssued 7234 # Number of instructions issued 453system.cpu.iq.iqSquashedInstsIssued 175 # Number of squashed instructions issued 454system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling 455system.cpu.iq.iqSquashedOperandsExamined 8237 # Number of squashed operands that are examined and possibly removed from graph 456system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed 457system.cpu.iq.issued_per_cycle::samples 15772 # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::mean 0.458661 # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::stdev 0.847067 # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::0 11502 72.93% 72.93% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::1 1999 12.67% 85.60% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::2 1621 10.28% 95.88% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::3 607 3.85% 99.73% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::total 15772 # Number of insts issued each cycle 474system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 475system.cpu.iq.fu_full::IntAlu 415 28.78% 28.78% # attempts to use FU when none available 476system.cpu.iq.fu_full::IntMult 0 0.00% 28.78% # attempts to use FU when none available 477system.cpu.iq.fu_full::IntDiv 0 0.00% 28.78% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.78% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.78% # attempts to use FU when none available 480system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.78% # attempts to use FU when none available 481system.cpu.iq.fu_full::FloatMult 0 0.00% 28.78% # attempts to use FU when none available 482system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.78% # attempts to use FU when none available 483system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.78% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.78% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.78% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.78% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.78% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.78% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.78% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdMult 0 0.00% 28.78% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.78% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdShift 0 0.00% 28.78% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.78% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.78% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.78% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.78% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.78% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.78% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.78% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.78% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.78% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.78% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.78% # attempts to use FU when none available 504system.cpu.iq.fu_full::MemRead 474 32.87% 61.65% # attempts to use FU when none available 505system.cpu.iq.fu_full::MemWrite 553 38.35% 100.00% # attempts to use FU when none available 506system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 507system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 508system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 509system.cpu.iq.FU_type_0::IntAlu 4534 62.68% 62.68% # Type of FU issued 510system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.75% # Type of FU issued 511system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.75% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.75% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.75% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.75% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.75% # Type of FU issued 516system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.75% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.75% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.75% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.75% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.75% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.75% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.75% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.75% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.75% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.75% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.75% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.75% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.75% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.75% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.75% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.75% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.75% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.75% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued 538system.cpu.iq.FU_type_0::MemRead 1605 22.19% 84.97% # Type of FU issued 539system.cpu.iq.FU_type_0::MemWrite 1087 15.03% 100.00% # Type of FU issued 540system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 541system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 542system.cpu.iq.FU_type_0::total 7234 # Type of FU issued 543system.cpu.iq.rate 0.192174 # Inst issue rate 544system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested 545system.cpu.iq.fu_busy_rate 0.199336 # FU busy rate (busy events/executed inst) 546system.cpu.iq.int_inst_queue_reads 31813 # Number of integer instruction queue reads 547system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes 548system.cpu.iq.int_inst_queue_wakeup_accesses 6621 # Number of integer instruction queue wakeup accesses 549system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads 550system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 551system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 552system.cpu.iq.int_alu_accesses 8648 # Number of integer alu accesses 553system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses 554system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores 555system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 556system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed 557system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 558system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 559system.cpu.iew.lsq.thread0.squashedStores 353 # Number of stores squashed 560system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 561system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 562system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 563system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 564system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 565system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing 566system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking 567system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking 568system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ 569system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 570system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions 571system.cpu.iew.iewDispStoreInsts 1291 # Number of dispatched store instructions 572system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 573system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 574system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 575system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 576system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly 577system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly 578system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 579system.cpu.iew.iewExecutedInsts 6824 # Number of executed instructions 580system.cpu.iew.iewExecLoadInsts 1421 # Number of load instructions executed 581system.cpu.iew.iewExecSquashedInsts 410 # Number of squashed instructions skipped in execute 582system.cpu.iew.exec_swp 0 # number of swp insts executed 583system.cpu.iew.exec_nop 13 # number of nop insts executed 584system.cpu.iew.exec_refs 2451 # number of memory reference insts executed 585system.cpu.iew.exec_branches 1299 # Number of branches executed 586system.cpu.iew.exec_stores 1030 # Number of stores executed 587system.cpu.iew.exec_rate 0.181282 # Inst execution rate 588system.cpu.iew.wb_sent 6681 # cumulative count of insts sent to commit 589system.cpu.iew.wb_count 6637 # cumulative count of insts written-back 590system.cpu.iew.wb_producers 2986 # num instructions producing a value 591system.cpu.iew.wb_consumers 5424 # num instructions consuming a value 592system.cpu.iew.wb_rate 0.176314 # insts written-back per cycle 593system.cpu.iew.wb_fanout 0.550516 # average fanout of values written-back 594system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit 595system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 596system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted 597system.cpu.commit.committed_per_cycle::samples 15204 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::mean 0.353723 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::stdev 0.993092 # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::0 12538 82.47% 82.47% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::1 1405 9.24% 91.71% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::2 597 3.93% 95.63% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::3 300 1.97% 97.61% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::4 170 1.12% 98.72% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::5 79 0.52% 99.24% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::total 15204 # Number of insts commited each cycle 614system.cpu.commit.committedInsts 4592 # Number of instructions committed 615system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 616system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 617system.cpu.commit.refs 1965 # Number of memory references committed 618system.cpu.commit.loads 1027 # Number of loads committed 619system.cpu.commit.membars 12 # Number of memory barriers committed 620system.cpu.commit.branches 1008 # Number of branches committed 621system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 622system.cpu.commit.int_insts 4624 # Number of committed integer instructions. 623system.cpu.commit.function_calls 82 # Number of function calls committed. 624system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 625system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 626system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 627system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 628system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 629system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 630system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 631system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 632system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 633system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 654system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 655system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 657system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 658system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 659system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached 660system.cpu.rob.rob_reads 23088 # The number of ROB reads 661system.cpu.rob.rob_writes 16743 # The number of ROB writes 662system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself 663system.cpu.idleCycles 21871 # Total number of cycles that the CPU has spent unscheduled due to idling 664system.cpu.committedInsts 4592 # Number of Instructions Simulated 665system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 666system.cpu.cpi 8.197517 # CPI: Cycles Per Instruction 667system.cpu.cpi_total 8.197517 # CPI: Total CPI of All Threads 668system.cpu.ipc 0.121988 # IPC: Instructions Per Cycle 669system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads 670system.cpu.int_regfile_reads 6777 # number of integer regfile reads 671system.cpu.int_regfile_writes 3787 # number of integer regfile writes 672system.cpu.fp_regfile_reads 16 # number of floating regfile reads 673system.cpu.cc_regfile_reads 24229 # number of cc regfile reads 674system.cpu.cc_regfile_writes 2921 # number of cc regfile writes
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