Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt

stats.txt (11312:3d7a85d71bd1)	stats.txt (11336:b318499f676c)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18741000 # Number of ticks simulated 5final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18741000 # Number of ticks simulated 5final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 27191 # Simulator instruction rate (inst/s) 8host_op_rate 31839 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 110934081 # Simulator tick rate (ticks/s) 10host_mem_usage 245436 # Number of bytes of host memory used 11host_seconds 0.17 # Real time elapsed on the host	7host_inst_rate 84742 # Simulator instruction rate (inst/s) 8host_op_rate 99228 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 345728368 # Simulator tick rate (ticks/s) 10host_mem_usage 266024 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host
12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18432 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28224 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18432 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18432 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 288 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 441 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 983512086 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 430286538 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 92204258 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 1506002881 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 983512086 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 983512086 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 983512086 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 430286538 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 92204258 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 1506002881 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 442 # Number of read requests accepted 37system.physmem.writeReqs 0 # Number of write requests accepted 38system.physmem.readBursts 442 # Number of DRAM read bursts, including those serviced by the write queue 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 40system.physmem.bytesReadDRAM 28288 # Total number of bytes read from DRAM 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 43system.physmem.bytesReadSys 28288 # Total read bytes from the system interface side 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 101 # Per bank write bursts 49system.physmem.perBankRdBursts::1 48 # Per bank write bursts 50system.physmem.perBankRdBursts::2 19 # Per bank write bursts 51system.physmem.perBankRdBursts::3 44 # Per bank write bursts 52system.physmem.perBankRdBursts::4 19 # Per bank write bursts 53system.physmem.perBankRdBursts::5 37 # Per bank write bursts 54system.physmem.perBankRdBursts::6 46 # Per bank write bursts 55system.physmem.perBankRdBursts::7 10 # Per bank write bursts 56system.physmem.perBankRdBursts::8 4 # Per bank write bursts 57system.physmem.perBankRdBursts::9 8 # Per bank write bursts 58system.physmem.perBankRdBursts::10 27 # Per bank write bursts 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts 60system.physmem.perBankRdBursts::12 17 # Per bank write bursts 61system.physmem.perBankRdBursts::13 8 # Per bank write bursts 62system.physmem.perBankRdBursts::14 0 # Per bank write bursts 63system.physmem.perBankRdBursts::15 7 # Per bank write bursts 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 82system.physmem.totGap 18727500 # Total gap between requests 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) 89system.physmem.readPktSize::6 442 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) 97system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 193system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 425.650794 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 288.378165 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 357.476918 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 21 33.33% 44.44% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 5 7.94% 76.19% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 206system.physmem.totQLat 3434000 # Total ticks spent queuing 207system.physmem.totMemAccLat 11721500 # Total ticks spent from burst creation until serviced by the DRAM 208system.physmem.totBusLat 2210000 # Total ticks spent in databus transfers 209system.physmem.avgQLat 7769.23 # Average queueing delay per DRAM burst 210system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 211system.physmem.avgMemAccLat 26519.23 # Average memory access latency per DRAM burst 212system.physmem.avgRdBW 1509.42 # Average DRAM read bandwidth in MiByte/s 213system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 214system.physmem.avgRdBWSys 1509.42 # Average system read bandwidth in MiByte/s 215system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 216system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 217system.physmem.busUtil 11.79 # Data bus utilization in percentage 218system.physmem.busUtilRead 11.79 # Data bus utilization in percentage for reads 219system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 220system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing 221system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 222system.physmem.readRowHits 370 # Number of row buffer hits during reads 223system.physmem.writeRowHits 0 # Number of row buffer hits during writes 224system.physmem.readRowHitRate 83.71 # Row buffer hit rate for reads 225system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 226system.physmem.avgGap 42369.91 # Average gap between requests 227system.physmem.pageHitRate 83.71 # Row buffer hit rate, read and write combined 228system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 229system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 230system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) 231system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 232system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 233system.physmem_0.actBackEnergy 10786680 # Energy for active background per rank (pJ) 234system.physmem_0.preBackEnergy 37500 # Energy for precharge background per rank (pJ) 235system.physmem_0.totalEnergy 14457615 # Total energy per rank (pJ) 236system.physmem_0.averagePower 913.160587 # Core power per rank (mW) 237system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states 238system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 239system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 240system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states 241system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 242system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 243system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 244system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) 245system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 246system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 247system.physmem_1.actBackEnergy 9859005 # Energy for active background per rank (pJ) 248system.physmem_1.preBackEnergy 851250 # Energy for precharge background per rank (pJ) 249system.physmem_1.totalEnergy 12737220 # Total energy per rank (pJ) 250system.physmem_1.averagePower 804.498342 # Core power per rank (mW) 251system.physmem_1.memoryStateTime::IDLE 2184750 # Time in different power states 252system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 253system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 254system.physmem_1.memoryStateTime::ACT 13949750 # Time in different power states 255system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 256system.cpu.branchPred.lookups 2341 # Number of BP lookups 257system.cpu.branchPred.condPredicted 1389 # Number of conditional branches predicted 258system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect 259system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups 260system.cpu.branchPred.BTBHits 447 # Number of BTB hits 261system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 262system.cpu.branchPred.BTBHitPct 53.341289 # BTB Hit Percentage 263system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target. 264system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 265system.cpu_clk_domain.clock 500 # Clock period in ticks 266system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 275system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 276system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 277system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 278system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 279system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 284system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 285system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 286system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 287system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 288system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 289system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 290system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 291system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 292system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 293system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 294system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 295system.cpu.dtb.walker.walks 0 # Table walker walks requested 296system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.inst_hits 0 # ITB inst hits 304system.cpu.dtb.inst_misses 0 # ITB inst misses 305system.cpu.dtb.read_hits 0 # DTB read hits 306system.cpu.dtb.read_misses 0 # DTB read misses 307system.cpu.dtb.write_hits 0 # DTB write hits 308system.cpu.dtb.write_misses 0 # DTB write misses 309system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 310system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 311system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 312system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 313system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 314system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 315system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 316system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 317system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.dtb.read_accesses 0 # DTB read accesses 319system.cpu.dtb.write_accesses 0 # DTB write accesses 320system.cpu.dtb.inst_accesses 0 # ITB inst accesses 321system.cpu.dtb.hits 0 # DTB hits 322system.cpu.dtb.misses 0 # DTB misses 323system.cpu.dtb.accesses 0 # DTB accesses 324system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 325system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 333system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 334system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 335system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 336system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 337system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 338system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 342system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 343system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 344system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 345system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 346system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 347system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 348system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 349system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 350system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 351system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 352system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 353system.cpu.itb.walker.walks 0 # Table walker walks requested 354system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.inst_hits 0 # ITB inst hits 362system.cpu.itb.inst_misses 0 # ITB inst misses 363system.cpu.itb.read_hits 0 # DTB read hits 364system.cpu.itb.read_misses 0 # DTB read misses 365system.cpu.itb.write_hits 0 # DTB write hits 366system.cpu.itb.write_misses 0 # DTB write misses 367system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 368system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 369system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 370system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 371system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 372system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 373system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 374system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 375system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 376system.cpu.itb.read_accesses 0 # DTB read accesses 377system.cpu.itb.write_accesses 0 # DTB write accesses 378system.cpu.itb.inst_accesses 0 # ITB inst accesses 379system.cpu.itb.hits 0 # DTB hits 380system.cpu.itb.misses 0 # DTB misses 381system.cpu.itb.accesses 0 # DTB accesses 382system.cpu.workload.num_syscalls 13 # Number of system calls 383system.cpu.numCycles 37483 # number of cpu cycles simulated 384system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 385system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 386system.cpu.fetch.icacheStallCycles 6059 # Number of cycles fetch is stalled on an Icache miss 387system.cpu.fetch.Insts 11274 # Number of instructions fetch has processed 388system.cpu.fetch.Branches 2341 # Number of branches that fetch encountered 389system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken 390system.cpu.fetch.Cycles 8204 # Number of cycles fetch has run and was not squashing or blocked 391system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing 392system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 393system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps 394system.cpu.fetch.IcacheWaitRetryStallCycles 363 # Number of stall cycles due to full MSHR 395system.cpu.fetch.CacheLines 3834 # Number of cache lines fetched 396system.cpu.fetch.IcacheSquashes 177 # Number of outstanding Icache misses that were squashed 397system.cpu.fetch.rateDist::samples 15601 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::mean 0.845843 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::stdev 1.199579 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::0 9385 60.16% 60.16% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::1 2463 15.79% 75.94% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::2 526 3.37% 79.32% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::3 3227 20.68% 100.00% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::total 15601 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.branchRate 0.062455 # Number of branch fetches per cycle 410system.cpu.fetch.rate 0.300776 # Number of inst fetches per cycle 411system.cpu.decode.IdleCycles 5749 # Number of cycles decode is idle 412system.cpu.decode.BlockedCycles 4322 # Number of cycles decode is blocked 413system.cpu.decode.RunCycles 5029 # Number of cycles decode is running 414system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 415system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing 416system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch 417system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction 418system.cpu.decode.DecodedInsts 9880 # Number of instructions handled by decode 419system.cpu.decode.SquashedInsts 1586 # Number of squashed instructions handled by decode 420system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing 421system.cpu.rename.IdleCycles 6811 # Number of cycles rename is idle 422system.cpu.rename.BlockCycles 1118 # Number of cycles rename is blocking 423system.cpu.rename.serializeStallCycles 2339 # count of cycles rename stalled for serializing inst 424system.cpu.rename.RunCycles 4089 # Number of cycles rename is running 425system.cpu.rename.UnblockCycles 875 # Number of cycles rename is unblocking 426system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename 427system.cpu.rename.SquashedInsts 417 # Number of squashed instructions processed by rename 428system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full 429system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 430system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full 431system.cpu.rename.SQFullEvents 772 # Number of times rename has blocked due to SQ full 432system.cpu.rename.RenamedOperands 9259 # Number of destination operands rename has renamed 433system.cpu.rename.RenameLookups 40331 # Number of register rename lookups that rename has made 434system.cpu.rename.int_rename_lookups 9781 # Number of integer rename lookups 435system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 436system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 437system.cpu.rename.UndoneMaps 3765 # Number of HB maps that are undone due to squashing 438system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 439system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 440system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer 441system.cpu.memDep0.insertedLoads 1800 # Number of loads inserted to the mem dependence unit. 442system.cpu.memDep0.insertedStores 1272 # Number of stores inserted to the mem dependence unit. 443system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 444system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 445system.cpu.iq.iqInstsAdded 8358 # Number of instructions added to the IQ (excludes non-spec) 446system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ 447system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued 448system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued 449system.cpu.iq.iqSquashedInstsExamined 3018 # Number of squashed instructions iterated over during squash; mainly for profiling 450system.cpu.iq.iqSquashedOperandsExamined 7856 # Number of squashed operands that are examined and possibly removed from graph 451system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed 452system.cpu.iq.issued_per_cycle::samples 15601 # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::mean 0.458176 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::stdev 0.848338 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::0 11391 73.01% 73.01% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::1 1965 12.60% 85.61% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::2 1598 10.24% 95.85% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::3 601 3.85% 99.71% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::4 46 0.29% 100.00% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::total 15601 # Number of insts issued each cycle 469system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 470system.cpu.iq.fu_full::IntAlu 413 28.70% 28.70% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntMult 0 0.00% 28.70% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntDiv 0 0.00% 28.70% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.70% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.70% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.70% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatMult 0 0.00% 28.70% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.70% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.70% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.70% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.70% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.70% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.70% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.70% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.70% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMult 0 0.00% 28.70% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.70% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdShift 0 0.00% 28.70% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.70% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.70% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.70% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.70% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.70% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.70% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.70% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.70% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.70% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.70% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.70% # attempts to use FU when none available 499system.cpu.iq.fu_full::MemRead 475 33.01% 61.71% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemWrite 551 38.29% 100.00% # attempts to use FU when none available 501system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 502system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 504system.cpu.iq.FU_type_0::IntAlu 4480 62.67% 62.67% # Type of FU issued 505system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.74% # Type of FU issued 506system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.74% # Type of FU issued 507system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.74% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.74% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.74% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.74% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.74% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued 533system.cpu.iq.FU_type_0::MemRead 1582 22.13% 84.92% # Type of FU issued 534system.cpu.iq.FU_type_0::MemWrite 1078 15.08% 100.00% # Type of FU issued 535system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 536system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::total 7148 # Type of FU issued 538system.cpu.iq.rate 0.190700 # Inst issue rate 539system.cpu.iq.fu_busy_cnt 1439 # FU busy when requested 540system.cpu.iq.fu_busy_rate 0.201315 # FU busy rate (busy events/executed inst) 541system.cpu.iq.int_inst_queue_reads 31476 # Number of integer instruction queue reads 542system.cpu.iq.int_inst_queue_writes 11405 # Number of integer instruction queue writes 543system.cpu.iq.int_inst_queue_wakeup_accesses 6562 # Number of integer instruction queue wakeup accesses 544system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads 545system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 546system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 547system.cpu.iq.int_alu_accesses 8559 # Number of integer alu accesses 548system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses 549system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores 550system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 551system.cpu.iew.lsq.thread0.squashedLoads 773 # Number of loads squashed 552system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 553system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 554system.cpu.iew.lsq.thread0.squashedStores 334 # Number of stores squashed 555system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 556system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 557system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled 558system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 559system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 560system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing 561system.cpu.iew.iewBlockCycles 385 # Number of cycles IEW is blocking 562system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking 563system.cpu.iew.iewDispatchedInsts 8410 # Number of instructions dispatched to IQ 564system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 565system.cpu.iew.iewDispLoadInsts 1800 # Number of dispatched load instructions 566system.cpu.iew.iewDispStoreInsts 1272 # Number of dispatched store instructions 567system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 568system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 569system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 570system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 571system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly 572system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly 573system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute 574system.cpu.iew.iewExecutedInsts 6751 # Number of executed instructions 575system.cpu.iew.iewExecLoadInsts 1398 # Number of load instructions executed 576system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute 577system.cpu.iew.exec_swp 0 # number of swp insts executed 578system.cpu.iew.exec_nop 14 # number of nop insts executed 579system.cpu.iew.exec_refs 2419 # number of memory reference insts executed 580system.cpu.iew.exec_branches 1275 # Number of branches executed 581system.cpu.iew.exec_stores 1021 # Number of stores executed 582system.cpu.iew.exec_rate 0.180108 # Inst execution rate 583system.cpu.iew.wb_sent 6621 # cumulative count of insts sent to commit 584system.cpu.iew.wb_count 6578 # cumulative count of insts written-back 585system.cpu.iew.wb_producers 2993 # num instructions producing a value 586system.cpu.iew.wb_consumers 5408 # num instructions consuming a value 587system.cpu.iew.wb_rate 0.175493 # insts written-back per cycle 588system.cpu.iew.wb_fanout 0.553439 # average fanout of values written-back 589system.cpu.commit.commitSquashedInsts 2586 # The number of squashed insts skipped by commit 590system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 591system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted 592system.cpu.commit.committed_per_cycle::samples 15057 # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::mean 0.357176 # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::stdev 1.003286 # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::0 12412 82.43% 82.43% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::1 1386 9.21% 91.64% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::2 592 3.93% 95.57% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::3 296 1.97% 97.54% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::4 173 1.15% 98.68% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::5 78 0.52% 99.20% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::6 45 0.30% 99.50% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::7 32 0.21% 99.71% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::total 15057 # Number of insts commited each cycle 609system.cpu.commit.committedInsts 4592 # Number of instructions committed 610system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 611system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 612system.cpu.commit.refs 1965 # Number of memory references committed 613system.cpu.commit.loads 1027 # Number of loads committed 614system.cpu.commit.membars 12 # Number of memory barriers committed 615system.cpu.commit.branches 1008 # Number of branches committed 616system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 617system.cpu.commit.int_insts 4624 # Number of committed integer instructions. 618system.cpu.commit.function_calls 82 # Number of function calls committed. 619system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 620system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 621system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 622system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 623system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 624system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 625system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 626system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 627system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 628system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 630system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 631system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 649system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 650system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 651system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 652system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 653system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 654system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached 655system.cpu.rob.rob_reads 22821 # The number of ROB reads 656system.cpu.rob.rob_writes 16478 # The number of ROB writes 657system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself 658system.cpu.idleCycles 21882 # Total number of cycles that the CPU has spent unscheduled due to idling 659system.cpu.committedInsts 4592 # Number of Instructions Simulated 660system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 661system.cpu.cpi 8.162674 # CPI: Cycles Per Instruction 662system.cpu.cpi_total 8.162674 # CPI: Total CPI of All Threads 663system.cpu.ipc 0.122509 # IPC: Instructions Per Cycle 664system.cpu.ipc_total 0.122509 # IPC: Total IPC of All Threads 665system.cpu.int_regfile_reads 6722 # number of integer regfile reads 666system.cpu.int_regfile_writes 3755 # number of integer regfile writes 667system.cpu.fp_regfile_reads 16 # number of floating regfile reads 668system.cpu.cc_regfile_reads 23977 # number of cc regfile reads 669system.cpu.cc_regfile_writes 2903 # number of cc regfile writes 670system.cpu.misc_regfile_reads 2611 # number of misc regfile reads 671system.cpu.misc_regfile_writes 24 # number of misc regfile writes 672system.cpu.dcache.tags.replacements 1 # number of replacements 673system.cpu.dcache.tags.tagsinuse 84.551975 # Cycle average of tags in use 674system.cpu.dcache.tags.total_refs 1908 # Total number of references to valid blocks. 675system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. 676system.cpu.dcache.tags.avg_refs 13.342657 # Average number of references to valid blocks. 677system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 678system.cpu.dcache.tags.occ_blocks::cpu.data 84.551975 # Average occupied blocks per requestor 679system.cpu.dcache.tags.occ_percent::cpu.data 0.165141 # Average percentage of cache occupancy 680system.cpu.dcache.tags.occ_percent::total 0.165141 # Average percentage of cache occupancy 681system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 682system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 683system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id 684system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id 685system.cpu.dcache.tags.tag_accesses 4677 # Number of tag accesses 686system.cpu.dcache.tags.data_accesses 4677 # Number of data accesses 687system.cpu.dcache.ReadReq_hits::cpu.data 1166 # number of ReadReq hits 688system.cpu.dcache.ReadReq_hits::total 1166 # number of ReadReq hits 689system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 690system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 691system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 692system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 693system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 694system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 695system.cpu.dcache.demand_hits::cpu.data 1888 # number of demand (read+write) hits 696system.cpu.dcache.demand_hits::total 1888 # number of demand (read+write) hits 697system.cpu.dcache.overall_hits::cpu.data 1888 # number of overall hits 698system.cpu.dcache.overall_hits::total 1888 # number of overall hits 699system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses 700system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses 701system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 702system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 703system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 704system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 705system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses 706system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses 707system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses 708system.cpu.dcache.overall_misses::total 357 # number of overall misses 709system.cpu.dcache.ReadReq_miss_latency::cpu.data 10689500 # number of ReadReq miss cycles 710system.cpu.dcache.ReadReq_miss_latency::total 10689500 # number of ReadReq miss cycles 711system.cpu.dcache.WriteReq_miss_latency::cpu.data 7727500 # number of WriteReq miss cycles 712system.cpu.dcache.WriteReq_miss_latency::total 7727500 # number of WriteReq miss cycles 713system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles 714system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles 715system.cpu.dcache.demand_miss_latency::cpu.data 18417000 # number of demand (read+write) miss cycles 716system.cpu.dcache.demand_miss_latency::total 18417000 # number of demand (read+write) miss cycles 717system.cpu.dcache.overall_miss_latency::cpu.data 18417000 # number of overall miss cycles 718system.cpu.dcache.overall_miss_latency::total 18417000 # number of overall miss cycles 719system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) 720system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) 721system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 722system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 723system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 724system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 725system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 726system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 727system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses 728system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses 729system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses 730system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses 731system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124625 # miss rate for ReadReq accesses 732system.cpu.dcache.ReadReq_miss_rate::total 0.124625 # miss rate for ReadReq accesses 733system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 734system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 735system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 736system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses 737system.cpu.dcache.demand_miss_rate::cpu.data 0.159020 # miss rate for demand accesses 738system.cpu.dcache.demand_miss_rate::total 0.159020 # miss rate for demand accesses 739system.cpu.dcache.overall_miss_rate::cpu.data 0.159020 # miss rate for overall accesses 740system.cpu.dcache.overall_miss_rate::total 0.159020 # miss rate for overall accesses 741system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64394.578313 # average ReadReq miss latency 742system.cpu.dcache.ReadReq_avg_miss_latency::total 64394.578313 # average ReadReq miss latency 743system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40458.115183 # average WriteReq miss latency 744system.cpu.dcache.WriteReq_avg_miss_latency::total 40458.115183 # average WriteReq miss latency 745system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency 746system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency 747system.cpu.dcache.demand_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency 748system.cpu.dcache.demand_avg_miss_latency::total 51588.235294 # average overall miss latency 749system.cpu.dcache.overall_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency 750system.cpu.dcache.overall_avg_miss_latency::total 51588.235294 # average overall miss latency 751system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 752system.cpu.dcache.blocked_cycles::no_targets 846 # number of cycles access was blocked 753system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 754system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 755system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 756system.cpu.dcache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked 757system.cpu.dcache.fast_writes 0 # number of fast writes performed 758system.cpu.dcache.cache_copies 0 # number of cache copies performed 759system.cpu.dcache.writebacks::writebacks 1 # number of writebacks 760system.cpu.dcache.writebacks::total 1 # number of writebacks 761system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 762system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 763system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 764system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 765system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 766system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 767system.cpu.dcache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits 768system.cpu.dcache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits 769system.cpu.dcache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits 770system.cpu.dcache.overall_mshr_hits::total 213 # number of overall MSHR hits 771system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 772system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 773system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 774system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 775system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 776system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 777system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 778system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses 779system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6989000 # number of ReadReq MSHR miss cycles 780system.cpu.dcache.ReadReq_mshr_miss_latency::total 6989000 # number of ReadReq MSHR miss cycles 781system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2447000 # number of WriteReq MSHR miss cycles 782system.cpu.dcache.WriteReq_mshr_miss_latency::total 2447000 # number of WriteReq MSHR miss cycles 783system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9436000 # number of demand (read+write) MSHR miss cycles 784system.cpu.dcache.demand_mshr_miss_latency::total 9436000 # number of demand (read+write) MSHR miss cycles 785system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9436000 # number of overall MSHR miss cycles 786system.cpu.dcache.overall_mshr_miss_latency::total 9436000 # number of overall MSHR miss cycles 787system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077327 # mshr miss rate for ReadReq accesses 788system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077327 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for demand accesses 792system.cpu.dcache.demand_mshr_miss_rate::total 0.064143 # mshr miss rate for demand accesses 793system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for overall accesses 794system.cpu.dcache.overall_mshr_miss_rate::total 0.064143 # mshr miss rate for overall accesses 795system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67854.368932 # average ReadReq mshr miss latency 796system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67854.368932 # average ReadReq mshr miss latency 797system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59682.926829 # average WriteReq mshr miss latency 798system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59682.926829 # average WriteReq mshr miss latency 799system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency 800system.cpu.dcache.demand_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency 801system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency 802system.cpu.dcache.overall_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency 803system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 804system.cpu.icache.tags.replacements 43 # number of replacements 805system.cpu.icache.tags.tagsinuse 137.647063 # Cycle average of tags in use 806system.cpu.icache.tags.total_refs 3470 # Total number of references to valid blocks. 807system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. 808system.cpu.icache.tags.avg_refs 11.722973 # Average number of references to valid blocks. 809system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 810system.cpu.icache.tags.occ_blocks::cpu.inst 137.647063 # Average occupied blocks per requestor 811system.cpu.icache.tags.occ_percent::cpu.inst 0.268842 # Average percentage of cache occupancy 812system.cpu.icache.tags.occ_percent::total 0.268842 # Average percentage of cache occupancy 813system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id 814system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 815system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 816system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id 817system.cpu.icache.tags.tag_accesses 7960 # Number of tag accesses 818system.cpu.icache.tags.data_accesses 7960 # Number of data accesses 819system.cpu.icache.ReadReq_hits::cpu.inst 3470 # number of ReadReq hits 820system.cpu.icache.ReadReq_hits::total 3470 # number of ReadReq hits 821system.cpu.icache.demand_hits::cpu.inst 3470 # number of demand (read+write) hits 822system.cpu.icache.demand_hits::total 3470 # number of demand (read+write) hits 823system.cpu.icache.overall_hits::cpu.inst 3470 # number of overall hits 824system.cpu.icache.overall_hits::total 3470 # number of overall hits 825system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses 826system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses 827system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses 828system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses 829system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses 830system.cpu.icache.overall_misses::total 362 # number of overall misses 831system.cpu.icache.ReadReq_miss_latency::cpu.inst 22661491 # number of ReadReq miss cycles 832system.cpu.icache.ReadReq_miss_latency::total 22661491 # number of ReadReq miss cycles 833system.cpu.icache.demand_miss_latency::cpu.inst 22661491 # number of demand (read+write) miss cycles 834system.cpu.icache.demand_miss_latency::total 22661491 # number of demand (read+write) miss cycles 835system.cpu.icache.overall_miss_latency::cpu.inst 22661491 # number of overall miss cycles 836system.cpu.icache.overall_miss_latency::total 22661491 # number of overall miss cycles 837system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses) 838system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses) 839system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses 840system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses 841system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses 842system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses 843system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094468 # miss rate for ReadReq accesses 844system.cpu.icache.ReadReq_miss_rate::total 0.094468 # miss rate for ReadReq accesses 845system.cpu.icache.demand_miss_rate::cpu.inst 0.094468 # miss rate for demand accesses 846system.cpu.icache.demand_miss_rate::total 0.094468 # miss rate for demand accesses 847system.cpu.icache.overall_miss_rate::cpu.inst 0.094468 # miss rate for overall accesses 848system.cpu.icache.overall_miss_rate::total 0.094468 # miss rate for overall accesses 849system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62600.803867 # average ReadReq miss latency 850system.cpu.icache.ReadReq_avg_miss_latency::total 62600.803867 # average ReadReq miss latency 851system.cpu.icache.demand_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency 852system.cpu.icache.demand_avg_miss_latency::total 62600.803867 # average overall miss latency 853system.cpu.icache.overall_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency 854system.cpu.icache.overall_avg_miss_latency::total 62600.803867 # average overall miss latency 855system.cpu.icache.blocked_cycles::no_mshrs 8953 # number of cycles access was blocked 856system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked 857system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked 858system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 859system.cpu.icache.avg_blocked_cycles::no_mshrs 93.260417 # average number of cycles each access was blocked 860system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked 861system.cpu.icache.fast_writes 0 # number of fast writes performed 862system.cpu.icache.cache_copies 0 # number of cache copies performed 863system.cpu.icache.writebacks::writebacks 43 # number of writebacks 864system.cpu.icache.writebacks::total 43 # number of writebacks 865system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits 866system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits 867system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits 868system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits 869system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits 870system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits 871system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses 872system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses 873system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses 874system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses 875system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses 876system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses 877system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19893491 # number of ReadReq MSHR miss cycles 878system.cpu.icache.ReadReq_mshr_miss_latency::total 19893491 # number of ReadReq MSHR miss cycles 879system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19893491 # number of demand (read+write) MSHR miss cycles 880system.cpu.icache.demand_mshr_miss_latency::total 19893491 # number of demand (read+write) MSHR miss cycles 881system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19893491 # number of overall MSHR miss cycles 882system.cpu.icache.overall_mshr_miss_latency::total 19893491 # number of overall MSHR miss cycles 883system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for ReadReq accesses 884system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077505 # mshr miss rate for ReadReq accesses 885system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for demand accesses 886system.cpu.icache.demand_mshr_miss_rate::total 0.077505 # mshr miss rate for demand accesses 887system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for overall accesses 888system.cpu.icache.overall_mshr_miss_rate::total 0.077505 # mshr miss rate for overall accesses 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66981.451178 # average ReadReq mshr miss latency 890system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66981.451178 # average ReadReq mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency 892system.cpu.icache.demand_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency 894system.cpu.icache.overall_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency 895system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 896system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 897system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 898system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 899system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 900system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 901system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 902system.cpu.l2cache.tags.replacements 0 # number of replacements 903system.cpu.l2cache.tags.tagsinuse 19.860815 # Cycle average of tags in use 904system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. 905system.cpu.l2cache.tags.sampled_refs 48 # Sample count of references to valid blocks. 906system.cpu.l2cache.tags.avg_refs 0.208333 # Average number of references to valid blocks. 907system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 908system.cpu.l2cache.tags.occ_blocks::writebacks 10.581774 # Average occupied blocks per requestor 909system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.279041 # Average occupied blocks per requestor 910system.cpu.l2cache.tags.occ_percent::writebacks 0.000646 # Average percentage of cache occupancy 911system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000566 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::total 0.001212 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id 914system.cpu.l2cache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id 915system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 916system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 918system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 919system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id 920system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id 921system.cpu.l2cache.tags.tag_accesses 7643 # Number of tag accesses 922system.cpu.l2cache.tags.data_accesses 7643 # Number of data accesses 923system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 924system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 925system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 926system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 927system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 7 # number of ReadCleanReq hits 928system.cpu.l2cache.ReadCleanReq_hits::total 7 # number of ReadCleanReq hits 929system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 930system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 931system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits 932system.cpu.l2cache.demand_hits::cpu.data 13 # number of demand (read+write) hits 933system.cpu.l2cache.demand_hits::total 20 # number of demand (read+write) hits 934system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits 935system.cpu.l2cache.overall_hits::cpu.data 13 # number of overall hits 936system.cpu.l2cache.overall_hits::total 20 # number of overall hits 937system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses 938system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses 939system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 290 # number of ReadCleanReq misses 940system.cpu.l2cache.ReadCleanReq_misses::total 290 # number of ReadCleanReq misses 941system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 942system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses 943system.cpu.l2cache.demand_misses::cpu.inst 290 # number of demand (read+write) misses 944system.cpu.l2cache.demand_misses::cpu.data 131 # number of demand (read+write) misses 945system.cpu.l2cache.demand_misses::total 421 # number of demand (read+write) misses 946system.cpu.l2cache.overall_misses::cpu.inst 290 # number of overall misses 947system.cpu.l2cache.overall_misses::cpu.data 131 # number of overall misses 948system.cpu.l2cache.overall_misses::total 421 # number of overall misses 949system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2313000 # number of ReadExReq miss cycles 950system.cpu.l2cache.ReadExReq_miss_latency::total 2313000 # number of ReadExReq miss cycles 951system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19544000 # number of ReadCleanReq miss cycles 952system.cpu.l2cache.ReadCleanReq_miss_latency::total 19544000 # number of ReadCleanReq miss cycles 953system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6815000 # number of ReadSharedReq miss cycles 954system.cpu.l2cache.ReadSharedReq_miss_latency::total 6815000 # number of ReadSharedReq miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.inst 19544000 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::cpu.data 9128000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.demand_miss_latency::total 28672000 # number of demand (read+write) miss cycles 958system.cpu.l2cache.overall_miss_latency::cpu.inst 19544000 # number of overall miss cycles 959system.cpu.l2cache.overall_miss_latency::cpu.data 9128000 # number of overall miss cycles 960system.cpu.l2cache.overall_miss_latency::total 28672000 # number of overall miss cycles 961system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 962system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 963system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 964system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 965system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 297 # number of ReadCleanReq accesses(hits+misses) 966system.cpu.l2cache.ReadCleanReq_accesses::total 297 # number of ReadCleanReq accesses(hits+misses) 967system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 968system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) 969system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses 970system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses 971system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 972system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses 973system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses 974system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 975system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses 976system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses 977system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976431 # miss rate for ReadCleanReq accesses 978system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976431 # miss rate for ReadCleanReq accesses 979system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.980583 # miss rate for ReadSharedReq accesses 980system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.980583 # miss rate for ReadSharedReq accesses 981system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976431 # miss rate for demand accesses 982system.cpu.l2cache.demand_miss_rate::cpu.data 0.909722 # miss rate for demand accesses 983system.cpu.l2cache.demand_miss_rate::total 0.954649 # miss rate for demand accesses 984system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976431 # miss rate for overall accesses 985system.cpu.l2cache.overall_miss_rate::cpu.data 0.909722 # miss rate for overall accesses 986system.cpu.l2cache.overall_miss_rate::total 0.954649 # miss rate for overall accesses 987system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77100 # average ReadExReq miss latency 988system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77100 # average ReadExReq miss latency 989system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67393.103448 # average ReadCleanReq miss latency 990system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67393.103448 # average ReadCleanReq miss latency 991system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67475.247525 # average ReadSharedReq miss latency 992system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67475.247525 # average ReadSharedReq miss latency 993system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency 994system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency 995system.cpu.l2cache.demand_avg_miss_latency::total 68104.513064 # average overall miss latency 996system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency 997system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency 998system.cpu.l2cache.overall_avg_miss_latency::total 68104.513064 # average overall miss latency 999system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1000system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1001system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1002system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1003system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1004system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1005system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1006system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1007system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1008system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1009system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 1010system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 1011system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1012system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1013system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1014system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1015system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 1016system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 1017system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses 1018system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses 1019system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses 1020system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses 1021system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 289 # number of ReadCleanReq MSHR misses 1022system.cpu.l2cache.ReadCleanReq_mshr_misses::total 289 # number of ReadCleanReq MSHR misses 1023system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 1024system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses 1025system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses 1026system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 1027system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses 1028system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses 1029system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses 1030system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses 1031system.cpu.l2cache.overall_mshr_misses::total 468 # number of overall MSHR misses 1032system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles 1033system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles 1034system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2133000 # number of ReadExReq MSHR miss cycles 1035system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2133000 # number of ReadExReq MSHR miss cycles 1036system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17760500 # number of ReadCleanReq MSHR miss cycles 1037system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17760500 # number of ReadCleanReq MSHR miss cycles 1038system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5946500 # number of ReadSharedReq MSHR miss cycles 1039system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5946500 # number of ReadSharedReq MSHR miss cycles 1040system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17760500 # number of demand (read+write) MSHR miss cycles 1041system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8079500 # number of demand (read+write) MSHR miss cycles 1042system.cpu.l2cache.demand_mshr_miss_latency::total 25840000 # number of demand (read+write) MSHR miss cycles 1043system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17760500 # number of overall MSHR miss cycles 1044system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8079500 # number of overall MSHR miss cycles 1045system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles 1046system.cpu.l2cache.overall_mshr_miss_latency::total 27465926 # number of overall MSHR miss cycles 1047system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1048system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1049system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1050system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 1051system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for ReadCleanReq accesses 1052system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.973064 # mshr miss rate for ReadCleanReq accesses 1053system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses 1054system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses 1055system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for demand accesses 1056system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses 1057system.cpu.l2cache.demand_mshr_miss_rate::total 0.941043 # mshr miss rate for demand accesses 1058system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for overall accesses 1059system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses 1060system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1061system.cpu.l2cache.overall_mshr_miss_rate::total 1.061224 # mshr miss rate for overall accesses 1062system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average HardPFReq mshr miss latency 1063system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 30677.849057 # average HardPFReq mshr miss latency 1064system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71100 # average ReadExReq mshr miss latency 1065system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71100 # average ReadExReq mshr miss latency 1066system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61455.017301 # average ReadCleanReq mshr miss latency 1067system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61455.017301 # average ReadCleanReq mshr miss latency 1068system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61942.708333 # average ReadSharedReq mshr miss latency 1069system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61942.708333 # average ReadSharedReq mshr miss latency 1070system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency 1071system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency 1072system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62265.060241 # average overall mshr miss latency 1073system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency 1074system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency 1075system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average overall mshr miss latency 1076system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58687.876068 # average overall mshr miss latency 1077system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1078system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. 1079system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1080system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1081system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # Total number of snoops made to the snoop filter. 1082system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1083system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1084system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution	12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18432 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28224 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18432 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18432 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 288 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 441 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 983512086 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 430286538 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 92204258 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 1506002881 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 983512086 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 983512086 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 983512086 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 430286538 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 92204258 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 1506002881 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 442 # Number of read requests accepted 37system.physmem.writeReqs 0 # Number of write requests accepted 38system.physmem.readBursts 442 # Number of DRAM read bursts, including those serviced by the write queue 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 40system.physmem.bytesReadDRAM 28288 # Total number of bytes read from DRAM 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 43system.physmem.bytesReadSys 28288 # Total read bytes from the system interface side 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 101 # Per bank write bursts 49system.physmem.perBankRdBursts::1 48 # Per bank write bursts 50system.physmem.perBankRdBursts::2 19 # Per bank write bursts 51system.physmem.perBankRdBursts::3 44 # Per bank write bursts 52system.physmem.perBankRdBursts::4 19 # Per bank write bursts 53system.physmem.perBankRdBursts::5 37 # Per bank write bursts 54system.physmem.perBankRdBursts::6 46 # Per bank write bursts 55system.physmem.perBankRdBursts::7 10 # Per bank write bursts 56system.physmem.perBankRdBursts::8 4 # Per bank write bursts 57system.physmem.perBankRdBursts::9 8 # Per bank write bursts 58system.physmem.perBankRdBursts::10 27 # Per bank write bursts 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts 60system.physmem.perBankRdBursts::12 17 # Per bank write bursts 61system.physmem.perBankRdBursts::13 8 # Per bank write bursts 62system.physmem.perBankRdBursts::14 0 # Per bank write bursts 63system.physmem.perBankRdBursts::15 7 # Per bank write bursts 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 82system.physmem.totGap 18727500 # Total gap between requests 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) 89system.physmem.readPktSize::6 442 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) 97system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 193system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 425.650794 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 288.378165 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 357.476918 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 21 33.33% 44.44% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 5 7.94% 76.19% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 206system.physmem.totQLat 3434000 # Total ticks spent queuing 207system.physmem.totMemAccLat 11721500 # Total ticks spent from burst creation until serviced by the DRAM 208system.physmem.totBusLat 2210000 # Total ticks spent in databus transfers 209system.physmem.avgQLat 7769.23 # Average queueing delay per DRAM burst 210system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 211system.physmem.avgMemAccLat 26519.23 # Average memory access latency per DRAM burst 212system.physmem.avgRdBW 1509.42 # Average DRAM read bandwidth in MiByte/s 213system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 214system.physmem.avgRdBWSys 1509.42 # Average system read bandwidth in MiByte/s 215system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 216system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 217system.physmem.busUtil 11.79 # Data bus utilization in percentage 218system.physmem.busUtilRead 11.79 # Data bus utilization in percentage for reads 219system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 220system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing 221system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 222system.physmem.readRowHits 370 # Number of row buffer hits during reads 223system.physmem.writeRowHits 0 # Number of row buffer hits during writes 224system.physmem.readRowHitRate 83.71 # Row buffer hit rate for reads 225system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 226system.physmem.avgGap 42369.91 # Average gap between requests 227system.physmem.pageHitRate 83.71 # Row buffer hit rate, read and write combined 228system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 229system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 230system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) 231system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 232system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 233system.physmem_0.actBackEnergy 10786680 # Energy for active background per rank (pJ) 234system.physmem_0.preBackEnergy 37500 # Energy for precharge background per rank (pJ) 235system.physmem_0.totalEnergy 14457615 # Total energy per rank (pJ) 236system.physmem_0.averagePower 913.160587 # Core power per rank (mW) 237system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states 238system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 239system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 240system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states 241system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 242system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 243system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 244system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) 245system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 246system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 247system.physmem_1.actBackEnergy 9859005 # Energy for active background per rank (pJ) 248system.physmem_1.preBackEnergy 851250 # Energy for precharge background per rank (pJ) 249system.physmem_1.totalEnergy 12737220 # Total energy per rank (pJ) 250system.physmem_1.averagePower 804.498342 # Core power per rank (mW) 251system.physmem_1.memoryStateTime::IDLE 2184750 # Time in different power states 252system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 253system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 254system.physmem_1.memoryStateTime::ACT 13949750 # Time in different power states 255system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 256system.cpu.branchPred.lookups 2341 # Number of BP lookups 257system.cpu.branchPred.condPredicted 1389 # Number of conditional branches predicted 258system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect 259system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups 260system.cpu.branchPred.BTBHits 447 # Number of BTB hits 261system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 262system.cpu.branchPred.BTBHitPct 53.341289 # BTB Hit Percentage 263system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target. 264system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 265system.cpu_clk_domain.clock 500 # Clock period in ticks 266system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 275system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 276system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 277system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 278system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 279system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 284system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 285system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 286system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 287system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 288system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 289system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 290system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 291system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 292system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 293system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 294system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 295system.cpu.dtb.walker.walks 0 # Table walker walks requested 296system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.inst_hits 0 # ITB inst hits 304system.cpu.dtb.inst_misses 0 # ITB inst misses 305system.cpu.dtb.read_hits 0 # DTB read hits 306system.cpu.dtb.read_misses 0 # DTB read misses 307system.cpu.dtb.write_hits 0 # DTB write hits 308system.cpu.dtb.write_misses 0 # DTB write misses 309system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 310system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 311system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 312system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 313system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 314system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 315system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 316system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 317system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.dtb.read_accesses 0 # DTB read accesses 319system.cpu.dtb.write_accesses 0 # DTB write accesses 320system.cpu.dtb.inst_accesses 0 # ITB inst accesses 321system.cpu.dtb.hits 0 # DTB hits 322system.cpu.dtb.misses 0 # DTB misses 323system.cpu.dtb.accesses 0 # DTB accesses 324system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 325system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 333system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 334system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 335system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 336system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 337system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 338system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 342system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 343system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 344system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 345system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 346system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 347system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 348system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 349system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 350system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 351system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 352system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 353system.cpu.itb.walker.walks 0 # Table walker walks requested 354system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.inst_hits 0 # ITB inst hits 362system.cpu.itb.inst_misses 0 # ITB inst misses 363system.cpu.itb.read_hits 0 # DTB read hits 364system.cpu.itb.read_misses 0 # DTB read misses 365system.cpu.itb.write_hits 0 # DTB write hits 366system.cpu.itb.write_misses 0 # DTB write misses 367system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 368system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 369system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 370system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 371system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 372system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 373system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 374system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 375system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 376system.cpu.itb.read_accesses 0 # DTB read accesses 377system.cpu.itb.write_accesses 0 # DTB write accesses 378system.cpu.itb.inst_accesses 0 # ITB inst accesses 379system.cpu.itb.hits 0 # DTB hits 380system.cpu.itb.misses 0 # DTB misses 381system.cpu.itb.accesses 0 # DTB accesses 382system.cpu.workload.num_syscalls 13 # Number of system calls 383system.cpu.numCycles 37483 # number of cpu cycles simulated 384system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 385system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 386system.cpu.fetch.icacheStallCycles 6059 # Number of cycles fetch is stalled on an Icache miss 387system.cpu.fetch.Insts 11274 # Number of instructions fetch has processed 388system.cpu.fetch.Branches 2341 # Number of branches that fetch encountered 389system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken 390system.cpu.fetch.Cycles 8204 # Number of cycles fetch has run and was not squashing or blocked 391system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing 392system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 393system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps 394system.cpu.fetch.IcacheWaitRetryStallCycles 363 # Number of stall cycles due to full MSHR 395system.cpu.fetch.CacheLines 3834 # Number of cache lines fetched 396system.cpu.fetch.IcacheSquashes 177 # Number of outstanding Icache misses that were squashed 397system.cpu.fetch.rateDist::samples 15601 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::mean 0.845843 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::stdev 1.199579 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::0 9385 60.16% 60.16% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::1 2463 15.79% 75.94% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::2 526 3.37% 79.32% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::3 3227 20.68% 100.00% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::total 15601 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.branchRate 0.062455 # Number of branch fetches per cycle 410system.cpu.fetch.rate 0.300776 # Number of inst fetches per cycle 411system.cpu.decode.IdleCycles 5749 # Number of cycles decode is idle 412system.cpu.decode.BlockedCycles 4322 # Number of cycles decode is blocked 413system.cpu.decode.RunCycles 5029 # Number of cycles decode is running 414system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 415system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing 416system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch 417system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction 418system.cpu.decode.DecodedInsts 9880 # Number of instructions handled by decode 419system.cpu.decode.SquashedInsts 1586 # Number of squashed instructions handled by decode 420system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing 421system.cpu.rename.IdleCycles 6811 # Number of cycles rename is idle 422system.cpu.rename.BlockCycles 1118 # Number of cycles rename is blocking 423system.cpu.rename.serializeStallCycles 2339 # count of cycles rename stalled for serializing inst 424system.cpu.rename.RunCycles 4089 # Number of cycles rename is running 425system.cpu.rename.UnblockCycles 875 # Number of cycles rename is unblocking 426system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename 427system.cpu.rename.SquashedInsts 417 # Number of squashed instructions processed by rename 428system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full 429system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 430system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full 431system.cpu.rename.SQFullEvents 772 # Number of times rename has blocked due to SQ full 432system.cpu.rename.RenamedOperands 9259 # Number of destination operands rename has renamed 433system.cpu.rename.RenameLookups 40331 # Number of register rename lookups that rename has made 434system.cpu.rename.int_rename_lookups 9781 # Number of integer rename lookups 435system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 436system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 437system.cpu.rename.UndoneMaps 3765 # Number of HB maps that are undone due to squashing 438system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 439system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 440system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer 441system.cpu.memDep0.insertedLoads 1800 # Number of loads inserted to the mem dependence unit. 442system.cpu.memDep0.insertedStores 1272 # Number of stores inserted to the mem dependence unit. 443system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 444system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 445system.cpu.iq.iqInstsAdded 8358 # Number of instructions added to the IQ (excludes non-spec) 446system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ 447system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued 448system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued 449system.cpu.iq.iqSquashedInstsExamined 3018 # Number of squashed instructions iterated over during squash; mainly for profiling 450system.cpu.iq.iqSquashedOperandsExamined 7856 # Number of squashed operands that are examined and possibly removed from graph 451system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed 452system.cpu.iq.issued_per_cycle::samples 15601 # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::mean 0.458176 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::stdev 0.848338 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::0 11391 73.01% 73.01% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::1 1965 12.60% 85.61% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::2 1598 10.24% 95.85% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::3 601 3.85% 99.71% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::4 46 0.29% 100.00% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::total 15601 # Number of insts issued each cycle 469system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 470system.cpu.iq.fu_full::IntAlu 413 28.70% 28.70% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntMult 0 0.00% 28.70% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntDiv 0 0.00% 28.70% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.70% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.70% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.70% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatMult 0 0.00% 28.70% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.70% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.70% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.70% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.70% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.70% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.70% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.70% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.70% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMult 0 0.00% 28.70% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.70% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdShift 0 0.00% 28.70% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.70% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.70% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.70% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.70% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.70% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.70% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.70% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.70% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.70% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.70% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.70% # attempts to use FU when none available 499system.cpu.iq.fu_full::MemRead 475 33.01% 61.71% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemWrite 551 38.29% 100.00% # attempts to use FU when none available 501system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 502system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 504system.cpu.iq.FU_type_0::IntAlu 4480 62.67% 62.67% # Type of FU issued 505system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.74% # Type of FU issued 506system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.74% # Type of FU issued 507system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.74% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.74% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.74% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.74% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.74% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued 533system.cpu.iq.FU_type_0::MemRead 1582 22.13% 84.92% # Type of FU issued 534system.cpu.iq.FU_type_0::MemWrite 1078 15.08% 100.00% # Type of FU issued 535system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 536system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::total 7148 # Type of FU issued 538system.cpu.iq.rate 0.190700 # Inst issue rate 539system.cpu.iq.fu_busy_cnt 1439 # FU busy when requested 540system.cpu.iq.fu_busy_rate 0.201315 # FU busy rate (busy events/executed inst) 541system.cpu.iq.int_inst_queue_reads 31476 # Number of integer instruction queue reads 542system.cpu.iq.int_inst_queue_writes 11405 # Number of integer instruction queue writes 543system.cpu.iq.int_inst_queue_wakeup_accesses 6562 # Number of integer instruction queue wakeup accesses 544system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads 545system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 546system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 547system.cpu.iq.int_alu_accesses 8559 # Number of integer alu accesses 548system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses 549system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores 550system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 551system.cpu.iew.lsq.thread0.squashedLoads 773 # Number of loads squashed 552system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 553system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 554system.cpu.iew.lsq.thread0.squashedStores 334 # Number of stores squashed 555system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 556system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 557system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled 558system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 559system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 560system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing 561system.cpu.iew.iewBlockCycles 385 # Number of cycles IEW is blocking 562system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking 563system.cpu.iew.iewDispatchedInsts 8410 # Number of instructions dispatched to IQ 564system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 565system.cpu.iew.iewDispLoadInsts 1800 # Number of dispatched load instructions 566system.cpu.iew.iewDispStoreInsts 1272 # Number of dispatched store instructions 567system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 568system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 569system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 570system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 571system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly 572system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly 573system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute 574system.cpu.iew.iewExecutedInsts 6751 # Number of executed instructions 575system.cpu.iew.iewExecLoadInsts 1398 # Number of load instructions executed 576system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute 577system.cpu.iew.exec_swp 0 # number of swp insts executed 578system.cpu.iew.exec_nop 14 # number of nop insts executed 579system.cpu.iew.exec_refs 2419 # number of memory reference insts executed 580system.cpu.iew.exec_branches 1275 # Number of branches executed 581system.cpu.iew.exec_stores 1021 # Number of stores executed 582system.cpu.iew.exec_rate 0.180108 # Inst execution rate 583system.cpu.iew.wb_sent 6621 # cumulative count of insts sent to commit 584system.cpu.iew.wb_count 6578 # cumulative count of insts written-back 585system.cpu.iew.wb_producers 2993 # num instructions producing a value 586system.cpu.iew.wb_consumers 5408 # num instructions consuming a value 587system.cpu.iew.wb_rate 0.175493 # insts written-back per cycle 588system.cpu.iew.wb_fanout 0.553439 # average fanout of values written-back 589system.cpu.commit.commitSquashedInsts 2586 # The number of squashed insts skipped by commit 590system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 591system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted 592system.cpu.commit.committed_per_cycle::samples 15057 # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::mean 0.357176 # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::stdev 1.003286 # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::0 12412 82.43% 82.43% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::1 1386 9.21% 91.64% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::2 592 3.93% 95.57% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::3 296 1.97% 97.54% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::4 173 1.15% 98.68% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::5 78 0.52% 99.20% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::6 45 0.30% 99.50% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::7 32 0.21% 99.71% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::total 15057 # Number of insts commited each cycle 609system.cpu.commit.committedInsts 4592 # Number of instructions committed 610system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 611system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 612system.cpu.commit.refs 1965 # Number of memory references committed 613system.cpu.commit.loads 1027 # Number of loads committed 614system.cpu.commit.membars 12 # Number of memory barriers committed 615system.cpu.commit.branches 1008 # Number of branches committed 616system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 617system.cpu.commit.int_insts 4624 # Number of committed integer instructions. 618system.cpu.commit.function_calls 82 # Number of function calls committed. 619system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 620system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 621system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 622system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 623system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 624system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 625system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 626system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 627system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 628system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 630system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 631system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 649system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 650system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 651system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 652system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 653system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 654system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached 655system.cpu.rob.rob_reads 22821 # The number of ROB reads 656system.cpu.rob.rob_writes 16478 # The number of ROB writes 657system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself 658system.cpu.idleCycles 21882 # Total number of cycles that the CPU has spent unscheduled due to idling 659system.cpu.committedInsts 4592 # Number of Instructions Simulated 660system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 661system.cpu.cpi 8.162674 # CPI: Cycles Per Instruction 662system.cpu.cpi_total 8.162674 # CPI: Total CPI of All Threads 663system.cpu.ipc 0.122509 # IPC: Instructions Per Cycle 664system.cpu.ipc_total 0.122509 # IPC: Total IPC of All Threads 665system.cpu.int_regfile_reads 6722 # number of integer regfile reads 666system.cpu.int_regfile_writes 3755 # number of integer regfile writes 667system.cpu.fp_regfile_reads 16 # number of floating regfile reads 668system.cpu.cc_regfile_reads 23977 # number of cc regfile reads 669system.cpu.cc_regfile_writes 2903 # number of cc regfile writes 670system.cpu.misc_regfile_reads 2611 # number of misc regfile reads 671system.cpu.misc_regfile_writes 24 # number of misc regfile writes 672system.cpu.dcache.tags.replacements 1 # number of replacements 673system.cpu.dcache.tags.tagsinuse 84.551975 # Cycle average of tags in use 674system.cpu.dcache.tags.total_refs 1908 # Total number of references to valid blocks. 675system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. 676system.cpu.dcache.tags.avg_refs 13.342657 # Average number of references to valid blocks. 677system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 678system.cpu.dcache.tags.occ_blocks::cpu.data 84.551975 # Average occupied blocks per requestor 679system.cpu.dcache.tags.occ_percent::cpu.data 0.165141 # Average percentage of cache occupancy 680system.cpu.dcache.tags.occ_percent::total 0.165141 # Average percentage of cache occupancy 681system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 682system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 683system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id 684system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id 685system.cpu.dcache.tags.tag_accesses 4677 # Number of tag accesses 686system.cpu.dcache.tags.data_accesses 4677 # Number of data accesses 687system.cpu.dcache.ReadReq_hits::cpu.data 1166 # number of ReadReq hits 688system.cpu.dcache.ReadReq_hits::total 1166 # number of ReadReq hits 689system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 690system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 691system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 692system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 693system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 694system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 695system.cpu.dcache.demand_hits::cpu.data 1888 # number of demand (read+write) hits 696system.cpu.dcache.demand_hits::total 1888 # number of demand (read+write) hits 697system.cpu.dcache.overall_hits::cpu.data 1888 # number of overall hits 698system.cpu.dcache.overall_hits::total 1888 # number of overall hits 699system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses 700system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses 701system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 702system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 703system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 704system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 705system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses 706system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses 707system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses 708system.cpu.dcache.overall_misses::total 357 # number of overall misses 709system.cpu.dcache.ReadReq_miss_latency::cpu.data 10689500 # number of ReadReq miss cycles 710system.cpu.dcache.ReadReq_miss_latency::total 10689500 # number of ReadReq miss cycles 711system.cpu.dcache.WriteReq_miss_latency::cpu.data 7727500 # number of WriteReq miss cycles 712system.cpu.dcache.WriteReq_miss_latency::total 7727500 # number of WriteReq miss cycles 713system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles 714system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles 715system.cpu.dcache.demand_miss_latency::cpu.data 18417000 # number of demand (read+write) miss cycles 716system.cpu.dcache.demand_miss_latency::total 18417000 # number of demand (read+write) miss cycles 717system.cpu.dcache.overall_miss_latency::cpu.data 18417000 # number of overall miss cycles 718system.cpu.dcache.overall_miss_latency::total 18417000 # number of overall miss cycles 719system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) 720system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) 721system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 722system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 723system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 724system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 725system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 726system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 727system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses 728system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses 729system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses 730system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses 731system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124625 # miss rate for ReadReq accesses 732system.cpu.dcache.ReadReq_miss_rate::total 0.124625 # miss rate for ReadReq accesses 733system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 734system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 735system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 736system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses 737system.cpu.dcache.demand_miss_rate::cpu.data 0.159020 # miss rate for demand accesses 738system.cpu.dcache.demand_miss_rate::total 0.159020 # miss rate for demand accesses 739system.cpu.dcache.overall_miss_rate::cpu.data 0.159020 # miss rate for overall accesses 740system.cpu.dcache.overall_miss_rate::total 0.159020 # miss rate for overall accesses 741system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64394.578313 # average ReadReq miss latency 742system.cpu.dcache.ReadReq_avg_miss_latency::total 64394.578313 # average ReadReq miss latency 743system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40458.115183 # average WriteReq miss latency 744system.cpu.dcache.WriteReq_avg_miss_latency::total 40458.115183 # average WriteReq miss latency 745system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency 746system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency 747system.cpu.dcache.demand_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency 748system.cpu.dcache.demand_avg_miss_latency::total 51588.235294 # average overall miss latency 749system.cpu.dcache.overall_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency 750system.cpu.dcache.overall_avg_miss_latency::total 51588.235294 # average overall miss latency 751system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 752system.cpu.dcache.blocked_cycles::no_targets 846 # number of cycles access was blocked 753system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 754system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 755system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 756system.cpu.dcache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked 757system.cpu.dcache.fast_writes 0 # number of fast writes performed 758system.cpu.dcache.cache_copies 0 # number of cache copies performed 759system.cpu.dcache.writebacks::writebacks 1 # number of writebacks 760system.cpu.dcache.writebacks::total 1 # number of writebacks 761system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 762system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 763system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 764system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 765system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 766system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 767system.cpu.dcache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits 768system.cpu.dcache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits 769system.cpu.dcache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits 770system.cpu.dcache.overall_mshr_hits::total 213 # number of overall MSHR hits 771system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 772system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 773system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 774system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 775system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 776system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 777system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 778system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses 779system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6989000 # number of ReadReq MSHR miss cycles 780system.cpu.dcache.ReadReq_mshr_miss_latency::total 6989000 # number of ReadReq MSHR miss cycles 781system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2447000 # number of WriteReq MSHR miss cycles 782system.cpu.dcache.WriteReq_mshr_miss_latency::total 2447000 # number of WriteReq MSHR miss cycles 783system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9436000 # number of demand (read+write) MSHR miss cycles 784system.cpu.dcache.demand_mshr_miss_latency::total 9436000 # number of demand (read+write) MSHR miss cycles 785system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9436000 # number of overall MSHR miss cycles 786system.cpu.dcache.overall_mshr_miss_latency::total 9436000 # number of overall MSHR miss cycles 787system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077327 # mshr miss rate for ReadReq accesses 788system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077327 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for demand accesses 792system.cpu.dcache.demand_mshr_miss_rate::total 0.064143 # mshr miss rate for demand accesses 793system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for overall accesses 794system.cpu.dcache.overall_mshr_miss_rate::total 0.064143 # mshr miss rate for overall accesses 795system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67854.368932 # average ReadReq mshr miss latency 796system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67854.368932 # average ReadReq mshr miss latency 797system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59682.926829 # average WriteReq mshr miss latency 798system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59682.926829 # average WriteReq mshr miss latency 799system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency 800system.cpu.dcache.demand_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency 801system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency 802system.cpu.dcache.overall_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency 803system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 804system.cpu.icache.tags.replacements 43 # number of replacements 805system.cpu.icache.tags.tagsinuse 137.647063 # Cycle average of tags in use 806system.cpu.icache.tags.total_refs 3470 # Total number of references to valid blocks. 807system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. 808system.cpu.icache.tags.avg_refs 11.722973 # Average number of references to valid blocks. 809system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 810system.cpu.icache.tags.occ_blocks::cpu.inst 137.647063 # Average occupied blocks per requestor 811system.cpu.icache.tags.occ_percent::cpu.inst 0.268842 # Average percentage of cache occupancy 812system.cpu.icache.tags.occ_percent::total 0.268842 # Average percentage of cache occupancy 813system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id 814system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 815system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 816system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id 817system.cpu.icache.tags.tag_accesses 7960 # Number of tag accesses 818system.cpu.icache.tags.data_accesses 7960 # Number of data accesses 819system.cpu.icache.ReadReq_hits::cpu.inst 3470 # number of ReadReq hits 820system.cpu.icache.ReadReq_hits::total 3470 # number of ReadReq hits 821system.cpu.icache.demand_hits::cpu.inst 3470 # number of demand (read+write) hits 822system.cpu.icache.demand_hits::total 3470 # number of demand (read+write) hits 823system.cpu.icache.overall_hits::cpu.inst 3470 # number of overall hits 824system.cpu.icache.overall_hits::total 3470 # number of overall hits 825system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses 826system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses 827system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses 828system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses 829system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses 830system.cpu.icache.overall_misses::total 362 # number of overall misses 831system.cpu.icache.ReadReq_miss_latency::cpu.inst 22661491 # number of ReadReq miss cycles 832system.cpu.icache.ReadReq_miss_latency::total 22661491 # number of ReadReq miss cycles 833system.cpu.icache.demand_miss_latency::cpu.inst 22661491 # number of demand (read+write) miss cycles 834system.cpu.icache.demand_miss_latency::total 22661491 # number of demand (read+write) miss cycles 835system.cpu.icache.overall_miss_latency::cpu.inst 22661491 # number of overall miss cycles 836system.cpu.icache.overall_miss_latency::total 22661491 # number of overall miss cycles 837system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses) 838system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses) 839system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses 840system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses 841system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses 842system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses 843system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094468 # miss rate for ReadReq accesses 844system.cpu.icache.ReadReq_miss_rate::total 0.094468 # miss rate for ReadReq accesses 845system.cpu.icache.demand_miss_rate::cpu.inst 0.094468 # miss rate for demand accesses 846system.cpu.icache.demand_miss_rate::total 0.094468 # miss rate for demand accesses 847system.cpu.icache.overall_miss_rate::cpu.inst 0.094468 # miss rate for overall accesses 848system.cpu.icache.overall_miss_rate::total 0.094468 # miss rate for overall accesses 849system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62600.803867 # average ReadReq miss latency 850system.cpu.icache.ReadReq_avg_miss_latency::total 62600.803867 # average ReadReq miss latency 851system.cpu.icache.demand_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency 852system.cpu.icache.demand_avg_miss_latency::total 62600.803867 # average overall miss latency 853system.cpu.icache.overall_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency 854system.cpu.icache.overall_avg_miss_latency::total 62600.803867 # average overall miss latency 855system.cpu.icache.blocked_cycles::no_mshrs 8953 # number of cycles access was blocked 856system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked 857system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked 858system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 859system.cpu.icache.avg_blocked_cycles::no_mshrs 93.260417 # average number of cycles each access was blocked 860system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked 861system.cpu.icache.fast_writes 0 # number of fast writes performed 862system.cpu.icache.cache_copies 0 # number of cache copies performed 863system.cpu.icache.writebacks::writebacks 43 # number of writebacks 864system.cpu.icache.writebacks::total 43 # number of writebacks 865system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits 866system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits 867system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits 868system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits 869system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits 870system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits 871system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses 872system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses 873system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses 874system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses 875system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses 876system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses 877system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19893491 # number of ReadReq MSHR miss cycles 878system.cpu.icache.ReadReq_mshr_miss_latency::total 19893491 # number of ReadReq MSHR miss cycles 879system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19893491 # number of demand (read+write) MSHR miss cycles 880system.cpu.icache.demand_mshr_miss_latency::total 19893491 # number of demand (read+write) MSHR miss cycles 881system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19893491 # number of overall MSHR miss cycles 882system.cpu.icache.overall_mshr_miss_latency::total 19893491 # number of overall MSHR miss cycles 883system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for ReadReq accesses 884system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077505 # mshr miss rate for ReadReq accesses 885system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for demand accesses 886system.cpu.icache.demand_mshr_miss_rate::total 0.077505 # mshr miss rate for demand accesses 887system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for overall accesses 888system.cpu.icache.overall_mshr_miss_rate::total 0.077505 # mshr miss rate for overall accesses 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66981.451178 # average ReadReq mshr miss latency 890system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66981.451178 # average ReadReq mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency 892system.cpu.icache.demand_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency 894system.cpu.icache.overall_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency 895system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 896system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 897system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 898system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 899system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 900system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 901system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 902system.cpu.l2cache.tags.replacements 0 # number of replacements 903system.cpu.l2cache.tags.tagsinuse 19.860815 # Cycle average of tags in use 904system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. 905system.cpu.l2cache.tags.sampled_refs 48 # Sample count of references to valid blocks. 906system.cpu.l2cache.tags.avg_refs 0.208333 # Average number of references to valid blocks. 907system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 908system.cpu.l2cache.tags.occ_blocks::writebacks 10.581774 # Average occupied blocks per requestor 909system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.279041 # Average occupied blocks per requestor 910system.cpu.l2cache.tags.occ_percent::writebacks 0.000646 # Average percentage of cache occupancy 911system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000566 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::total 0.001212 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id 914system.cpu.l2cache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id 915system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 916system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 918system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 919system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id 920system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id 921system.cpu.l2cache.tags.tag_accesses 7643 # Number of tag accesses 922system.cpu.l2cache.tags.data_accesses 7643 # Number of data accesses 923system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 924system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 925system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 926system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 927system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 7 # number of ReadCleanReq hits 928system.cpu.l2cache.ReadCleanReq_hits::total 7 # number of ReadCleanReq hits 929system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 930system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 931system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits 932system.cpu.l2cache.demand_hits::cpu.data 13 # number of demand (read+write) hits 933system.cpu.l2cache.demand_hits::total 20 # number of demand (read+write) hits 934system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits 935system.cpu.l2cache.overall_hits::cpu.data 13 # number of overall hits 936system.cpu.l2cache.overall_hits::total 20 # number of overall hits 937system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses 938system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses 939system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 290 # number of ReadCleanReq misses 940system.cpu.l2cache.ReadCleanReq_misses::total 290 # number of ReadCleanReq misses 941system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 942system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses 943system.cpu.l2cache.demand_misses::cpu.inst 290 # number of demand (read+write) misses 944system.cpu.l2cache.demand_misses::cpu.data 131 # number of demand (read+write) misses 945system.cpu.l2cache.demand_misses::total 421 # number of demand (read+write) misses 946system.cpu.l2cache.overall_misses::cpu.inst 290 # number of overall misses 947system.cpu.l2cache.overall_misses::cpu.data 131 # number of overall misses 948system.cpu.l2cache.overall_misses::total 421 # number of overall misses 949system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2313000 # number of ReadExReq miss cycles 950system.cpu.l2cache.ReadExReq_miss_latency::total 2313000 # number of ReadExReq miss cycles 951system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19544000 # number of ReadCleanReq miss cycles 952system.cpu.l2cache.ReadCleanReq_miss_latency::total 19544000 # number of ReadCleanReq miss cycles 953system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6815000 # number of ReadSharedReq miss cycles 954system.cpu.l2cache.ReadSharedReq_miss_latency::total 6815000 # number of ReadSharedReq miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.inst 19544000 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::cpu.data 9128000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.demand_miss_latency::total 28672000 # number of demand (read+write) miss cycles 958system.cpu.l2cache.overall_miss_latency::cpu.inst 19544000 # number of overall miss cycles 959system.cpu.l2cache.overall_miss_latency::cpu.data 9128000 # number of overall miss cycles 960system.cpu.l2cache.overall_miss_latency::total 28672000 # number of overall miss cycles 961system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 962system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 963system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 964system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 965system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 297 # number of ReadCleanReq accesses(hits+misses) 966system.cpu.l2cache.ReadCleanReq_accesses::total 297 # number of ReadCleanReq accesses(hits+misses) 967system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 968system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) 969system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses 970system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses 971system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 972system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses 973system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses 974system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 975system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses 976system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses 977system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976431 # miss rate for ReadCleanReq accesses 978system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976431 # miss rate for ReadCleanReq accesses 979system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.980583 # miss rate for ReadSharedReq accesses 980system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.980583 # miss rate for ReadSharedReq accesses 981system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976431 # miss rate for demand accesses 982system.cpu.l2cache.demand_miss_rate::cpu.data 0.909722 # miss rate for demand accesses 983system.cpu.l2cache.demand_miss_rate::total 0.954649 # miss rate for demand accesses 984system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976431 # miss rate for overall accesses 985system.cpu.l2cache.overall_miss_rate::cpu.data 0.909722 # miss rate for overall accesses 986system.cpu.l2cache.overall_miss_rate::total 0.954649 # miss rate for overall accesses 987system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77100 # average ReadExReq miss latency 988system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77100 # average ReadExReq miss latency 989system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67393.103448 # average ReadCleanReq miss latency 990system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67393.103448 # average ReadCleanReq miss latency 991system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67475.247525 # average ReadSharedReq miss latency 992system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67475.247525 # average ReadSharedReq miss latency 993system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency 994system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency 995system.cpu.l2cache.demand_avg_miss_latency::total 68104.513064 # average overall miss latency 996system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency 997system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency 998system.cpu.l2cache.overall_avg_miss_latency::total 68104.513064 # average overall miss latency 999system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1000system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1001system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1002system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1003system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1004system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1005system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1006system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1007system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1008system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1009system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 1010system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 1011system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1012system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1013system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1014system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1015system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 1016system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 1017system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses 1018system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses 1019system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses 1020system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses 1021system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 289 # number of ReadCleanReq MSHR misses 1022system.cpu.l2cache.ReadCleanReq_mshr_misses::total 289 # number of ReadCleanReq MSHR misses 1023system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 1024system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses 1025system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses 1026system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 1027system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses 1028system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses 1029system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses 1030system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses 1031system.cpu.l2cache.overall_mshr_misses::total 468 # number of overall MSHR misses 1032system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles 1033system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles 1034system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2133000 # number of ReadExReq MSHR miss cycles 1035system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2133000 # number of ReadExReq MSHR miss cycles 1036system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17760500 # number of ReadCleanReq MSHR miss cycles 1037system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17760500 # number of ReadCleanReq MSHR miss cycles 1038system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5946500 # number of ReadSharedReq MSHR miss cycles 1039system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5946500 # number of ReadSharedReq MSHR miss cycles 1040system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17760500 # number of demand (read+write) MSHR miss cycles 1041system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8079500 # number of demand (read+write) MSHR miss cycles 1042system.cpu.l2cache.demand_mshr_miss_latency::total 25840000 # number of demand (read+write) MSHR miss cycles 1043system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17760500 # number of overall MSHR miss cycles 1044system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8079500 # number of overall MSHR miss cycles 1045system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles 1046system.cpu.l2cache.overall_mshr_miss_latency::total 27465926 # number of overall MSHR miss cycles 1047system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1048system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1049system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1050system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 1051system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for ReadCleanReq accesses 1052system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.973064 # mshr miss rate for ReadCleanReq accesses 1053system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses 1054system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses 1055system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for demand accesses 1056system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses 1057system.cpu.l2cache.demand_mshr_miss_rate::total 0.941043 # mshr miss rate for demand accesses 1058system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for overall accesses 1059system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses 1060system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1061system.cpu.l2cache.overall_mshr_miss_rate::total 1.061224 # mshr miss rate for overall accesses 1062system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average HardPFReq mshr miss latency 1063system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 30677.849057 # average HardPFReq mshr miss latency 1064system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71100 # average ReadExReq mshr miss latency 1065system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71100 # average ReadExReq mshr miss latency 1066system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61455.017301 # average ReadCleanReq mshr miss latency 1067system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61455.017301 # average ReadCleanReq mshr miss latency 1068system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61942.708333 # average ReadSharedReq mshr miss latency 1069system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61942.708333 # average ReadSharedReq mshr miss latency 1070system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency 1071system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency 1072system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62265.060241 # average overall mshr miss latency 1073system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency 1074system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency 1075system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average overall mshr miss latency 1076system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58687.876068 # average overall mshr miss latency 1077system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1078system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. 1079system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1080system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1081system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # Total number of snoops made to the snoop filter. 1082system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1083system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1084system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
1085system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution	1085system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution
1086system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution 1087system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution 1088system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1089system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1090system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution 1091system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution	1086system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution 1087system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution 1088system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1089system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1090system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution 1091system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
1092system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) 1093system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) 1094system.cpu.toL2Bus.pkt_count::total 913 # Packet count per connected master and slave (bytes) 1095system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21056 # Cumulative packet size per connected master and slave (bytes) 1096system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) 1097system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)	1092system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 636 # Packet count per connected master and slave (bytes) 1093system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes) 1094system.cpu.toL2Bus.pkt_count::total 924 # Packet count per connected master and slave (bytes) 1095system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21696 # Cumulative packet size per connected master and slave (bytes) 1096system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) 1097system.cpu.toL2Bus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes)
1098system.cpu.toL2Bus.snoops 452 # Total snoops (count) 1099system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram 1100system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram 1101system.cpu.toL2Bus.snoop_fanout::stdev 0.582857 # Request fanout histogram 1102system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1103system.cpu.toL2Bus.snoop_fanout::0 443 49.61% 49.61% # Request fanout histogram 1104system.cpu.toL2Bus.snoop_fanout::1 409 45.80% 95.41% # Request fanout histogram 1105system.cpu.toL2Bus.snoop_fanout::2 41 4.59% 100.00% # Request fanout histogram 1106system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1107system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1108system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1109system.cpu.toL2Bus.snoop_fanout::total 893 # Request fanout histogram 1110system.cpu.toL2Bus.reqLayer0.occupancy 286500 # Layer occupancy (ticks) 1111system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 1112system.cpu.toL2Bus.respLayer0.occupancy 444499 # Layer occupancy (ticks) 1113system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 1114system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) 1115system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 1116system.membus.trans_dist::ReadResp 410 # Transaction distribution 1117system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1118system.membus.trans_dist::ReadExResp 30 # Transaction distribution 1119system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution 1120system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 882 # Packet count per connected master and slave (bytes) 1121system.membus.pkt_count::total 882 # Packet count per connected master and slave (bytes) 1122system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28160 # Cumulative packet size per connected master and slave (bytes) 1123system.membus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 1124system.membus.snoops 0 # Total snoops (count) 1125system.membus.snoop_fanout::samples 442 # Request fanout histogram 1126system.membus.snoop_fanout::mean 0 # Request fanout histogram 1127system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1128system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1129system.membus.snoop_fanout::0 442 100.00% 100.00% # Request fanout histogram 1130system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1131system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1132system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1133system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1134system.membus.snoop_fanout::total 442 # Request fanout histogram 1135system.membus.reqLayer0.occupancy 559944 # Layer occupancy (ticks) 1136system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 1137system.membus.respLayer1.occupancy 2320000 # Layer occupancy (ticks) 1138system.membus.respLayer1.utilization 12.4 # Layer utilization (%) 1139 1140---------- End Simulation Statistics ----------	1098system.cpu.toL2Bus.snoops 452 # Total snoops (count) 1099system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram 1100system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram 1101system.cpu.toL2Bus.snoop_fanout::stdev 0.582857 # Request fanout histogram 1102system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1103system.cpu.toL2Bus.snoop_fanout::0 443 49.61% 49.61% # Request fanout histogram 1104system.cpu.toL2Bus.snoop_fanout::1 409 45.80% 95.41% # Request fanout histogram 1105system.cpu.toL2Bus.snoop_fanout::2 41 4.59% 100.00% # Request fanout histogram 1106system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1107system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1108system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1109system.cpu.toL2Bus.snoop_fanout::total 893 # Request fanout histogram 1110system.cpu.toL2Bus.reqLayer0.occupancy 286500 # Layer occupancy (ticks) 1111system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 1112system.cpu.toL2Bus.respLayer0.occupancy 444499 # Layer occupancy (ticks) 1113system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 1114system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) 1115system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 1116system.membus.trans_dist::ReadResp 410 # Transaction distribution 1117system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1118system.membus.trans_dist::ReadExResp 30 # Transaction distribution 1119system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution 1120system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 882 # Packet count per connected master and slave (bytes) 1121system.membus.pkt_count::total 882 # Packet count per connected master and slave (bytes) 1122system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28160 # Cumulative packet size per connected master and slave (bytes) 1123system.membus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 1124system.membus.snoops 0 # Total snoops (count) 1125system.membus.snoop_fanout::samples 442 # Request fanout histogram 1126system.membus.snoop_fanout::mean 0 # Request fanout histogram 1127system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1128system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1129system.membus.snoop_fanout::0 442 100.00% 100.00% # Request fanout histogram 1130system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1131system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1132system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1133system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1134system.membus.snoop_fanout::total 442 # Request fanout histogram 1135system.membus.reqLayer0.occupancy 559944 # Layer occupancy (ticks) 1136system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 1137system.membus.respLayer1.occupancy 2320000 # Layer occupancy (ticks) 1138system.membus.respLayer1.utilization 12.4 # Layer utilization (%) 1139 1140---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000019 # Number of seconds simulated
4sim_ticks 18741000 # Number of ticks simulated
5final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 27191 # Simulator instruction rate (inst/s)
8host_op_rate 31839 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 110934081 # Simulator tick rate (ticks/s)
10host_mem_usage 245436 # Number of bytes of host memory used
11host_seconds 0.17 # Real time elapsed on the host

7host_inst_rate 84742 # Simulator instruction rate (inst/s)
8host_op_rate 99228 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 345728368 # Simulator tick rate (ticks/s)
10host_mem_usage 266024 # Number of bytes of host memory used
11host_seconds 0.05 # Real time elapsed on the host

12sim_insts 4592 # Number of instructions simulated
13sim_ops 5378 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 18432 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory
19system.physmem.bytes_read::total 28224 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 18432 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 18432 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 288 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 441 # Number of read requests responded to by this memory
26system.physmem.bw_read::cpu.inst 983512086 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 430286538 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::cpu.l2cache.prefetcher 92204258 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::total 1506002881 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::cpu.inst 983512086 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::total 983512086 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_total::cpu.inst 983512086 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.bw_total::cpu.data 430286538 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.l2cache.prefetcher 92204258 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::total 1506002881 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.readReqs 442 # Number of read requests accepted
37system.physmem.writeReqs 0 # Number of write requests accepted
38system.physmem.readBursts 442 # Number of DRAM read bursts, including those serviced by the write queue
39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
40system.physmem.bytesReadDRAM 28288 # Total number of bytes read from DRAM
41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
43system.physmem.bytesReadSys 28288 # Total read bytes from the system interface side
44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
48system.physmem.perBankRdBursts::0 101 # Per bank write bursts
49system.physmem.perBankRdBursts::1 48 # Per bank write bursts
50system.physmem.perBankRdBursts::2 19 # Per bank write bursts
51system.physmem.perBankRdBursts::3 44 # Per bank write bursts
52system.physmem.perBankRdBursts::4 19 # Per bank write bursts
53system.physmem.perBankRdBursts::5 37 # Per bank write bursts
54system.physmem.perBankRdBursts::6 46 # Per bank write bursts
55system.physmem.perBankRdBursts::7 10 # Per bank write bursts
56system.physmem.perBankRdBursts::8 4 # Per bank write bursts
57system.physmem.perBankRdBursts::9 8 # Per bank write bursts
58system.physmem.perBankRdBursts::10 27 # Per bank write bursts
59system.physmem.perBankRdBursts::11 47 # Per bank write bursts
60system.physmem.perBankRdBursts::12 17 # Per bank write bursts
61system.physmem.perBankRdBursts::13 8 # Per bank write bursts
62system.physmem.perBankRdBursts::14 0 # Per bank write bursts
63system.physmem.perBankRdBursts::15 7 # Per bank write bursts
64system.physmem.perBankWrBursts::0 0 # Per bank write bursts
65system.physmem.perBankWrBursts::1 0 # Per bank write bursts
66system.physmem.perBankWrBursts::2 0 # Per bank write bursts
67system.physmem.perBankWrBursts::3 0 # Per bank write bursts
68system.physmem.perBankWrBursts::4 0 # Per bank write bursts
69system.physmem.perBankWrBursts::5 0 # Per bank write bursts
70system.physmem.perBankWrBursts::6 0 # Per bank write bursts
71system.physmem.perBankWrBursts::7 0 # Per bank write bursts
72system.physmem.perBankWrBursts::8 0 # Per bank write bursts
73system.physmem.perBankWrBursts::9 0 # Per bank write bursts
74system.physmem.perBankWrBursts::10 0 # Per bank write bursts
75system.physmem.perBankWrBursts::11 0 # Per bank write bursts
76system.physmem.perBankWrBursts::12 0 # Per bank write bursts
77system.physmem.perBankWrBursts::13 0 # Per bank write bursts
78system.physmem.perBankWrBursts::14 0 # Per bank write bursts
79system.physmem.perBankWrBursts::15 0 # Per bank write bursts
80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
82system.physmem.totGap 18727500 # Total gap between requests
83system.physmem.readPktSize::0 0 # Read request sizes (log2)
84system.physmem.readPktSize::1 0 # Read request sizes (log2)
85system.physmem.readPktSize::2 0 # Read request sizes (log2)
86system.physmem.readPktSize::3 0 # Read request sizes (log2)
87system.physmem.readPktSize::4 0 # Read request sizes (log2)
88system.physmem.readPktSize::5 0 # Read request sizes (log2)
89system.physmem.readPktSize::6 442 # Read request sizes (log2)
90system.physmem.writePktSize::0 0 # Write request sizes (log2)
91system.physmem.writePktSize::1 0 # Write request sizes (log2)
92system.physmem.writePktSize::2 0 # Write request sizes (log2)
93system.physmem.writePktSize::3 0 # Write request sizes (log2)
94system.physmem.writePktSize::4 0 # Write request sizes (log2)
95system.physmem.writePktSize::5 0 # Write request sizes (log2)
96system.physmem.writePktSize::6 0 # Write request sizes (log2)
97system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
193system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::mean 425.650794 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::gmean 288.378165 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::stdev 357.476918 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::128-255 21 33.33% 44.44% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::640-767 5 7.94% 76.19% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
206system.physmem.totQLat 3434000 # Total ticks spent queuing
207system.physmem.totMemAccLat 11721500 # Total ticks spent from burst creation until serviced by the DRAM
208system.physmem.totBusLat 2210000 # Total ticks spent in databus transfers
209system.physmem.avgQLat 7769.23 # Average queueing delay per DRAM burst
210system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
211system.physmem.avgMemAccLat 26519.23 # Average memory access latency per DRAM burst
212system.physmem.avgRdBW 1509.42 # Average DRAM read bandwidth in MiByte/s
213system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
214system.physmem.avgRdBWSys 1509.42 # Average system read bandwidth in MiByte/s
215system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
216system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
217system.physmem.busUtil 11.79 # Data bus utilization in percentage
218system.physmem.busUtilRead 11.79 # Data bus utilization in percentage for reads
219system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
220system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing
221system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
222system.physmem.readRowHits 370 # Number of row buffer hits during reads
223system.physmem.writeRowHits 0 # Number of row buffer hits during writes
224system.physmem.readRowHitRate 83.71 # Row buffer hit rate for reads
225system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
226system.physmem.avgGap 42369.91 # Average gap between requests
227system.physmem.pageHitRate 83.71 # Row buffer hit rate, read and write combined
228system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
229system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
230system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ)
231system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
232system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
233system.physmem_0.actBackEnergy 10786680 # Energy for active background per rank (pJ)
234system.physmem_0.preBackEnergy 37500 # Energy for precharge background per rank (pJ)
235system.physmem_0.totalEnergy 14457615 # Total energy per rank (pJ)
236system.physmem_0.averagePower 913.160587 # Core power per rank (mW)
237system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states
238system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
239system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
240system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states
241system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
242system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
243system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
244system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ)
245system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
246system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
247system.physmem_1.actBackEnergy 9859005 # Energy for active background per rank (pJ)
248system.physmem_1.preBackEnergy 851250 # Energy for precharge background per rank (pJ)
249system.physmem_1.totalEnergy 12737220 # Total energy per rank (pJ)
250system.physmem_1.averagePower 804.498342 # Core power per rank (mW)
251system.physmem_1.memoryStateTime::IDLE 2184750 # Time in different power states
252system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
253system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
254system.physmem_1.memoryStateTime::ACT 13949750 # Time in different power states
255system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
256system.cpu.branchPred.lookups 2341 # Number of BP lookups
257system.cpu.branchPred.condPredicted 1389 # Number of conditional branches predicted
258system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect
259system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups
260system.cpu.branchPred.BTBHits 447 # Number of BTB hits
261system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
262system.cpu.branchPred.BTBHitPct 53.341289 # BTB Hit Percentage
263system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target.
264system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions.
265system.cpu_clk_domain.clock 500 # Clock period in ticks
266system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
275system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
276system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
277system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
278system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
279system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
284system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
285system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
286system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
287system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
288system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
289system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
290system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
291system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
292system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
293system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
294system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
295system.cpu.dtb.walker.walks 0 # Table walker walks requested
296system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
297system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
298system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
299system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
300system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
301system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.inst_hits 0 # ITB inst hits
304system.cpu.dtb.inst_misses 0 # ITB inst misses
305system.cpu.dtb.read_hits 0 # DTB read hits
306system.cpu.dtb.read_misses 0 # DTB read misses
307system.cpu.dtb.write_hits 0 # DTB write hits
308system.cpu.dtb.write_misses 0 # DTB write misses
309system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
310system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
311system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
312system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
313system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
314system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
315system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
316system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
317system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
318system.cpu.dtb.read_accesses 0 # DTB read accesses
319system.cpu.dtb.write_accesses 0 # DTB write accesses
320system.cpu.dtb.inst_accesses 0 # ITB inst accesses
321system.cpu.dtb.hits 0 # DTB hits
322system.cpu.dtb.misses 0 # DTB misses
323system.cpu.dtb.accesses 0 # DTB accesses
324system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
325system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
333system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
334system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
335system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
336system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
337system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
338system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
339system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
342system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
343system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
344system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
345system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
346system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
347system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
348system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
349system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
350system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
351system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
352system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
353system.cpu.itb.walker.walks 0 # Table walker walks requested
354system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
355system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
356system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
357system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
358system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
359system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
360system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
361system.cpu.itb.inst_hits 0 # ITB inst hits
362system.cpu.itb.inst_misses 0 # ITB inst misses
363system.cpu.itb.read_hits 0 # DTB read hits
364system.cpu.itb.read_misses 0 # DTB read misses
365system.cpu.itb.write_hits 0 # DTB write hits
366system.cpu.itb.write_misses 0 # DTB write misses
367system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
368system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
369system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
370system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
371system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
372system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
373system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
374system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
375system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
376system.cpu.itb.read_accesses 0 # DTB read accesses
377system.cpu.itb.write_accesses 0 # DTB write accesses
378system.cpu.itb.inst_accesses 0 # ITB inst accesses
379system.cpu.itb.hits 0 # DTB hits
380system.cpu.itb.misses 0 # DTB misses
381system.cpu.itb.accesses 0 # DTB accesses
382system.cpu.workload.num_syscalls 13 # Number of system calls
383system.cpu.numCycles 37483 # number of cpu cycles simulated
384system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
385system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
386system.cpu.fetch.icacheStallCycles 6059 # Number of cycles fetch is stalled on an Icache miss
387system.cpu.fetch.Insts 11274 # Number of instructions fetch has processed
388system.cpu.fetch.Branches 2341 # Number of branches that fetch encountered
389system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken
390system.cpu.fetch.Cycles 8204 # Number of cycles fetch has run and was not squashing or blocked
391system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing
392system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
393system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps
394system.cpu.fetch.IcacheWaitRetryStallCycles 363 # Number of stall cycles due to full MSHR
395system.cpu.fetch.CacheLines 3834 # Number of cache lines fetched
396system.cpu.fetch.IcacheSquashes 177 # Number of outstanding Icache misses that were squashed
397system.cpu.fetch.rateDist::samples 15601 # Number of instructions fetched each cycle (Total)
398system.cpu.fetch.rateDist::mean 0.845843 # Number of instructions fetched each cycle (Total)
399system.cpu.fetch.rateDist::stdev 1.199579 # Number of instructions fetched each cycle (Total)
400system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
401system.cpu.fetch.rateDist::0 9385 60.16% 60.16% # Number of instructions fetched each cycle (Total)
402system.cpu.fetch.rateDist::1 2463 15.79% 75.94% # Number of instructions fetched each cycle (Total)
403system.cpu.fetch.rateDist::2 526 3.37% 79.32% # Number of instructions fetched each cycle (Total)
404system.cpu.fetch.rateDist::3 3227 20.68% 100.00% # Number of instructions fetched each cycle (Total)
405system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
406system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
407system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
408system.cpu.fetch.rateDist::total 15601 # Number of instructions fetched each cycle (Total)
409system.cpu.fetch.branchRate 0.062455 # Number of branch fetches per cycle
410system.cpu.fetch.rate 0.300776 # Number of inst fetches per cycle
411system.cpu.decode.IdleCycles 5749 # Number of cycles decode is idle
412system.cpu.decode.BlockedCycles 4322 # Number of cycles decode is blocked
413system.cpu.decode.RunCycles 5029 # Number of cycles decode is running
414system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking
415system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing
416system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch
417system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction
418system.cpu.decode.DecodedInsts 9880 # Number of instructions handled by decode
419system.cpu.decode.SquashedInsts 1586 # Number of squashed instructions handled by decode
420system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing
421system.cpu.rename.IdleCycles 6811 # Number of cycles rename is idle
422system.cpu.rename.BlockCycles 1118 # Number of cycles rename is blocking
423system.cpu.rename.serializeStallCycles 2339 # count of cycles rename stalled for serializing inst
424system.cpu.rename.RunCycles 4089 # Number of cycles rename is running
425system.cpu.rename.UnblockCycles 875 # Number of cycles rename is unblocking
426system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename
427system.cpu.rename.SquashedInsts 417 # Number of squashed instructions processed by rename
428system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full
429system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
430system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full
431system.cpu.rename.SQFullEvents 772 # Number of times rename has blocked due to SQ full
432system.cpu.rename.RenamedOperands 9259 # Number of destination operands rename has renamed
433system.cpu.rename.RenameLookups 40331 # Number of register rename lookups that rename has made
434system.cpu.rename.int_rename_lookups 9781 # Number of integer rename lookups
435system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
436system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
437system.cpu.rename.UndoneMaps 3765 # Number of HB maps that are undone due to squashing
438system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
439system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
440system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer
441system.cpu.memDep0.insertedLoads 1800 # Number of loads inserted to the mem dependence unit.
442system.cpu.memDep0.insertedStores 1272 # Number of stores inserted to the mem dependence unit.
443system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
444system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
445system.cpu.iq.iqInstsAdded 8358 # Number of instructions added to the IQ (excludes non-spec)
446system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
447system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued
448system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued
449system.cpu.iq.iqSquashedInstsExamined 3018 # Number of squashed instructions iterated over during squash; mainly for profiling
450system.cpu.iq.iqSquashedOperandsExamined 7856 # Number of squashed operands that are examined and possibly removed from graph
451system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
452system.cpu.iq.issued_per_cycle::samples 15601 # Number of insts issued each cycle
453system.cpu.iq.issued_per_cycle::mean 0.458176 # Number of insts issued each cycle
454system.cpu.iq.issued_per_cycle::stdev 0.848338 # Number of insts issued each cycle
455system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
456system.cpu.iq.issued_per_cycle::0 11391 73.01% 73.01% # Number of insts issued each cycle
457system.cpu.iq.issued_per_cycle::1 1965 12.60% 85.61% # Number of insts issued each cycle
458system.cpu.iq.issued_per_cycle::2 1598 10.24% 95.85% # Number of insts issued each cycle
459system.cpu.iq.issued_per_cycle::3 601 3.85% 99.71% # Number of insts issued each cycle
460system.cpu.iq.issued_per_cycle::4 46 0.29% 100.00% # Number of insts issued each cycle
461system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle
462system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
463system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
464system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
465system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
466system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
467system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle
468system.cpu.iq.issued_per_cycle::total 15601 # Number of insts issued each cycle
469system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
470system.cpu.iq.fu_full::IntAlu 413 28.70% 28.70% # attempts to use FU when none available
471system.cpu.iq.fu_full::IntMult 0 0.00% 28.70% # attempts to use FU when none available
472system.cpu.iq.fu_full::IntDiv 0 0.00% 28.70% # attempts to use FU when none available
473system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.70% # attempts to use FU when none available
474system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.70% # attempts to use FU when none available
475system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.70% # attempts to use FU when none available
476system.cpu.iq.fu_full::FloatMult 0 0.00% 28.70% # attempts to use FU when none available
477system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.70% # attempts to use FU when none available
478system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.70% # attempts to use FU when none available
479system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.70% # attempts to use FU when none available
480system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.70% # attempts to use FU when none available
481system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.70% # attempts to use FU when none available
482system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.70% # attempts to use FU when none available
483system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.70% # attempts to use FU when none available
484system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.70% # attempts to use FU when none available
485system.cpu.iq.fu_full::SimdMult 0 0.00% 28.70% # attempts to use FU when none available
486system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.70% # attempts to use FU when none available
487system.cpu.iq.fu_full::SimdShift 0 0.00% 28.70% # attempts to use FU when none available
488system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.70% # attempts to use FU when none available
489system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.70% # attempts to use FU when none available
490system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.70% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.70% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.70% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.70% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.70% # attempts to use FU when none available
495system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.70% # attempts to use FU when none available
496system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.70% # attempts to use FU when none available
497system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.70% # attempts to use FU when none available
498system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.70% # attempts to use FU when none available
499system.cpu.iq.fu_full::MemRead 475 33.01% 61.71% # attempts to use FU when none available
500system.cpu.iq.fu_full::MemWrite 551 38.29% 100.00% # attempts to use FU when none available
501system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
502system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
503system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
504system.cpu.iq.FU_type_0::IntAlu 4480 62.67% 62.67% # Type of FU issued
505system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.74% # Type of FU issued
506system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.74% # Type of FU issued
507system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.74% # Type of FU issued
508system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.74% # Type of FU issued
509system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.74% # Type of FU issued
510system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.74% # Type of FU issued
511system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.74% # Type of FU issued
512system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued
513system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued
514system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued
515system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued
516system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued
517system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued
518system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued
519system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued
520system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued
521system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued
522system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued
523system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued
524system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued
528system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued
529system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued
530system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued
531system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued
532system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued
533system.cpu.iq.FU_type_0::MemRead 1582 22.13% 84.92% # Type of FU issued
534system.cpu.iq.FU_type_0::MemWrite 1078 15.08% 100.00% # Type of FU issued
535system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
536system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
537system.cpu.iq.FU_type_0::total 7148 # Type of FU issued
538system.cpu.iq.rate 0.190700 # Inst issue rate
539system.cpu.iq.fu_busy_cnt 1439 # FU busy when requested
540system.cpu.iq.fu_busy_rate 0.201315 # FU busy rate (busy events/executed inst)
541system.cpu.iq.int_inst_queue_reads 31476 # Number of integer instruction queue reads
542system.cpu.iq.int_inst_queue_writes 11405 # Number of integer instruction queue writes
543system.cpu.iq.int_inst_queue_wakeup_accesses 6562 # Number of integer instruction queue wakeup accesses
544system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads
545system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
546system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
547system.cpu.iq.int_alu_accesses 8559 # Number of integer alu accesses
548system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses
549system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores
550system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
551system.cpu.iew.lsq.thread0.squashedLoads 773 # Number of loads squashed
552system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
553system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
554system.cpu.iew.lsq.thread0.squashedStores 334 # Number of stores squashed
555system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
556system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
557system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
558system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
559system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
560system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing
561system.cpu.iew.iewBlockCycles 385 # Number of cycles IEW is blocking
562system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
563system.cpu.iew.iewDispatchedInsts 8410 # Number of instructions dispatched to IQ
564system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
565system.cpu.iew.iewDispLoadInsts 1800 # Number of dispatched load instructions
566system.cpu.iew.iewDispStoreInsts 1272 # Number of dispatched store instructions
567system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
568system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
569system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall
570system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
571system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly
572system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
573system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute
574system.cpu.iew.iewExecutedInsts 6751 # Number of executed instructions
575system.cpu.iew.iewExecLoadInsts 1398 # Number of load instructions executed
576system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
577system.cpu.iew.exec_swp 0 # number of swp insts executed
578system.cpu.iew.exec_nop 14 # number of nop insts executed
579system.cpu.iew.exec_refs 2419 # number of memory reference insts executed
580system.cpu.iew.exec_branches 1275 # Number of branches executed
581system.cpu.iew.exec_stores 1021 # Number of stores executed
582system.cpu.iew.exec_rate 0.180108 # Inst execution rate
583system.cpu.iew.wb_sent 6621 # cumulative count of insts sent to commit
584system.cpu.iew.wb_count 6578 # cumulative count of insts written-back
585system.cpu.iew.wb_producers 2993 # num instructions producing a value
586system.cpu.iew.wb_consumers 5408 # num instructions consuming a value
587system.cpu.iew.wb_rate 0.175493 # insts written-back per cycle
588system.cpu.iew.wb_fanout 0.553439 # average fanout of values written-back
589system.cpu.commit.commitSquashedInsts 2586 # The number of squashed insts skipped by commit
590system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
591system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted
592system.cpu.commit.committed_per_cycle::samples 15057 # Number of insts commited each cycle
593system.cpu.commit.committed_per_cycle::mean 0.357176 # Number of insts commited each cycle
594system.cpu.commit.committed_per_cycle::stdev 1.003286 # Number of insts commited each cycle
595system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
596system.cpu.commit.committed_per_cycle::0 12412 82.43% 82.43% # Number of insts commited each cycle
597system.cpu.commit.committed_per_cycle::1 1386 9.21% 91.64% # Number of insts commited each cycle
598system.cpu.commit.committed_per_cycle::2 592 3.93% 95.57% # Number of insts commited each cycle
599system.cpu.commit.committed_per_cycle::3 296 1.97% 97.54% # Number of insts commited each cycle
600system.cpu.commit.committed_per_cycle::4 173 1.15% 98.68% # Number of insts commited each cycle
601system.cpu.commit.committed_per_cycle::5 78 0.52% 99.20% # Number of insts commited each cycle
602system.cpu.commit.committed_per_cycle::6 45 0.30% 99.50% # Number of insts commited each cycle
603system.cpu.commit.committed_per_cycle::7 32 0.21% 99.71% # Number of insts commited each cycle
604system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle
605system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
606system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
607system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
608system.cpu.commit.committed_per_cycle::total 15057 # Number of insts commited each cycle
609system.cpu.commit.committedInsts 4592 # Number of instructions committed
610system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
611system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
612system.cpu.commit.refs 1965 # Number of memory references committed
613system.cpu.commit.loads 1027 # Number of loads committed
614system.cpu.commit.membars 12 # Number of memory barriers committed
615system.cpu.commit.branches 1008 # Number of branches committed
616system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
617system.cpu.commit.int_insts 4624 # Number of committed integer instructions.
618system.cpu.commit.function_calls 82 # Number of function calls committed.
619system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
620system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction
621system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction
622system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction
623system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction
624system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction
625system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction
626system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction
627system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction
628system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction
629system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction
630system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction
631system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction
632system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction
633system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction
634system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction
635system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction
636system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction
637system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction
638system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction
639system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction
640system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction
641system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction
642system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction
643system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction
644system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction
645system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction
646system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction
647system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
648system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
649system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction
650system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction
651system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
652system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
653system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
654system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached
655system.cpu.rob.rob_reads 22821 # The number of ROB reads
656system.cpu.rob.rob_writes 16478 # The number of ROB writes
657system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
658system.cpu.idleCycles 21882 # Total number of cycles that the CPU has spent unscheduled due to idling
659system.cpu.committedInsts 4592 # Number of Instructions Simulated
660system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
661system.cpu.cpi 8.162674 # CPI: Cycles Per Instruction
662system.cpu.cpi_total 8.162674 # CPI: Total CPI of All Threads
663system.cpu.ipc 0.122509 # IPC: Instructions Per Cycle
664system.cpu.ipc_total 0.122509 # IPC: Total IPC of All Threads
665system.cpu.int_regfile_reads 6722 # number of integer regfile reads
666system.cpu.int_regfile_writes 3755 # number of integer regfile writes
667system.cpu.fp_regfile_reads 16 # number of floating regfile reads
668system.cpu.cc_regfile_reads 23977 # number of cc regfile reads
669system.cpu.cc_regfile_writes 2903 # number of cc regfile writes
670system.cpu.misc_regfile_reads 2611 # number of misc regfile reads
671system.cpu.misc_regfile_writes 24 # number of misc regfile writes
672system.cpu.dcache.tags.replacements 1 # number of replacements
673system.cpu.dcache.tags.tagsinuse 84.551975 # Cycle average of tags in use
674system.cpu.dcache.tags.total_refs 1908 # Total number of references to valid blocks.
675system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
676system.cpu.dcache.tags.avg_refs 13.342657 # Average number of references to valid blocks.
677system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
678system.cpu.dcache.tags.occ_blocks::cpu.data 84.551975 # Average occupied blocks per requestor
679system.cpu.dcache.tags.occ_percent::cpu.data 0.165141 # Average percentage of cache occupancy
680system.cpu.dcache.tags.occ_percent::total 0.165141 # Average percentage of cache occupancy
681system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
682system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
683system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
684system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id
685system.cpu.dcache.tags.tag_accesses 4677 # Number of tag accesses
686system.cpu.dcache.tags.data_accesses 4677 # Number of data accesses
687system.cpu.dcache.ReadReq_hits::cpu.data 1166 # number of ReadReq hits
688system.cpu.dcache.ReadReq_hits::total 1166 # number of ReadReq hits
689system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
690system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits
691system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
692system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
693system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
694system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
695system.cpu.dcache.demand_hits::cpu.data 1888 # number of demand (read+write) hits
696system.cpu.dcache.demand_hits::total 1888 # number of demand (read+write) hits
697system.cpu.dcache.overall_hits::cpu.data 1888 # number of overall hits
698system.cpu.dcache.overall_hits::total 1888 # number of overall hits
699system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses
700system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses
701system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses
702system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses
703system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
704system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
705system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses
706system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses
707system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses
708system.cpu.dcache.overall_misses::total 357 # number of overall misses
709system.cpu.dcache.ReadReq_miss_latency::cpu.data 10689500 # number of ReadReq miss cycles
710system.cpu.dcache.ReadReq_miss_latency::total 10689500 # number of ReadReq miss cycles
711system.cpu.dcache.WriteReq_miss_latency::cpu.data 7727500 # number of WriteReq miss cycles
712system.cpu.dcache.WriteReq_miss_latency::total 7727500 # number of WriteReq miss cycles
713system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles
714system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles
715system.cpu.dcache.demand_miss_latency::cpu.data 18417000 # number of demand (read+write) miss cycles
716system.cpu.dcache.demand_miss_latency::total 18417000 # number of demand (read+write) miss cycles
717system.cpu.dcache.overall_miss_latency::cpu.data 18417000 # number of overall miss cycles
718system.cpu.dcache.overall_miss_latency::total 18417000 # number of overall miss cycles
719system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses)
720system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses)
721system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
722system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
723system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
724system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
725system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
726system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
727system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses
728system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses
729system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses
730system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses
731system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124625 # miss rate for ReadReq accesses
732system.cpu.dcache.ReadReq_miss_rate::total 0.124625 # miss rate for ReadReq accesses
733system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses
734system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses
735system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
736system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
737system.cpu.dcache.demand_miss_rate::cpu.data 0.159020 # miss rate for demand accesses
738system.cpu.dcache.demand_miss_rate::total 0.159020 # miss rate for demand accesses
739system.cpu.dcache.overall_miss_rate::cpu.data 0.159020 # miss rate for overall accesses
740system.cpu.dcache.overall_miss_rate::total 0.159020 # miss rate for overall accesses
741system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64394.578313 # average ReadReq miss latency
742system.cpu.dcache.ReadReq_avg_miss_latency::total 64394.578313 # average ReadReq miss latency
743system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40458.115183 # average WriteReq miss latency
744system.cpu.dcache.WriteReq_avg_miss_latency::total 40458.115183 # average WriteReq miss latency
745system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
746system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
747system.cpu.dcache.demand_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency
748system.cpu.dcache.demand_avg_miss_latency::total 51588.235294 # average overall miss latency
749system.cpu.dcache.overall_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency
750system.cpu.dcache.overall_avg_miss_latency::total 51588.235294 # average overall miss latency
751system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
752system.cpu.dcache.blocked_cycles::no_targets 846 # number of cycles access was blocked
753system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
754system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked
755system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
756system.cpu.dcache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked
757system.cpu.dcache.fast_writes 0 # number of fast writes performed
758system.cpu.dcache.cache_copies 0 # number of cache copies performed
759system.cpu.dcache.writebacks::writebacks 1 # number of writebacks
760system.cpu.dcache.writebacks::total 1 # number of writebacks
761system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits
762system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
763system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits
764system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits
765system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
766system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
767system.cpu.dcache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits
768system.cpu.dcache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits
769system.cpu.dcache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits
770system.cpu.dcache.overall_mshr_hits::total 213 # number of overall MSHR hits
771system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses
772system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
773system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
774system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
775system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses
776system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
777system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
778system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
779system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6989000 # number of ReadReq MSHR miss cycles
780system.cpu.dcache.ReadReq_mshr_miss_latency::total 6989000 # number of ReadReq MSHR miss cycles
781system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2447000 # number of WriteReq MSHR miss cycles
782system.cpu.dcache.WriteReq_mshr_miss_latency::total 2447000 # number of WriteReq MSHR miss cycles
783system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9436000 # number of demand (read+write) MSHR miss cycles
784system.cpu.dcache.demand_mshr_miss_latency::total 9436000 # number of demand (read+write) MSHR miss cycles
785system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9436000 # number of overall MSHR miss cycles
786system.cpu.dcache.overall_mshr_miss_latency::total 9436000 # number of overall MSHR miss cycles
787system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077327 # mshr miss rate for ReadReq accesses
788system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077327 # mshr miss rate for ReadReq accesses
789system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
790system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
791system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for demand accesses
792system.cpu.dcache.demand_mshr_miss_rate::total 0.064143 # mshr miss rate for demand accesses
793system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for overall accesses
794system.cpu.dcache.overall_mshr_miss_rate::total 0.064143 # mshr miss rate for overall accesses
795system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67854.368932 # average ReadReq mshr miss latency
796system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67854.368932 # average ReadReq mshr miss latency
797system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59682.926829 # average WriteReq mshr miss latency
798system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59682.926829 # average WriteReq mshr miss latency
799system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency
800system.cpu.dcache.demand_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency
801system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency
802system.cpu.dcache.overall_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency
803system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
804system.cpu.icache.tags.replacements 43 # number of replacements
805system.cpu.icache.tags.tagsinuse 137.647063 # Cycle average of tags in use
806system.cpu.icache.tags.total_refs 3470 # Total number of references to valid blocks.
807system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks.
808system.cpu.icache.tags.avg_refs 11.722973 # Average number of references to valid blocks.
809system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
810system.cpu.icache.tags.occ_blocks::cpu.inst 137.647063 # Average occupied blocks per requestor
811system.cpu.icache.tags.occ_percent::cpu.inst 0.268842 # Average percentage of cache occupancy
812system.cpu.icache.tags.occ_percent::total 0.268842 # Average percentage of cache occupancy
813system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id
814system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
815system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
816system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id
817system.cpu.icache.tags.tag_accesses 7960 # Number of tag accesses
818system.cpu.icache.tags.data_accesses 7960 # Number of data accesses
819system.cpu.icache.ReadReq_hits::cpu.inst 3470 # number of ReadReq hits
820system.cpu.icache.ReadReq_hits::total 3470 # number of ReadReq hits
821system.cpu.icache.demand_hits::cpu.inst 3470 # number of demand (read+write) hits
822system.cpu.icache.demand_hits::total 3470 # number of demand (read+write) hits
823system.cpu.icache.overall_hits::cpu.inst 3470 # number of overall hits
824system.cpu.icache.overall_hits::total 3470 # number of overall hits
825system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses
826system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses
827system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses
828system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses
829system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses
830system.cpu.icache.overall_misses::total 362 # number of overall misses
831system.cpu.icache.ReadReq_miss_latency::cpu.inst 22661491 # number of ReadReq miss cycles
832system.cpu.icache.ReadReq_miss_latency::total 22661491 # number of ReadReq miss cycles
833system.cpu.icache.demand_miss_latency::cpu.inst 22661491 # number of demand (read+write) miss cycles
834system.cpu.icache.demand_miss_latency::total 22661491 # number of demand (read+write) miss cycles
835system.cpu.icache.overall_miss_latency::cpu.inst 22661491 # number of overall miss cycles
836system.cpu.icache.overall_miss_latency::total 22661491 # number of overall miss cycles
837system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses)
838system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses)
839system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses
840system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses
841system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses
842system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses
843system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094468 # miss rate for ReadReq accesses
844system.cpu.icache.ReadReq_miss_rate::total 0.094468 # miss rate for ReadReq accesses
845system.cpu.icache.demand_miss_rate::cpu.inst 0.094468 # miss rate for demand accesses
846system.cpu.icache.demand_miss_rate::total 0.094468 # miss rate for demand accesses
847system.cpu.icache.overall_miss_rate::cpu.inst 0.094468 # miss rate for overall accesses
848system.cpu.icache.overall_miss_rate::total 0.094468 # miss rate for overall accesses
849system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62600.803867 # average ReadReq miss latency
850system.cpu.icache.ReadReq_avg_miss_latency::total 62600.803867 # average ReadReq miss latency
851system.cpu.icache.demand_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency
852system.cpu.icache.demand_avg_miss_latency::total 62600.803867 # average overall miss latency
853system.cpu.icache.overall_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency
854system.cpu.icache.overall_avg_miss_latency::total 62600.803867 # average overall miss latency
855system.cpu.icache.blocked_cycles::no_mshrs 8953 # number of cycles access was blocked
856system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked
857system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked
858system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
859system.cpu.icache.avg_blocked_cycles::no_mshrs 93.260417 # average number of cycles each access was blocked
860system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked
861system.cpu.icache.fast_writes 0 # number of fast writes performed
862system.cpu.icache.cache_copies 0 # number of cache copies performed
863system.cpu.icache.writebacks::writebacks 43 # number of writebacks
864system.cpu.icache.writebacks::total 43 # number of writebacks
865system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits
866system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits
867system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits
868system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits
869system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits
870system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits
871system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses
872system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses
873system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses
874system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
875system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
876system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses
877system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19893491 # number of ReadReq MSHR miss cycles
878system.cpu.icache.ReadReq_mshr_miss_latency::total 19893491 # number of ReadReq MSHR miss cycles
879system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19893491 # number of demand (read+write) MSHR miss cycles
880system.cpu.icache.demand_mshr_miss_latency::total 19893491 # number of demand (read+write) MSHR miss cycles
881system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19893491 # number of overall MSHR miss cycles
882system.cpu.icache.overall_mshr_miss_latency::total 19893491 # number of overall MSHR miss cycles
883system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for ReadReq accesses
884system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077505 # mshr miss rate for ReadReq accesses
885system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for demand accesses
886system.cpu.icache.demand_mshr_miss_rate::total 0.077505 # mshr miss rate for demand accesses
887system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for overall accesses
888system.cpu.icache.overall_mshr_miss_rate::total 0.077505 # mshr miss rate for overall accesses
889system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66981.451178 # average ReadReq mshr miss latency
890system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66981.451178 # average ReadReq mshr miss latency
891system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency
892system.cpu.icache.demand_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency
893system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency
894system.cpu.icache.overall_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency
895system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
896system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued
897system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified
898system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
899system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
900system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
901system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
902system.cpu.l2cache.tags.replacements 0 # number of replacements
903system.cpu.l2cache.tags.tagsinuse 19.860815 # Cycle average of tags in use
904system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
905system.cpu.l2cache.tags.sampled_refs 48 # Sample count of references to valid blocks.
906system.cpu.l2cache.tags.avg_refs 0.208333 # Average number of references to valid blocks.
907system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
908system.cpu.l2cache.tags.occ_blocks::writebacks 10.581774 # Average occupied blocks per requestor
909system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.279041 # Average occupied blocks per requestor
910system.cpu.l2cache.tags.occ_percent::writebacks 0.000646 # Average percentage of cache occupancy
911system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000566 # Average percentage of cache occupancy
912system.cpu.l2cache.tags.occ_percent::total 0.001212 # Average percentage of cache occupancy
913system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id
914system.cpu.l2cache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id
915system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
916system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
917system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
918system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
919system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id
920system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id
921system.cpu.l2cache.tags.tag_accesses 7643 # Number of tag accesses
922system.cpu.l2cache.tags.data_accesses 7643 # Number of data accesses
923system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits
924system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits
925system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits
926system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits
927system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 7 # number of ReadCleanReq hits
928system.cpu.l2cache.ReadCleanReq_hits::total 7 # number of ReadCleanReq hits
929system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits
930system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits
931system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits
932system.cpu.l2cache.demand_hits::cpu.data 13 # number of demand (read+write) hits
933system.cpu.l2cache.demand_hits::total 20 # number of demand (read+write) hits
934system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits
935system.cpu.l2cache.overall_hits::cpu.data 13 # number of overall hits
936system.cpu.l2cache.overall_hits::total 20 # number of overall hits
937system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses
938system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses
939system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 290 # number of ReadCleanReq misses
940system.cpu.l2cache.ReadCleanReq_misses::total 290 # number of ReadCleanReq misses
941system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses
942system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses
943system.cpu.l2cache.demand_misses::cpu.inst 290 # number of demand (read+write) misses
944system.cpu.l2cache.demand_misses::cpu.data 131 # number of demand (read+write) misses
945system.cpu.l2cache.demand_misses::total 421 # number of demand (read+write) misses
946system.cpu.l2cache.overall_misses::cpu.inst 290 # number of overall misses
947system.cpu.l2cache.overall_misses::cpu.data 131 # number of overall misses
948system.cpu.l2cache.overall_misses::total 421 # number of overall misses
949system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2313000 # number of ReadExReq miss cycles
950system.cpu.l2cache.ReadExReq_miss_latency::total 2313000 # number of ReadExReq miss cycles
951system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19544000 # number of ReadCleanReq miss cycles
952system.cpu.l2cache.ReadCleanReq_miss_latency::total 19544000 # number of ReadCleanReq miss cycles
953system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6815000 # number of ReadSharedReq miss cycles
954system.cpu.l2cache.ReadSharedReq_miss_latency::total 6815000 # number of ReadSharedReq miss cycles
955system.cpu.l2cache.demand_miss_latency::cpu.inst 19544000 # number of demand (read+write) miss cycles
956system.cpu.l2cache.demand_miss_latency::cpu.data 9128000 # number of demand (read+write) miss cycles
957system.cpu.l2cache.demand_miss_latency::total 28672000 # number of demand (read+write) miss cycles
958system.cpu.l2cache.overall_miss_latency::cpu.inst 19544000 # number of overall miss cycles
959system.cpu.l2cache.overall_miss_latency::cpu.data 9128000 # number of overall miss cycles
960system.cpu.l2cache.overall_miss_latency::total 28672000 # number of overall miss cycles
961system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses)
962system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses)
963system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
964system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
965system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 297 # number of ReadCleanReq accesses(hits+misses)
966system.cpu.l2cache.ReadCleanReq_accesses::total 297 # number of ReadCleanReq accesses(hits+misses)
967system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses)
968system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses)
969system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses
970system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses
971system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
972system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses
973system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses
974system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
975system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses
976system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses
977system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976431 # miss rate for ReadCleanReq accesses
978system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976431 # miss rate for ReadCleanReq accesses
979system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.980583 # miss rate for ReadSharedReq accesses
980system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.980583 # miss rate for ReadSharedReq accesses
981system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976431 # miss rate for demand accesses
982system.cpu.l2cache.demand_miss_rate::cpu.data 0.909722 # miss rate for demand accesses
983system.cpu.l2cache.demand_miss_rate::total 0.954649 # miss rate for demand accesses
984system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976431 # miss rate for overall accesses
985system.cpu.l2cache.overall_miss_rate::cpu.data 0.909722 # miss rate for overall accesses
986system.cpu.l2cache.overall_miss_rate::total 0.954649 # miss rate for overall accesses
987system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77100 # average ReadExReq miss latency
988system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77100 # average ReadExReq miss latency
989system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67393.103448 # average ReadCleanReq miss latency
990system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67393.103448 # average ReadCleanReq miss latency
991system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67475.247525 # average ReadSharedReq miss latency
992system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67475.247525 # average ReadSharedReq miss latency
993system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency
994system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency
995system.cpu.l2cache.demand_avg_miss_latency::total 68104.513064 # average overall miss latency
996system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency
997system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency
998system.cpu.l2cache.overall_avg_miss_latency::total 68104.513064 # average overall miss latency
999system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1000system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1001system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1002system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1003system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1004system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1005system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1006system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1007system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
1008system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
1009system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits
1010system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
1011system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1012system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
1013system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
1014system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1015system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
1016system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
1017system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses
1018system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses
1019system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses
1020system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses
1021system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 289 # number of ReadCleanReq MSHR misses
1022system.cpu.l2cache.ReadCleanReq_mshr_misses::total 289 # number of ReadCleanReq MSHR misses
1023system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses
1024system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses
1025system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses
1026system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses
1027system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses
1028system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
1029system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses
1030system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses
1031system.cpu.l2cache.overall_mshr_misses::total 468 # number of overall MSHR misses
1032system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles
1033system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles
1034system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2133000 # number of ReadExReq MSHR miss cycles
1035system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2133000 # number of ReadExReq MSHR miss cycles
1036system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17760500 # number of ReadCleanReq MSHR miss cycles
1037system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17760500 # number of ReadCleanReq MSHR miss cycles
1038system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5946500 # number of ReadSharedReq MSHR miss cycles
1039system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5946500 # number of ReadSharedReq MSHR miss cycles
1040system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17760500 # number of demand (read+write) MSHR miss cycles
1041system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8079500 # number of demand (read+write) MSHR miss cycles
1042system.cpu.l2cache.demand_mshr_miss_latency::total 25840000 # number of demand (read+write) MSHR miss cycles
1043system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17760500 # number of overall MSHR miss cycles
1044system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8079500 # number of overall MSHR miss cycles
1045system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles
1046system.cpu.l2cache.overall_mshr_miss_latency::total 27465926 # number of overall MSHR miss cycles
1047system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1048system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1049system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses
1050system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses
1051system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for ReadCleanReq accesses
1052system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.973064 # mshr miss rate for ReadCleanReq accesses
1053system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses
1054system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses
1055system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for demand accesses
1056system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses
1057system.cpu.l2cache.demand_mshr_miss_rate::total 0.941043 # mshr miss rate for demand accesses
1058system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for overall accesses
1059system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses
1060system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1061system.cpu.l2cache.overall_mshr_miss_rate::total 1.061224 # mshr miss rate for overall accesses
1062system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average HardPFReq mshr miss latency
1063system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 30677.849057 # average HardPFReq mshr miss latency
1064system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71100 # average ReadExReq mshr miss latency
1065system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71100 # average ReadExReq mshr miss latency
1066system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61455.017301 # average ReadCleanReq mshr miss latency
1067system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61455.017301 # average ReadCleanReq mshr miss latency
1068system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61942.708333 # average ReadSharedReq mshr miss latency
1069system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61942.708333 # average ReadSharedReq mshr miss latency
1070system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency
1071system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency
1072system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62265.060241 # average overall mshr miss latency
1073system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency
1074system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency
1075system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average overall mshr miss latency
1076system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58687.876068 # average overall mshr miss latency
1077system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1078system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter.
1079system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1080system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1081system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # Total number of snoops made to the snoop filter.
1082system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1083system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1084system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution

1085system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution

1085system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution

1086system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution
1087system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution
1088system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
1089system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
1090system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution
1091system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution

1092system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes)
1093system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes)
1094system.cpu.toL2Bus.pkt_count::total 913 # Packet count per connected master and slave (bytes)
1095system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21056 # Cumulative packet size per connected master and slave (bytes)
1096system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes)
1097system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)

1092system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 636 # Packet count per connected master and slave (bytes)
1093system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes)
1094system.cpu.toL2Bus.pkt_count::total 924 # Packet count per connected master and slave (bytes)
1095system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21696 # Cumulative packet size per connected master and slave (bytes)
1096system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes)
1097system.cpu.toL2Bus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes)