Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt

Deleted Added

sdiff udiff text old ( 10036:80e84beef3bb ) new ( 10038:7eccd14e2610 )

full compact

stats.txt (10036:80e84beef3bb)	stats.txt (10038:7eccd14e2610)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16981000 # Number of ticks simulated 5final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16981000 # Number of ticks simulated 5final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 34743 # Simulator instruction rate (inst/s) 8host_op_rate 43351 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 128481440 # Simulator tick rate (ticks/s) 10host_mem_usage 246872 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host	7host_inst_rate 45620 # Simulator instruction rate (inst/s) 8host_op_rate 56920 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 168691831 # Simulator tick rate (ticks/s) 10host_mem_usage 267756 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host
12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 392 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 392 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 86 # Per bank write bursts 45system.physmem.perBankRdBursts::1 46 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 42 # Per bank write bursts 48system.physmem.perBankRdBursts::4 17 # Per bank write bursts 49system.physmem.perBankRdBursts::5 34 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 7 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 9 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 16923500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 392 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation 180system.physmem.totQLat 3153000 # Total ticks spent queuing 181system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM 182system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 183system.physmem.totBankLat 5403750 # Total ticks spent accessing banks 184system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst 185system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst 186system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 187system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst 188system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s 189system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 190system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s 191system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 192system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 193system.physmem.busUtil 11.54 # Data bus utilization in percentage 194system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads 195system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 196system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing 197system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 198system.physmem.readRowHits 332 # Number of row buffer hits during reads 199system.physmem.writeRowHits 0 # Number of row buffer hits during writes 200system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads 201system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 202system.physmem.avgGap 43172.19 # Average gap between requests 203system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined 204system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state 205system.membus.throughput 1473647017 # Throughput (bytes/s) 206system.membus.trans_dist::ReadReq 351 # Transaction distribution 207system.membus.trans_dist::ReadResp 350 # Transaction distribution 208system.membus.trans_dist::ReadExReq 41 # Transaction distribution 209system.membus.trans_dist::ReadExResp 41 # Transaction distribution 210system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) 211system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) 212system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) 213system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 214system.membus.data_through_bus 25024 # Total data (bytes) 215system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 216system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) 217system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 218system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) 219system.membus.respLayer1.utilization 21.5 # Layer utilization (%) 220system.cpu_clk_domain.clock 500 # Clock period in ticks 221system.cpu.branchPred.lookups 2481 # Number of BP lookups 222system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 223system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 224system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 225system.cpu.branchPred.BTBHits 697 # Number of BTB hits 226system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 227system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 228system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 229system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.	12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 392 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 392 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 86 # Per bank write bursts 45system.physmem.perBankRdBursts::1 46 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 42 # Per bank write bursts 48system.physmem.perBankRdBursts::4 17 # Per bank write bursts 49system.physmem.perBankRdBursts::5 34 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 7 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 9 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 16923500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 392 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation 180system.physmem.totQLat 3153000 # Total ticks spent queuing 181system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM 182system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 183system.physmem.totBankLat 5403750 # Total ticks spent accessing banks 184system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst 185system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst 186system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 187system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst 188system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s 189system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 190system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s 191system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 192system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 193system.physmem.busUtil 11.54 # Data bus utilization in percentage 194system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads 195system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 196system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing 197system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 198system.physmem.readRowHits 332 # Number of row buffer hits during reads 199system.physmem.writeRowHits 0 # Number of row buffer hits during writes 200system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads 201system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 202system.physmem.avgGap 43172.19 # Average gap between requests 203system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined 204system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state 205system.membus.throughput 1473647017 # Throughput (bytes/s) 206system.membus.trans_dist::ReadReq 351 # Transaction distribution 207system.membus.trans_dist::ReadResp 350 # Transaction distribution 208system.membus.trans_dist::ReadExReq 41 # Transaction distribution 209system.membus.trans_dist::ReadExResp 41 # Transaction distribution 210system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) 211system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) 212system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) 213system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 214system.membus.data_through_bus 25024 # Total data (bytes) 215system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 216system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) 217system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 218system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) 219system.membus.respLayer1.utilization 21.5 # Layer utilization (%) 220system.cpu_clk_domain.clock 500 # Clock period in ticks 221system.cpu.branchPred.lookups 2481 # Number of BP lookups 222system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 223system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 224system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 225system.cpu.branchPred.BTBHits 697 # Number of BTB hits 226system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 227system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 228system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 229system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
	230system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 231system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 232system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 233system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 234system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 235system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 236system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 237system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 238system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 239system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 240system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 241system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 242system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 243system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 244system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 245system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 246system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 247system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 248system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 249system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 250system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
230system.cpu.dtb.inst_hits 0 # ITB inst hits 231system.cpu.dtb.inst_misses 0 # ITB inst misses 232system.cpu.dtb.read_hits 0 # DTB read hits 233system.cpu.dtb.read_misses 0 # DTB read misses 234system.cpu.dtb.write_hits 0 # DTB write hits 235system.cpu.dtb.write_misses 0 # DTB write misses 236system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 237system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 238system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 239system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 240system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 241system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 242system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 243system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 244system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 245system.cpu.dtb.read_accesses 0 # DTB read accesses 246system.cpu.dtb.write_accesses 0 # DTB write accesses 247system.cpu.dtb.inst_accesses 0 # ITB inst accesses 248system.cpu.dtb.hits 0 # DTB hits 249system.cpu.dtb.misses 0 # DTB misses 250system.cpu.dtb.accesses 0 # DTB accesses	251system.cpu.dtb.inst_hits 0 # ITB inst hits 252system.cpu.dtb.inst_misses 0 # ITB inst misses 253system.cpu.dtb.read_hits 0 # DTB read hits 254system.cpu.dtb.read_misses 0 # DTB read misses 255system.cpu.dtb.write_hits 0 # DTB write hits 256system.cpu.dtb.write_misses 0 # DTB write misses 257system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 258system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 259system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 260system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 261system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 262system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 263system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 264system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 265system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 266system.cpu.dtb.read_accesses 0 # DTB read accesses 267system.cpu.dtb.write_accesses 0 # DTB write accesses 268system.cpu.dtb.inst_accesses 0 # ITB inst accesses 269system.cpu.dtb.hits 0 # DTB hits 270system.cpu.dtb.misses 0 # DTB misses 271system.cpu.dtb.accesses 0 # DTB accesses
	272system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 273system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 274system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 275system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 276system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 277system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 278system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 279system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 280system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 281system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 282system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 283system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 284system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 285system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 286system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 287system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 288system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 289system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 290system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 291system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 292system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
251system.cpu.itb.inst_hits 0 # ITB inst hits 252system.cpu.itb.inst_misses 0 # ITB inst misses 253system.cpu.itb.read_hits 0 # DTB read hits 254system.cpu.itb.read_misses 0 # DTB read misses 255system.cpu.itb.write_hits 0 # DTB write hits 256system.cpu.itb.write_misses 0 # DTB write misses 257system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 258system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 259system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 260system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 261system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 262system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 263system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 264system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 265system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 266system.cpu.itb.read_accesses 0 # DTB read accesses 267system.cpu.itb.write_accesses 0 # DTB write accesses 268system.cpu.itb.inst_accesses 0 # ITB inst accesses 269system.cpu.itb.hits 0 # DTB hits 270system.cpu.itb.misses 0 # DTB misses 271system.cpu.itb.accesses 0 # DTB accesses 272system.cpu.workload.num_syscalls 13 # Number of system calls 273system.cpu.numCycles 33963 # number of cpu cycles simulated 274system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 275system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 276system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss 277system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed 278system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered 279system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 280system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked 281system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 282system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked 283system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 284system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 285system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle 303system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle 304system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle 305system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked 306system.cpu.decode.RunCycles 2426 # Number of cycles decode is running 307system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 308system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 309system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 310system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 311system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode 312system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 313system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 314system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle 315system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking 316system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst 317system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 318system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 319system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 320system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 321system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 322system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 323system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed	293system.cpu.itb.inst_hits 0 # ITB inst hits 294system.cpu.itb.inst_misses 0 # ITB inst misses 295system.cpu.itb.read_hits 0 # DTB read hits 296system.cpu.itb.read_misses 0 # DTB read misses 297system.cpu.itb.write_hits 0 # DTB write hits 298system.cpu.itb.write_misses 0 # DTB write misses 299system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 300system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 301system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 302system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 303system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 304system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 305system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 306system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 308system.cpu.itb.read_accesses 0 # DTB read accesses 309system.cpu.itb.write_accesses 0 # DTB write accesses 310system.cpu.itb.inst_accesses 0 # ITB inst accesses 311system.cpu.itb.hits 0 # DTB hits 312system.cpu.itb.misses 0 # DTB misses 313system.cpu.itb.accesses 0 # DTB accesses 314system.cpu.workload.num_syscalls 13 # Number of system calls 315system.cpu.numCycles 33963 # number of cpu cycles simulated 316system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 317system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 318system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss 319system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed 320system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered 321system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 322system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked 323system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 324system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked 325system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 326system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 327system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle 345system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle 346system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle 347system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked 348system.cpu.decode.RunCycles 2426 # Number of cycles decode is running 349system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 350system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 351system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 352system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 353system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode 354system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 355system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 356system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle 357system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking 358system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst 359system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 360system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 361system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 362system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 363system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 364system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 365system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed
324system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made	366system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made
325system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 326system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 327system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 328system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 329system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 330system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 331system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer 332system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 333system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 334system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 335system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 336system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 337system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 338system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 339system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 340system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling	367system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 368system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 369system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 370system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 371system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 373system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer 374system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 376system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 377system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 378system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 379system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 380system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 381system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 382system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
341system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph	383system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
342system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 343system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle 360system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 361system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available 362system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available 363system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available 368system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available 369system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 390system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available 391system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available 392system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 393system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 394system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 395system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued 396system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued 397system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued 402system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued 403system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 424system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued 425system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued 426system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 427system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 428system.cpu.iq.FU_type_0::total 8921 # Type of FU issued 429system.cpu.iq.rate 0.262668 # Inst issue rate 430system.cpu.iq.fu_busy_cnt 224 # FU busy when requested 431system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) 432system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads 433system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes 434system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses 435system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 436system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 437system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 438system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses 439system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 440system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 441system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 442system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed 443system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 444system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 445system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed 446system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 447system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 448system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 449system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 450system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 451system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 452system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 453system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 454system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ 455system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch 456system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 457system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions 458system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 459system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 460system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 461system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 462system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 463system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 464system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 465system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions 466system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed 467system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute 468system.cpu.iew.exec_swp 0 # number of swp insts executed 469system.cpu.iew.exec_nop 0 # number of nop insts executed 470system.cpu.iew.exec_refs 3299 # number of memory reference insts executed 471system.cpu.iew.exec_branches 1437 # Number of branches executed 472system.cpu.iew.exec_stores 1160 # Number of stores executed 473system.cpu.iew.exec_rate 0.250950 # Inst execution rate 474system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit 475system.cpu.iew.wb_count 8068 # cumulative count of insts written-back 476system.cpu.iew.wb_producers 3883 # num instructions producing a value 477system.cpu.iew.wb_consumers 7788 # num instructions consuming a value 478system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 479system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle 480system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back 481system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 482system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit 483system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 484system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 485system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle 502system.cpu.commit.committedInsts 4591 # Number of instructions committed 503system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 504system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 505system.cpu.commit.refs 2138 # Number of memory references committed 506system.cpu.commit.loads 1200 # Number of loads committed 507system.cpu.commit.membars 12 # Number of memory barriers committed 508system.cpu.commit.branches 1007 # Number of branches committed 509system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 510system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 511system.cpu.commit.function_calls 82 # Number of function calls committed. 512system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 513system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 514system.cpu.rob.rob_reads 23234 # The number of ROB reads 515system.cpu.rob.rob_writes 23415 # The number of ROB writes 516system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself 517system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling 518system.cpu.committedInsts 4591 # Number of Instructions Simulated 519system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 520system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 521system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction 522system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads 523system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle 524system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads 525system.cpu.int_regfile_reads 39210 # number of integer regfile reads 526system.cpu.int_regfile_writes 7985 # number of integer regfile writes 527system.cpu.fp_regfile_reads 16 # number of floating regfile reads	384system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 385system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle 402system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 432system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available 433system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available 434system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 436system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 437system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued 438system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued 439system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued 445system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 466system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued 467system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued 468system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 469system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 470system.cpu.iq.FU_type_0::total 8921 # Type of FU issued 471system.cpu.iq.rate 0.262668 # Inst issue rate 472system.cpu.iq.fu_busy_cnt 224 # FU busy when requested 473system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) 474system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads 475system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes 476system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses 477system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 478system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 479system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 480system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses 481system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 482system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 483system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 484system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed 485system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 486system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 487system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed 488system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 489system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 490system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 491system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 492system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 493system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 494system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 495system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 496system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ 497system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch 498system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 499system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions 500system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 501system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 502system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 503system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 504system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 505system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 506system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 507system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions 508system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed 509system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute 510system.cpu.iew.exec_swp 0 # number of swp insts executed 511system.cpu.iew.exec_nop 0 # number of nop insts executed 512system.cpu.iew.exec_refs 3299 # number of memory reference insts executed 513system.cpu.iew.exec_branches 1437 # Number of branches executed 514system.cpu.iew.exec_stores 1160 # Number of stores executed 515system.cpu.iew.exec_rate 0.250950 # Inst execution rate 516system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit 517system.cpu.iew.wb_count 8068 # cumulative count of insts written-back 518system.cpu.iew.wb_producers 3883 # num instructions producing a value 519system.cpu.iew.wb_consumers 7788 # num instructions consuming a value 520system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 521system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle 522system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back 523system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 524system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit 525system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 526system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 527system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle 544system.cpu.commit.committedInsts 4591 # Number of instructions committed 545system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 546system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 547system.cpu.commit.refs 2138 # Number of memory references committed 548system.cpu.commit.loads 1200 # Number of loads committed 549system.cpu.commit.membars 12 # Number of memory barriers committed 550system.cpu.commit.branches 1007 # Number of branches committed 551system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 552system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 553system.cpu.commit.function_calls 82 # Number of function calls committed. 554system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 555system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 556system.cpu.rob.rob_reads 23234 # The number of ROB reads 557system.cpu.rob.rob_writes 23415 # The number of ROB writes 558system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself 559system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling 560system.cpu.committedInsts 4591 # Number of Instructions Simulated 561system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 562system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 563system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction 564system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads 565system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle 566system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads 567system.cpu.int_regfile_reads 39210 # number of integer regfile reads 568system.cpu.int_regfile_writes 7985 # number of integer regfile writes 569system.cpu.fp_regfile_reads 16 # number of floating regfile reads
528system.cpu.misc_regfile_reads 2977 # number of misc regfile reads	570system.cpu.misc_regfile_reads 3239 # number of misc regfile reads
529system.cpu.misc_regfile_writes 24 # number of misc regfile writes 530system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) 531system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 532system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 533system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 534system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 535system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 536system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 537system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) 538system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) 539system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 540system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) 541system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) 542system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 543system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 544system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 545system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) 546system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 547system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) 548system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 549system.cpu.icache.tags.replacements 4 # number of replacements 550system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use 551system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. 552system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 553system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. 554system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 555system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor 556system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy 557system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy 558system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 560system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id 561system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id 562system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses 563system.cpu.icache.tags.data_accesses 4184 # Number of data accesses 564system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits 565system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits 566system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits 567system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits 568system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits 569system.cpu.icache.overall_hits::total 1584 # number of overall hits 570system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses 571system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses 572system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 573system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses 574system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses 575system.cpu.icache.overall_misses::total 363 # number of overall misses 576system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles 577system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles 578system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles 579system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles 580system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles 581system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles 582system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 583system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 584system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 585system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 586system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 587system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 588system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses 589system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses 590system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses 591system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses 592system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses 593system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses 594system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency 595system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency 596system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency 597system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency 598system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency 599system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency 600system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked 601system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 602system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 603system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 604system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 605system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 606system.cpu.icache.fast_writes 0 # number of fast writes performed 607system.cpu.icache.cache_copies 0 # number of cache copies performed 608system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 609system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 610system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 611system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 612system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 613system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 614system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 615system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 616system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 617system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 618system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 619system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 620system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles 621system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles 622system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles 623system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles 624system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles 625system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles 626system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses 627system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses 628system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses 629system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses 630system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses 631system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses 632system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency 633system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency 634system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency 635system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency 636system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency 637system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency 638system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 639system.cpu.l2cache.tags.replacements 0 # number of replacements 640system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use 641system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 642system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 643system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. 644system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 645system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor 646system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor 647system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy 648system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy 649system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy 650system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 651system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 652system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 653system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id 654system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses 655system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses 656system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 657system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 658system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 659system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 660system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 661system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 662system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 663system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 664system.cpu.l2cache.overall_hits::total 40 # number of overall hits 665system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 666system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 667system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 668system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 669system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 670system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 671system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 672system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 673system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 674system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 675system.cpu.l2cache.overall_misses::total 397 # number of overall misses 676system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles 677system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles 678system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles 679system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles 680system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles 681system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles 682system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles 683system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles 684system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles 685system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles 686system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles 687system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) 688system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 689system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) 690system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 691system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 692system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses 693system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 694system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses 695system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses 696system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 697system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses 698system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses 699system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 700system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses 701system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 702system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 703system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses 704system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 705system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses 706system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses 707system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 708system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses 709system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency 710system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency 711system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency 712system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency 713system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency 714system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency 715system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency 716system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency 717system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency 718system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency 719system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency 720system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 721system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 722system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 723system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 724system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 725system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 726system.cpu.l2cache.fast_writes 0 # number of fast writes performed 727system.cpu.l2cache.cache_copies 0 # number of cache copies performed 728system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 729system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 730system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 731system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 732system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 733system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 734system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 735system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 736system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 737system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 738system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 739system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 740system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 741system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 742system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 743system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 744system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 745system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles 746system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles 747system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles 748system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles 749system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles 750system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles 751system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles 752system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles 753system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles 754system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles 755system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles 756system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses 757system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 758system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses 759system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 760system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 761system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses 762system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 763system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses 764system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses 765system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 766system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses 767system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency 768system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency 769system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency 770system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency 771system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency 772system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency 773system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency 774system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency 775system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency 776system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency 777system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency 778system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 779system.cpu.dcache.tags.replacements 0 # number of replacements 780system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use 781system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. 782system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 783system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. 784system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 785system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor 786system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy 787system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy 788system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 789system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 790system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 791system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 792system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses 793system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses 794system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 795system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 796system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 797system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 798system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 799system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 800system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 801system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 802system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 803system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 804system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 805system.cpu.dcache.overall_hits::total 2373 # number of overall hits 806system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses 807system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses 808system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 809system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 810system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 811system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 812system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 813system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 814system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 815system.cpu.dcache.overall_misses::total 496 # number of overall misses 816system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles 817system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles 818system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles 819system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles 820system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 821system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 822system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles 823system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles 824system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles 825system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles 826system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 827system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 828system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 829system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 830system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 831system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 832system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 833system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 834system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 835system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 836system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 837system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 838system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses 839system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses 840system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 841system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 842system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 843system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 844system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 845system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses 846system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 847system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses 848system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency 849system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency 850system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency 851system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency 852system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 853system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 854system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency 855system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency 856system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency 857system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency 858system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 859system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 860system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 861system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 862system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 863system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 864system.cpu.dcache.fast_writes 0 # number of fast writes performed 865system.cpu.dcache.cache_copies 0 # number of cache copies performed 866system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 867system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 868system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 869system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 870system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 871system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 872system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits 873system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits 874system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits 875system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits 876system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 877system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 878system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 879system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 880system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 881system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 882system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 883system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 884system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles 885system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles 886system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles 887system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles 888system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles 889system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles 890system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles 891system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles 892system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 893system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 894system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 895system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 896system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 897system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 898system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 899system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 900system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency 901system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency 902system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency 903system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency 904system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency 905system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency 906system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency 907system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency 908system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 909 910---------- End Simulation Statistics ----------	571system.cpu.misc_regfile_writes 24 # number of misc regfile writes 572system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) 573system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 579system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) 580system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) 581system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 582system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) 584system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 585system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 586system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 587system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) 588system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 589system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) 590system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 591system.cpu.icache.tags.replacements 4 # number of replacements 592system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use 593system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. 594system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 595system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. 596system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 597system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor 598system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy 599system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy 600system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id 601system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 602system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id 603system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id 604system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses 605system.cpu.icache.tags.data_accesses 4184 # Number of data accesses 606system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits 607system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits 608system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits 609system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits 610system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits 611system.cpu.icache.overall_hits::total 1584 # number of overall hits 612system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses 613system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses 614system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 615system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses 616system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses 617system.cpu.icache.overall_misses::total 363 # number of overall misses 618system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles 619system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles 620system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles 621system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles 622system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles 623system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles 624system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 625system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 626system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 627system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 628system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 629system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 630system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses 631system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses 632system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses 633system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses 634system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses 635system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses 636system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency 637system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency 638system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency 639system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency 640system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency 641system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency 642system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked 643system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 645system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 646system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 647system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.icache.fast_writes 0 # number of fast writes performed 649system.cpu.icache.cache_copies 0 # number of cache copies performed 650system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 651system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 652system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 653system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 654system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 655system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 656system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 657system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 658system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 659system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 660system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 661system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 662system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles 663system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles 664system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles 665system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles 666system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles 667system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles 668system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses 669system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses 670system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses 671system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses 672system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses 673system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency 675system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency 677system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency 679system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency 680system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 681system.cpu.l2cache.tags.replacements 0 # number of replacements 682system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use 683system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 684system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 685system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. 686system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 687system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor 688system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor 689system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy 690system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy 691system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy 692system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 693system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 695system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id 696system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses 697system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses 698system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 699system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 700system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 701system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 702system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 703system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 704system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 705system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 706system.cpu.l2cache.overall_hits::total 40 # number of overall hits 707system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 708system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 709system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 710system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 711system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 712system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 713system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 714system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 715system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 716system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 717system.cpu.l2cache.overall_misses::total 397 # number of overall misses 718system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles 719system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles 720system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles 721system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles 722system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles 723system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles 724system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles 725system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles 726system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles 727system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles 728system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles 729system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) 730system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 731system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) 732system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 733system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 734system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses 735system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 736system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses 737system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses 738system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 739system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses 740system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses 741system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 742system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses 743system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 744system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 745system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses 746system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 747system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses 748system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses 749system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 750system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses 751system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency 752system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency 753system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency 754system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency 755system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency 756system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency 757system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency 758system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency 759system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency 760system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency 761system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency 762system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 763system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 765system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 767system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu.l2cache.fast_writes 0 # number of fast writes performed 769system.cpu.l2cache.cache_copies 0 # number of cache copies performed 770system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 771system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 772system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 773system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 774system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 775system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 776system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 777system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 778system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 779system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 780system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 781system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 782system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 783system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 784system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 785system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 786system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 787system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles 788system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles 789system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles 790system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles 791system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles 792system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles 793system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles 794system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles 795system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles 796system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles 797system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles 798system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses 799system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 800system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses 801system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 802system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 803system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses 804system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 805system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses 806system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses 807system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 808system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses 809system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency 810system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency 811system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency 812system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency 813system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency 814system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency 815system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency 817system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency 818system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency 820system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 821system.cpu.dcache.tags.replacements 0 # number of replacements 822system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use 823system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. 824system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 825system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. 826system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 827system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor 828system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy 829system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy 830system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 831system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 832system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 833system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 834system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses 835system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses 836system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 837system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 838system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 839system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 840system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 841system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 842system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 843system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 844system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 845system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 846system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 847system.cpu.dcache.overall_hits::total 2373 # number of overall hits 848system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses 849system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses 850system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 851system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 852system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 853system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 854system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 855system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 856system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 857system.cpu.dcache.overall_misses::total 496 # number of overall misses 858system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles 859system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles 860system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles 861system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles 862system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 863system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 864system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles 865system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles 866system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles 867system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles 868system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 869system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 870system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 871system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 872system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 873system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 874system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 875system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 876system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 877system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 878system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 879system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 880system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses 881system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses 882system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 883system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 884system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 885system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 886system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 887system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses 888system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 889system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses 890system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency 891system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency 892system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency 893system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency 894system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 895system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 896system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency 897system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency 898system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency 899system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency 900system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 901system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 902system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 903system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 904system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 905system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 906system.cpu.dcache.fast_writes 0 # number of fast writes performed 907system.cpu.dcache.cache_copies 0 # number of cache copies performed 908system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 909system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 910system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 911system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 912system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 913system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 914system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits 915system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits 916system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits 917system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits 918system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 919system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 920system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 921system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 922system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 923system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 924system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 925system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 926system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles 927system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles 928system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles 929system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles 930system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles 931system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles 932system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles 933system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles 934system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 935system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 936system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 937system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 938system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 939system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 940system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 941system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 942system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency 943system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency 944system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency 945system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency 946system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency 947system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency 948system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency 949system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency 950system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 951 952---------- End Simulation Statistics ----------