1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000014 # Number of seconds simulated
4sim_ticks 13709000 # Number of ticks simulated
5final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 36221 # Simulator instruction rate (inst/s)
8host_op_rate 45190 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 108117571 # Simulator tick rate (ticks/s)
10host_mem_usage 238932 # Number of bytes of host memory used
11host_seconds 0.13 # Real time elapsed on the host
12sim_insts 4591 # Number of instructions simulated
13sim_ops 5729 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
--- 53 unchanged lines hidden (view full) ---
73system.physmem.totGap 13651500 # Total gap between requests
74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 394 # Categorize read packet sizes
81system.physmem.writePktSize::0 0 # Categorize write packet sizes
82system.physmem.writePktSize::1 0 # Categorize write packet sizes
83system.physmem.writePktSize::2 0 # Categorize write packet sizes
84system.physmem.writePktSize::3 0 # Categorize write packet sizes
85system.physmem.writePktSize::4 0 # Categorize write packet sizes
86system.physmem.writePktSize::5 0 # Categorize write packet sizes
87system.physmem.writePktSize::6 0 # Categorize write packet sizes
88system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
89system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
--- 16 unchanged lines hidden (view full) ---
112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
--- 16 unchanged lines hidden (view full) ---
144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152system.physmem.totQLat 2507750 # Total cycles spent in queuing delays
153system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests
154system.physmem.totBusLat 1970000 # Total cycles spent in databus access
155system.physmem.totBankLat 7273750 # Total cycles spent in bank access
156system.physmem.avgQLat 6364.85 # Average queueing delay per request
157system.physmem.avgBankLat 18461.29 # Average bank access latency per request
158system.physmem.avgBusLat 5000.00 # Average bus latency per request
159system.physmem.avgMemAccLat 29826.14 # Average memory access latency
160system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
162system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
165system.physmem.busUtil 14.37 # Data bus utilization in percentage
166system.physmem.avgRdQLen 0.86 # Average read queue length over time
167system.physmem.avgWrQLen 0.00 # Average write queue length over time
--- 391 unchanged lines hidden (view full) ---
559system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency
560system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency
561system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency
562system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
563system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency
564system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
565system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
566system.cpu.l2cache.replacements 0 # number of replacements
567system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use
568system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
569system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
570system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks.
571system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
572system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor
573system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor
574system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy
575system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy
576system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy
577system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits
578system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
579system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
580system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits
581system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
--- 76 unchanged lines hidden (view full) ---
658system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
659system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
660system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
661system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
662system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
663system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
664system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
665system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
666system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles
667system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles
668system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles
669system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles
670system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles
671system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles
672system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles
673system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles
674system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles
675system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles
676system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles
677system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses
678system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
679system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses
680system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
681system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
682system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for demand accesses
683system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
684system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 # mshr miss rate for demand accesses
685system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses
686system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
687system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses
688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency
689system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency
690system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency
691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency
692system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency
693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency
694system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
695system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency
696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency
697system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
698system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency
699system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
700system.cpu.dcache.replacements 0 # number of replacements
701system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use
702system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks.
703system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
704system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks.
705system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
706system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor
--- 119 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000014 # Number of seconds simulated
4sim_ticks 13709000 # Number of ticks simulated
5final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 36221 # Simulator instruction rate (inst/s)
8host_op_rate 45190 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 108117571 # Simulator tick rate (ticks/s)
10host_mem_usage 238932 # Number of bytes of host memory used
11host_seconds 0.13 # Real time elapsed on the host
12sim_insts 4591 # Number of instructions simulated
13sim_ops 5729 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
--- 53 unchanged lines hidden (view full) ---
73system.physmem.totGap 13651500 # Total gap between requests
74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 394 # Categorize read packet sizes
81system.physmem.writePktSize::0 0 # Categorize write packet sizes
82system.physmem.writePktSize::1 0 # Categorize write packet sizes
83system.physmem.writePktSize::2 0 # Categorize write packet sizes
84system.physmem.writePktSize::3 0 # Categorize write packet sizes
85system.physmem.writePktSize::4 0 # Categorize write packet sizes
86system.physmem.writePktSize::5 0 # Categorize write packet sizes
87system.physmem.writePktSize::6 0 # Categorize write packet sizes
88system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
89system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
--- 16 unchanged lines hidden (view full) ---
112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
--- 16 unchanged lines hidden (view full) ---
144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152system.physmem.totQLat 2507750 # Total cycles spent in queuing delays
153system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests
154system.physmem.totBusLat 1970000 # Total cycles spent in databus access
155system.physmem.totBankLat 7273750 # Total cycles spent in bank access
156system.physmem.avgQLat 6364.85 # Average queueing delay per request
157system.physmem.avgBankLat 18461.29 # Average bank access latency per request
158system.physmem.avgBusLat 5000.00 # Average bus latency per request
159system.physmem.avgMemAccLat 29826.14 # Average memory access latency
160system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
162system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
165system.physmem.busUtil 14.37 # Data bus utilization in percentage
166system.physmem.avgRdQLen 0.86 # Average read queue length over time
167system.physmem.avgWrQLen 0.00 # Average write queue length over time
--- 391 unchanged lines hidden (view full) ---
559system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency
560system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency
561system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency
562system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
563system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency
564system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
565system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
566system.cpu.l2cache.replacements 0 # number of replacements
567system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use
568system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
569system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
570system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks.
571system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
572system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor
573system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor
574system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy
575system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy
576system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy
577system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits
578system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
579system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
580system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits
581system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
--- 76 unchanged lines hidden (view full) ---
658system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
659system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
660system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
661system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
662system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
663system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
664system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
665system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
666system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles
667system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles
668system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles
669system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles
670system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles
671system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles
672system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles
673system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles
674system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles
675system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles
676system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles
677system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses
678system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
679system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses
680system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
681system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
682system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for demand accesses
683system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
684system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 # mshr miss rate for demand accesses
685system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses
686system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
687system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses
688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency
689system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency
690system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency
691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency
692system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency
693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency
694system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
695system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency
696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency
697system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
698system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency
699system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
700system.cpu.dcache.replacements 0 # number of replacements
701system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use
702system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks.
703system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
704system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks.
705system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
706system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor
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