| config.ini (9096:8971a998190a) | config.ini (9265:8fe936e937bd) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a |
| 13clock=1 |
|
| 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= --- 69 unchanged lines hidden (view full) --- 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 | 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= --- 69 unchanged lines hidden (view full) --- 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 |
| 98phase=0 | |
| 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 --- 17 unchanged lines hidden (view full) --- 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 | 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 --- 17 unchanged lines hidden (view full) --- 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 |
| 132clock=1 |
|
| 132forward_snoops=true 133hash_delay=1 | 133forward_snoops=true 134hash_delay=1 |
| 135hit_latency=1000 |
|
| 134is_top_level=true | 136is_top_level=true |
| 135latency=1000 | |
| 136max_miss_count=0 137mshrs=10 138prefetch_on_access=false 139prefetcher=Null 140prioritizeRequests=false 141repl=Null | 137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null |
| 143response_latency=1000 |
|
| 142size=262144 143subblock_size=0 144system=system 145tgts_per_mshr=20 146trace_addr=0 147two_queue=false 148write_buffers=8 149cpu_side=system.cpu.dcache_port 150mem_side=system.cpu.toL2Bus.slave[1] 151 152[system.cpu.dtb] 153type=ArmTLB 154children=walker 155size=64 156walker=system.cpu.dtb.walker 157 158[system.cpu.dtb.walker] 159type=ArmTableWalker | 144size=262144 145subblock_size=0 146system=system 147tgts_per_mshr=20 148trace_addr=0 149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port 152mem_side=system.cpu.toL2Bus.slave[1] 153 154[system.cpu.dtb] 155type=ArmTLB 156children=walker 157size=64 158walker=system.cpu.dtb.walker 159 160[system.cpu.dtb.walker] 161type=ArmTableWalker |
| 160max_backoff=100000 161min_backoff=0 | 162clock=1 163num_squash_per_cycle=2 |
| 162sys=system 163port=system.cpu.toL2Bus.slave[3] 164 165[system.cpu.fuPool] 166type=FUPool 167children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 168FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 169 --- 255 unchanged lines hidden (view full) --- 425opClass=IprAccess 426opLat=3 427 428[system.cpu.icache] 429type=BaseCache 430addr_ranges=0:18446744073709551615 431assoc=2 432block_size=64 | 164sys=system 165port=system.cpu.toL2Bus.slave[3] 166 167[system.cpu.fuPool] 168type=FUPool 169children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 170FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 171 --- 255 unchanged lines hidden (view full) --- 427opClass=IprAccess 428opLat=3 429 430[system.cpu.icache] 431type=BaseCache 432addr_ranges=0:18446744073709551615 433assoc=2 434block_size=64 |
| 435clock=1 |
|
| 433forward_snoops=true 434hash_delay=1 | 436forward_snoops=true 437hash_delay=1 |
| 438hit_latency=1000 |
|
| 435is_top_level=true | 439is_top_level=true |
| 436latency=1000 | |
| 437max_miss_count=0 438mshrs=10 439prefetch_on_access=false 440prefetcher=Null 441prioritizeRequests=false 442repl=Null | 440max_miss_count=0 441mshrs=10 442prefetch_on_access=false 443prefetcher=Null 444prioritizeRequests=false 445repl=Null |
| 446response_latency=1000 |
|
| 443size=131072 444subblock_size=0 445system=system 446tgts_per_mshr=20 447trace_addr=0 448two_queue=false 449write_buffers=8 450cpu_side=system.cpu.icache_port --- 5 unchanged lines hidden (view full) --- 456[system.cpu.itb] 457type=ArmTLB 458children=walker 459size=64 460walker=system.cpu.itb.walker 461 462[system.cpu.itb.walker] 463type=ArmTableWalker | 447size=131072 448subblock_size=0 449system=system 450tgts_per_mshr=20 451trace_addr=0 452two_queue=false 453write_buffers=8 454cpu_side=system.cpu.icache_port --- 5 unchanged lines hidden (view full) --- 460[system.cpu.itb] 461type=ArmTLB 462children=walker 463size=64 464walker=system.cpu.itb.walker 465 466[system.cpu.itb.walker] 467type=ArmTableWalker |
| 464max_backoff=100000 465min_backoff=0 | 468clock=1 469num_squash_per_cycle=2 |
| 466sys=system 467port=system.cpu.toL2Bus.slave[2] 468 469[system.cpu.l2cache] 470type=BaseCache 471addr_ranges=0:18446744073709551615 472assoc=2 473block_size=64 | 470sys=system 471port=system.cpu.toL2Bus.slave[2] 472 473[system.cpu.l2cache] 474type=BaseCache 475addr_ranges=0:18446744073709551615 476assoc=2 477block_size=64 |
| 478clock=1 |
|
| 474forward_snoops=true 475hash_delay=1 | 479forward_snoops=true 480hash_delay=1 |
| 481hit_latency=1000 |
|
| 476is_top_level=false | 482is_top_level=false |
| 477latency=1000 | |
| 478max_miss_count=0 479mshrs=10 480prefetch_on_access=false 481prefetcher=Null 482prioritizeRequests=false 483repl=Null | 483max_miss_count=0 484mshrs=10 485prefetch_on_access=false 486prefetcher=Null 487prioritizeRequests=false 488repl=Null |
| 489response_latency=1000 |
|
| 484size=2097152 485subblock_size=0 486system=system 487tgts_per_mshr=5 488trace_addr=0 489two_queue=false 490write_buffers=8 491cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 507[system.cpu.workload] 508type=LiveProcess 509cmd=hello 510cwd= 511egid=100 512env= 513errout=cerr 514euid=100 | 490size=2097152 491subblock_size=0 492system=system 493tgts_per_mshr=5 494trace_addr=0 495two_queue=false 496write_buffers=8 497cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 513[system.cpu.workload] 514type=LiveProcess 515cmd=hello 516cwd= 517egid=100 518env= 519errout=cerr 520euid=100 |
| 515executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello | 521executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello |
| 516gid=100 517input=cin 518max_stack_size=67108864 519output=cout 520pid=100 521ppid=99 522simpoint=0 523system=system 524uid=100 525 526[system.membus] 527type=CoherentBus 528block_size=64 529clock=1000 530header_cycles=1 531use_default_range=false 532width=8 | 522gid=100 523input=cin 524max_stack_size=67108864 525output=cout 526pid=100 527ppid=99 528simpoint=0 529system=system 530uid=100 531 532[system.membus] 533type=CoherentBus 534block_size=64 535clock=1000 536header_cycles=1 537use_default_range=false 538width=8 |
| 533master=system.physmem.port[0] | 539master=system.physmem.port |
| 534slave=system.system_port system.cpu.l2cache.mem_side 535 536[system.physmem] 537type=SimpleMemory | 540slave=system.system_port system.cpu.l2cache.mem_side 541 542[system.physmem] 543type=SimpleMemory |
| 544bandwidth=73.000000 545clock=1 |
|
| 538conf_table_reported=false | 546conf_table_reported=false |
| 539file= | |
| 540in_addr_map=true 541latency=30000 542latency_var=0 543null=false 544range=0:134217727 545zero=false 546port=system.membus.master[0] 547 | 547in_addr_map=true 548latency=30000 549latency_var=0 550null=false 551range=0:134217727 552zero=false 553port=system.membus.master[0] 554 |