config.ini (11312:3d7a85d71bd1) config.ini (11384:e3cbd2823210)
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 145 unchanged lines hidden (view full) ---

154type=Cache
155children=tags
156addr_ranges=0:18446744073709551615
157assoc=2
158clk_domain=system.cpu_clk_domain
159clusivity=mostly_incl
160demand_mshr_reserve=1
161eventq_index=0
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 145 unchanged lines hidden (view full) ---

154type=Cache
155children=tags
156addr_ranges=0:18446744073709551615
157assoc=2
158clk_domain=system.cpu_clk_domain
159clusivity=mostly_incl
160demand_mshr_reserve=1
161eventq_index=0
162forward_snoops=true
163hit_latency=2
164is_read_only=false
165max_miss_count=0
166mshrs=6
167prefetch_on_access=false
168prefetcher=Null
169response_latency=2
170sequential_access=false

--- 326 unchanged lines hidden (view full) ---

497type=Cache
498children=tags
499addr_ranges=0:18446744073709551615
500assoc=2
501clk_domain=system.cpu_clk_domain
502clusivity=mostly_incl
503demand_mshr_reserve=1
504eventq_index=0
162hit_latency=2
163is_read_only=false
164max_miss_count=0
165mshrs=6
166prefetch_on_access=false
167prefetcher=Null
168response_latency=2
169sequential_access=false

--- 326 unchanged lines hidden (view full) ---

496type=Cache
497children=tags
498addr_ranges=0:18446744073709551615
499assoc=2
500clk_domain=system.cpu_clk_domain
501clusivity=mostly_incl
502demand_mshr_reserve=1
503eventq_index=0
505forward_snoops=false
506hit_latency=1
507is_read_only=true
508max_miss_count=0
509mshrs=2
510prefetch_on_access=false
511prefetcher=Null
512response_latency=1
513sequential_access=false

--- 96 unchanged lines hidden (view full) ---

610type=Cache
611children=prefetcher tags
612addr_ranges=0:18446744073709551615
613assoc=16
614clk_domain=system.cpu_clk_domain
615clusivity=mostly_excl
616demand_mshr_reserve=1
617eventq_index=0
504hit_latency=1
505is_read_only=true
506max_miss_count=0
507mshrs=2
508prefetch_on_access=false
509prefetcher=Null
510response_latency=1
511sequential_access=false

--- 96 unchanged lines hidden (view full) ---

608type=Cache
609children=prefetcher tags
610addr_ranges=0:18446744073709551615
611assoc=16
612clk_domain=system.cpu_clk_domain
613clusivity=mostly_excl
614demand_mshr_reserve=1
615eventq_index=0
618forward_snoops=true
619hit_latency=12
620is_read_only=false
621max_miss_count=0
622mshrs=16
623prefetch_on_access=true
624prefetcher=system.cpu.l2cache.prefetcher
625response_latency=12
626sequential_access=false

--- 43 unchanged lines hidden (view full) ---

670
671[system.cpu.toL2Bus]
672type=CoherentXBar
673children=snoop_filter
674clk_domain=system.cpu_clk_domain
675eventq_index=0
676forward_latency=0
677frontend_latency=1
616hit_latency=12
617is_read_only=false
618max_miss_count=0
619mshrs=16
620prefetch_on_access=true
621prefetcher=system.cpu.l2cache.prefetcher
622response_latency=12
623sequential_access=false

--- 43 unchanged lines hidden (view full) ---

667
668[system.cpu.toL2Bus]
669type=CoherentXBar
670children=snoop_filter
671clk_domain=system.cpu_clk_domain
672eventq_index=0
673forward_latency=0
674frontend_latency=1
675point_of_coherency=false
678response_latency=1
679snoop_filter=system.cpu.toL2Bus.snoop_filter
680snoop_response_latency=1
681system=system
682use_default_range=false
683width=32
684master=system.cpu.l2cache.cpu_side
685slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port

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700cmd=hello
701cwd=
702drivers=
703egid=100
704env=
705errout=cerr
706euid=100
707eventq_index=0
676response_latency=1
677snoop_filter=system.cpu.toL2Bus.snoop_filter
678snoop_response_latency=1
679system=system
680use_default_range=false
681width=32
682master=system.cpu.l2cache.cpu_side
683slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port

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698cmd=hello
699cwd=
700drivers=
701egid=100
702env=
703errout=cerr
704euid=100
705eventq_index=0
708executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
706executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
709gid=100
710input=cin
711kvmInSE=false
712max_stack_size=67108864
713output=cout
714pid=100
715ppid=99
716simpoint=0

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735transition_latency=100000000
736
737[system.membus]
738type=CoherentXBar
739clk_domain=system.clk_domain
740eventq_index=0
741forward_latency=4
742frontend_latency=3
707gid=100
708input=cin
709kvmInSE=false
710max_stack_size=67108864
711output=cout
712pid=100
713ppid=99
714simpoint=0

--- 18 unchanged lines hidden (view full) ---

733transition_latency=100000000
734
735[system.membus]
736type=CoherentXBar
737clk_domain=system.clk_domain
738eventq_index=0
739forward_latency=4
740frontend_latency=3
741point_of_coherency=true
743response_latency=2
744snoop_filter=Null
745snoop_response_latency=4
746system=system
747use_default_range=false
748width=16
749master=system.physmem.port
750slave=system.system_port system.cpu.l2cache.mem_side

--- 83 unchanged lines hidden ---
742response_latency=2
743snoop_filter=Null
744snoop_response_latency=4
745system=system
746use_default_range=false
747width=16
748master=system.physmem.port
749slave=system.system_port system.cpu.l2cache.mem_side

--- 83 unchanged lines hidden ---