| config.ini (10451:3a87241adfb8) | config.ini (10736:4433fb00fa7d) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem |
| 26mmap_using_noreserve=false |
|
| 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 --- 118 unchanged lines hidden (view full) --- 152predType=bi-mode 153 154[system.cpu.dcache] 155type=BaseCache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=2 159clk_domain=system.cpu_clk_domain | 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 --- 118 unchanged lines hidden (view full) --- 153predType=bi-mode 154 155[system.cpu.dcache] 156type=BaseCache 157children=tags 158addr_ranges=0:18446744073709551615 159assoc=2 160clk_domain=system.cpu_clk_domain |
| 161demand_mshr_reserve=1 |
|
| 160eventq_index=0 161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=6 166prefetch_on_access=false 167prefetcher=Null --- 18 unchanged lines hidden (view full) --- 186sequential_access=false 187size=32768 188 189[system.cpu.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb | 162eventq_index=0 163forward_snoops=true 164hit_latency=2 165is_top_level=true 166max_miss_count=0 167mshrs=6 168prefetch_on_access=false 169prefetcher=Null --- 18 unchanged lines hidden (view full) --- 188sequential_access=false 189size=32768 190 191[system.cpu.dstage2_mmu] 192type=ArmStage2MMU 193children=stage2_tlb 194eventq_index=0 195stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| 196sys=system |
|
| 194tlb=system.cpu.dtb 195 196[system.cpu.dstage2_mmu.stage2_tlb] 197type=ArmTLB 198children=walker 199eventq_index=0 200is_stage2=true 201size=32 202walker=system.cpu.dstage2_mmu.stage2_tlb.walker 203 204[system.cpu.dstage2_mmu.stage2_tlb.walker] 205type=ArmTableWalker 206clk_domain=system.cpu_clk_domain 207eventq_index=0 208is_stage2=true 209num_squash_per_cycle=2 210sys=system | 197tlb=system.cpu.dtb 198 199[system.cpu.dstage2_mmu.stage2_tlb] 200type=ArmTLB 201children=walker 202eventq_index=0 203is_stage2=true 204size=32 205walker=system.cpu.dstage2_mmu.stage2_tlb.walker 206 207[system.cpu.dstage2_mmu.stage2_tlb.walker] 208type=ArmTableWalker 209clk_domain=system.cpu_clk_domain 210eventq_index=0 211is_stage2=true 212num_squash_per_cycle=2 213sys=system |
| 211port=system.cpu.toL2Bus.slave[5] | |
| 212 213[system.cpu.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.dtb.walker --- 273 unchanged lines hidden (view full) --- 493opLat=4 494 495[system.cpu.icache] 496type=BaseCache 497children=tags 498addr_ranges=0:18446744073709551615 499assoc=2 500clk_domain=system.cpu_clk_domain | 214 215[system.cpu.dtb] 216type=ArmTLB 217children=walker 218eventq_index=0 219is_stage2=false 220size=64 221walker=system.cpu.dtb.walker --- 273 unchanged lines hidden (view full) --- 495opLat=4 496 497[system.cpu.icache] 498type=BaseCache 499children=tags 500addr_ranges=0:18446744073709551615 501assoc=2 502clk_domain=system.cpu_clk_domain |
| 503demand_mshr_reserve=1 |
|
| 501eventq_index=0 502forward_snoops=true 503hit_latency=1 504is_top_level=true 505max_miss_count=0 506mshrs=2 507prefetch_on_access=false 508prefetcher=Null --- 44 unchanged lines hidden (view full) --- 553id_isar5=0 554id_mmfr0=270536963 555id_mmfr1=0 556id_mmfr2=19070976 557id_mmfr3=34611729 558id_pfr0=49 559id_pfr1=4113 560midr=1091551472 | 504eventq_index=0 505forward_snoops=true 506hit_latency=1 507is_top_level=true 508max_miss_count=0 509mshrs=2 510prefetch_on_access=false 511prefetcher=Null --- 44 unchanged lines hidden (view full) --- 556id_isar5=0 557id_mmfr0=270536963 558id_mmfr1=0 559id_mmfr2=19070976 560id_mmfr3=34611729 561id_pfr0=49 562id_pfr1=4113 563midr=1091551472 |
| 564pmu=Null |
|
| 561system=system 562 563[system.cpu.istage2_mmu] 564type=ArmStage2MMU 565children=stage2_tlb 566eventq_index=0 567stage2_tlb=system.cpu.istage2_mmu.stage2_tlb | 565system=system 566 567[system.cpu.istage2_mmu] 568type=ArmStage2MMU 569children=stage2_tlb 570eventq_index=0 571stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| 572sys=system |
|
| 568tlb=system.cpu.itb 569 570[system.cpu.istage2_mmu.stage2_tlb] 571type=ArmTLB 572children=walker 573eventq_index=0 574is_stage2=true 575size=32 576walker=system.cpu.istage2_mmu.stage2_tlb.walker 577 578[system.cpu.istage2_mmu.stage2_tlb.walker] 579type=ArmTableWalker 580clk_domain=system.cpu_clk_domain 581eventq_index=0 582is_stage2=true 583num_squash_per_cycle=2 584sys=system | 573tlb=system.cpu.itb 574 575[system.cpu.istage2_mmu.stage2_tlb] 576type=ArmTLB 577children=walker 578eventq_index=0 579is_stage2=true 580size=32 581walker=system.cpu.istage2_mmu.stage2_tlb.walker 582 583[system.cpu.istage2_mmu.stage2_tlb.walker] 584type=ArmTableWalker 585clk_domain=system.cpu_clk_domain 586eventq_index=0 587is_stage2=true 588num_squash_per_cycle=2 589sys=system |
| 585port=system.cpu.toL2Bus.slave[4] | |
| 586 587[system.cpu.itb] 588type=ArmTLB 589children=walker 590eventq_index=0 591is_stage2=false 592size=64 593walker=system.cpu.itb.walker --- 8 unchanged lines hidden (view full) --- 602port=system.cpu.toL2Bus.slave[2] 603 604[system.cpu.l2cache] 605type=BaseCache 606children=prefetcher tags 607addr_ranges=0:18446744073709551615 608assoc=16 609clk_domain=system.cpu_clk_domain | 590 591[system.cpu.itb] 592type=ArmTLB 593children=walker 594eventq_index=0 595is_stage2=false 596size=64 597walker=system.cpu.itb.walker --- 8 unchanged lines hidden (view full) --- 606port=system.cpu.toL2Bus.slave[2] 607 608[system.cpu.l2cache] 609type=BaseCache 610children=prefetcher tags 611addr_ranges=0:18446744073709551615 612assoc=16 613clk_domain=system.cpu_clk_domain |
| 614demand_mshr_reserve=1 |
|
| 610eventq_index=0 611forward_snoops=true 612hit_latency=12 613is_top_level=false 614max_miss_count=0 615mshrs=16 616prefetch_on_access=true 617prefetcher=system.cpu.l2cache.prefetcher --- 5 unchanged lines hidden (view full) --- 623tgts_per_mshr=8 624two_queue=false 625write_buffers=8 626cpu_side=system.cpu.toL2Bus.master[0] 627mem_side=system.membus.slave[1] 628 629[system.cpu.l2cache.prefetcher] 630type=StridePrefetcher | 615eventq_index=0 616forward_snoops=true 617hit_latency=12 618is_top_level=false 619max_miss_count=0 620mshrs=16 621prefetch_on_access=true 622prefetcher=system.cpu.l2cache.prefetcher --- 5 unchanged lines hidden (view full) --- 628tgts_per_mshr=8 629two_queue=false 630write_buffers=8 631cpu_side=system.cpu.toL2Bus.master[0] 632mem_side=system.membus.slave[1] 633 634[system.cpu.l2cache.prefetcher] 635type=StridePrefetcher |
| 636cache_snoop=false |
|
| 631clk_domain=system.cpu_clk_domain | 637clk_domain=system.cpu_clk_domain |
| 632cross_pages=false 633data_accesses_only=false | |
| 634degree=8 635eventq_index=0 | 638degree=8 639eventq_index=0 |
| 636inst_tagged=true | |
| 637latency=1 | 640latency=1 |
| 638on_miss_only=false 639on_prefetch=true 640on_read_only=false 641serial_squash=false 642size=100 | 641max_conf=7 642min_conf=0 643on_data=true 644on_inst=true 645on_miss=false 646on_read=true 647on_write=true 648queue_filter=true 649queue_size=32 650queue_squash=true 651start_conf=4 |
| 643sys=system | 652sys=system |
| 653table_assoc=4 654table_sets=16 655tag_prefetch=true 656thresh_conf=4 |
|
| 644use_master_id=true 645 646[system.cpu.l2cache.tags] 647type=RandomRepl 648assoc=16 649block_size=64 650clk_domain=system.cpu_clk_domain 651eventq_index=0 652hit_latency=12 653sequential_access=false 654size=1048576 655 656[system.cpu.toL2Bus] 657type=CoherentXBar 658clk_domain=system.cpu_clk_domain 659eventq_index=0 | 657use_master_id=true 658 659[system.cpu.l2cache.tags] 660type=RandomRepl 661assoc=16 662block_size=64 663clk_domain=system.cpu_clk_domain 664eventq_index=0 665hit_latency=12 666sequential_access=false 667size=1048576 668 669[system.cpu.toL2Bus] 670type=CoherentXBar 671clk_domain=system.cpu_clk_domain 672eventq_index=0 |
| 660header_cycles=1 | 673forward_latency=0 674frontend_latency=1 675response_latency=1 |
| 661snoop_filter=Null | 676snoop_filter=Null |
| 677snoop_response_latency=1 |
|
| 662system=system 663use_default_range=false 664width=32 665master=system.cpu.l2cache.cpu_side | 678system=system 679use_default_range=false 680width=32 681master=system.cpu.l2cache.cpu_side |
| 666slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port | 682slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| 667 668[system.cpu.tracer] 669type=ExeTracer 670eventq_index=0 671 672[system.cpu.workload] 673type=LiveProcess 674cmd=hello 675cwd= | 683 684[system.cpu.tracer] 685type=ExeTracer 686eventq_index=0 687 688[system.cpu.workload] 689type=LiveProcess 690cmd=hello 691cwd= |
| 692drivers= |
|
| 676egid=100 677env= 678errout=cerr 679euid=100 680eventq_index=0 681executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 682gid=100 683input=cin | 693egid=100 694env= 695errout=cerr 696euid=100 697eventq_index=0 698executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 699gid=100 700input=cin |
| 701kvmInSE=false |
|
| 684max_stack_size=67108864 685output=cout 686pid=100 687ppid=99 688simpoint=0 689system=system 690uid=100 691useArchPT=false --- 13 unchanged lines hidden (view full) --- 705eventq_index=0 706sys_clk_domain=system.clk_domain 707transition_latency=100000000 708 709[system.membus] 710type=CoherentXBar 711clk_domain=system.clk_domain 712eventq_index=0 | 702max_stack_size=67108864 703output=cout 704pid=100 705ppid=99 706simpoint=0 707system=system 708uid=100 709useArchPT=false --- 13 unchanged lines hidden (view full) --- 723eventq_index=0 724sys_clk_domain=system.clk_domain 725transition_latency=100000000 726 727[system.membus] 728type=CoherentXBar 729clk_domain=system.clk_domain 730eventq_index=0 |
| 713header_cycles=1 | 731forward_latency=4 732frontend_latency=3 733response_latency=2 |
| 714snoop_filter=Null | 734snoop_filter=Null |
| 735snoop_response_latency=4 |
|
| 715system=system 716use_default_range=false | 736system=system 737use_default_range=false |
| 717width=8 | 738width=16 |
| 718master=system.physmem.port 719slave=system.system_port system.cpu.l2cache.mem_side 720 721[system.physmem] 722type=DRAMCtrl 723IDD0=0.075000 724IDD02=0.000000 725IDD2N=0.050000 --- 14 unchanged lines hidden (view full) --- 740IDD4W2=0.000000 741IDD5=0.220000 742IDD52=0.000000 743IDD6=0.000000 744IDD62=0.000000 745VDD=1.500000 746VDD2=0.000000 747activation_limit=4 | 739master=system.physmem.port 740slave=system.system_port system.cpu.l2cache.mem_side 741 742[system.physmem] 743type=DRAMCtrl 744IDD0=0.075000 745IDD02=0.000000 746IDD2N=0.050000 --- 14 unchanged lines hidden (view full) --- 761IDD4W2=0.000000 762IDD5=0.220000 763IDD52=0.000000 764IDD6=0.000000 765IDD62=0.000000 766VDD=1.500000 767VDD2=0.000000 768activation_limit=4 |
| 748addr_mapping=RoRaBaChCo | 769addr_mapping=RoRaBaCoCh |
| 749bank_groups_per_rank=0 750banks_per_rank=8 751burst_length=8 752channels=1 753clk_domain=system.clk_domain 754conf_table_reported=true 755device_bus_width=8 756device_rowbuffer_size=1024 | 770bank_groups_per_rank=0 771banks_per_rank=8 772burst_length=8 773channels=1 774clk_domain=system.clk_domain 775conf_table_reported=true 776device_bus_width=8 777device_rowbuffer_size=1024 |
| 778device_size=536870912 |
|
| 757devices_per_rank=8 758dll=true 759eventq_index=0 760in_addr_map=true 761max_accesses_per_row=16 762mem_sched_policy=frfcfs 763min_writes_per_switch=16 764null=false --- 37 unchanged lines hidden --- | 779devices_per_rank=8 780dll=true 781eventq_index=0 782in_addr_map=true 783max_accesses_per_row=16 784mem_sched_policy=frfcfs 785min_writes_per_switch=16 786null=false --- 37 unchanged lines hidden --- |