1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 162 unchanged lines hidden (view full) --- 171 172[system.cpu.dcache] 173type=Cache 174children=tags 175addr_ranges=0:18446744073709551615:0:0:0:0 176assoc=2 177clk_domain=system.cpu_clk_domain 178clusivity=mostly_incl |
179data_latency=2 |
180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0 |
183is_read_only=false 184max_miss_count=0 185mshrs=6 186p_state_clk_gate_bins=20 187p_state_clk_gate_max=1000000000000 188p_state_clk_gate_min=1000 189power_model=Null 190prefetch_on_access=false 191prefetcher=Null 192response_latency=2 193sequential_access=false 194size=32768 195system=system |
196tag_latency=2 |
197tags=system.cpu.dcache.tags 198tgts_per_mshr=8 199write_buffers=16 200writeback_clean=true 201cpu_side=system.cpu.dcache_port 202mem_side=system.cpu.toL2Bus.slave[1] 203 204[system.cpu.dcache.tags] 205type=LRU 206assoc=2 207block_size=64 208clk_domain=system.cpu_clk_domain |
209data_latency=2 |
210default_p_state=UNDEFINED 211eventq_index=0 |
212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null 216sequential_access=false 217size=32768 |
218tag_latency=2 |
219 220[system.cpu.dstage2_mmu] 221type=ArmStage2MMU 222children=stage2_tlb 223eventq_index=0 224stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 225sys=system 226tlb=system.cpu.dtb --- 86 unchanged lines hidden (view full) --- 313type=OpDesc 314eventq_index=0 315opClass=IprAccess 316opLat=3 317pipelined=true 318 319[system.cpu.fuPool.FUList2] 320type=FUDesc |
321children=opList0 opList1 |
322count=1 323eventq_index=0 |
324opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 |
325 |
326[system.cpu.fuPool.FUList2.opList0] |
327type=OpDesc 328eventq_index=0 329opClass=MemRead 330opLat=2 331pipelined=true 332 |
333[system.cpu.fuPool.FUList2.opList1] 334type=OpDesc 335eventq_index=0 336opClass=FloatMemRead 337opLat=2 338pipelined=true 339 |
340[system.cpu.fuPool.FUList3] 341type=FUDesc |
342children=opList0 opList1 |
343count=1 344eventq_index=0 |
345opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 |
346 |
347[system.cpu.fuPool.FUList3.opList0] |
348type=OpDesc 349eventq_index=0 350opClass=MemWrite 351opLat=2 352pipelined=true 353 |
354[system.cpu.fuPool.FUList3.opList1] 355type=OpDesc 356eventq_index=0 357opClass=FloatMemWrite 358opLat=2 359pipelined=true 360 |
361[system.cpu.fuPool.FUList4] 362type=FUDesc |
363children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 |
364count=2 365eventq_index=0 |
366opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 |
367 368[system.cpu.fuPool.FUList4.opList00] 369type=OpDesc 370eventq_index=0 371opClass=SimdAdd 372opLat=4 373pipelined=true 374 --- 115 unchanged lines hidden (view full) --- 490opClass=SimdFloatMult 491opLat=3 492pipelined=true 493 494[system.cpu.fuPool.FUList4.opList18] 495type=OpDesc 496eventq_index=0 497opClass=SimdFloatMultAcc |
498opLat=5 |
499pipelined=true 500 501[system.cpu.fuPool.FUList4.opList19] 502type=OpDesc 503eventq_index=0 504opClass=SimdFloatSqrt 505opLat=9 506pipelined=true --- 35 unchanged lines hidden (view full) --- 542 543[system.cpu.fuPool.FUList4.opList25] 544type=OpDesc 545eventq_index=0 546opClass=FloatMult 547opLat=4 548pipelined=true 549 |
550[system.cpu.fuPool.FUList4.opList26] 551type=OpDesc 552eventq_index=0 553opClass=FloatMultAcc 554opLat=5 555pipelined=true 556 557[system.cpu.fuPool.FUList4.opList27] 558type=OpDesc 559eventq_index=0 560opClass=FloatMisc 561opLat=3 562pipelined=true 563 |
564[system.cpu.icache] 565type=Cache 566children=tags 567addr_ranges=0:18446744073709551615:0:0:0:0 568assoc=2 569clk_domain=system.cpu_clk_domain 570clusivity=mostly_incl |
571data_latency=1 |
572default_p_state=UNDEFINED 573demand_mshr_reserve=1 574eventq_index=0 |
575is_read_only=true 576max_miss_count=0 577mshrs=2 578p_state_clk_gate_bins=20 579p_state_clk_gate_max=1000000000000 580p_state_clk_gate_min=1000 581power_model=Null 582prefetch_on_access=false 583prefetcher=Null 584response_latency=1 585sequential_access=false 586size=32768 587system=system |
588tag_latency=1 |
589tags=system.cpu.icache.tags 590tgts_per_mshr=8 591write_buffers=8 592writeback_clean=true 593cpu_side=system.cpu.icache_port 594mem_side=system.cpu.toL2Bus.slave[0] 595 596[system.cpu.icache.tags] 597type=LRU 598assoc=2 599block_size=64 600clk_domain=system.cpu_clk_domain |
601data_latency=1 |
602default_p_state=UNDEFINED 603eventq_index=0 |
604p_state_clk_gate_bins=20 605p_state_clk_gate_max=1000000000000 606p_state_clk_gate_min=1000 607power_model=Null 608sequential_access=false 609size=32768 |
610tag_latency=1 |
611 612[system.cpu.interrupts] 613type=ArmInterrupts 614eventq_index=0 615 616[system.cpu.isa] 617type=ArmISA 618decoderFlavour=Generic --- 78 unchanged lines hidden (view full) --- 697 698[system.cpu.l2cache] 699type=Cache 700children=prefetcher tags 701addr_ranges=0:18446744073709551615:0:0:0:0 702assoc=16 703clk_domain=system.cpu_clk_domain 704clusivity=mostly_excl |
705data_latency=12 |
706default_p_state=UNDEFINED 707demand_mshr_reserve=1 708eventq_index=0 |
709is_read_only=false 710max_miss_count=0 711mshrs=16 712p_state_clk_gate_bins=20 713p_state_clk_gate_max=1000000000000 714p_state_clk_gate_min=1000 715power_model=Null 716prefetch_on_access=true 717prefetcher=system.cpu.l2cache.prefetcher 718response_latency=12 719sequential_access=false 720size=1048576 721system=system |
722tag_latency=12 |
723tags=system.cpu.l2cache.tags 724tgts_per_mshr=8 725write_buffers=8 726writeback_clean=false 727cpu_side=system.cpu.toL2Bus.master[0] 728mem_side=system.membus.slave[1] 729 730[system.cpu.l2cache.prefetcher] --- 26 unchanged lines hidden (view full) --- 757thresh_conf=4 758use_master_id=true 759 760[system.cpu.l2cache.tags] 761type=RandomRepl 762assoc=16 763block_size=64 764clk_domain=system.cpu_clk_domain |
765data_latency=12 |
766default_p_state=UNDEFINED 767eventq_index=0 |
768p_state_clk_gate_bins=20 769p_state_clk_gate_max=1000000000000 770p_state_clk_gate_min=1000 771power_model=Null 772sequential_access=false 773size=1048576 |
774tag_latency=12 |
775 776[system.cpu.toL2Bus] 777type=CoherentXBar 778children=snoop_filter 779clk_domain=system.cpu_clk_domain 780default_p_state=UNDEFINED 781eventq_index=0 782forward_latency=0 --- 28 unchanged lines hidden (view full) --- 811cmd=hello 812cwd= 813drivers= 814egid=100 815env= 816errout=cerr 817euid=100 818eventq_index=0 |
819executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello |
820gid=100 821input=cin 822kvmInSE=false 823max_stack_size=67108864 824output=cout 825pid=100 826ppid=99 827simpoint=0 --- 137 unchanged lines hidden --- |