25a26
> mmap_using_noreserve=false
159a161
> demand_mshr_reserve=1
193a196
> sys=system
211d213
< port=system.cpu.toL2Bus.slave[5]
500a503
> demand_mshr_reserve=1
560a564
> pmu=Null
567a572
> sys=system
585d589
< port=system.cpu.toL2Bus.slave[4]
609a614
> demand_mshr_reserve=1
630a636
> cache_snoop=false
632,633d637
< cross_pages=false
< data_accesses_only=false
636d639
< inst_tagged=true
638,642c641,651
< on_miss_only=false
< on_prefetch=true
< on_read_only=false
< serial_squash=false
< size=100
---
> max_conf=7
> min_conf=0
> on_data=true
> on_inst=true
> on_miss=false
> on_read=true
> on_write=true
> queue_filter=true
> queue_size=32
> queue_squash=true
> start_conf=4
643a653,656
> table_assoc=4
> table_sets=16
> tag_prefetch=true
> thresh_conf=4
660c673,675
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
661a677
> snoop_response_latency=1
666c682
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
675a692
> drivers=
683a701
> kvmInSE=false
713c731,733
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
714a735
> snoop_response_latency=4
717c738
< width=8
---
> width=16
748c769
< addr_mapping=RoRaBaChCo
---
> addr_mapping=RoRaBaCoCh
756a778
> device_size=536870912