1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16
|
19physmem=system.physmem
| |
20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99phase=0 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null 143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port 151mem_side=system.cpu.toL2Bus.slave[1] 152 153[system.cpu.dtb] 154type=ArmTLB 155children=walker 156size=64 157walker=system.cpu.dtb.walker 158 159[system.cpu.dtb.walker] 160type=ArmTableWalker 161max_backoff=100000 162min_backoff=0 163sys=system 164port=system.cpu.toL2Bus.slave[3] 165 166[system.cpu.fuPool] 167type=FUPool 168children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 169FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 170 171[system.cpu.fuPool.FUList0] 172type=FUDesc 173children=opList 174count=6 175opList=system.cpu.fuPool.FUList0.opList 176 177[system.cpu.fuPool.FUList0.opList] 178type=OpDesc 179issueLat=1 180opClass=IntAlu 181opLat=1 182 183[system.cpu.fuPool.FUList1] 184type=FUDesc 185children=opList0 opList1 186count=2 187opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 188 189[system.cpu.fuPool.FUList1.opList0] 190type=OpDesc 191issueLat=1 192opClass=IntMult 193opLat=3 194 195[system.cpu.fuPool.FUList1.opList1] 196type=OpDesc 197issueLat=19 198opClass=IntDiv 199opLat=20 200 201[system.cpu.fuPool.FUList2] 202type=FUDesc 203children=opList0 opList1 opList2 204count=4 205opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 206 207[system.cpu.fuPool.FUList2.opList0] 208type=OpDesc 209issueLat=1 210opClass=FloatAdd 211opLat=2 212 213[system.cpu.fuPool.FUList2.opList1] 214type=OpDesc 215issueLat=1 216opClass=FloatCmp 217opLat=2 218 219[system.cpu.fuPool.FUList2.opList2] 220type=OpDesc 221issueLat=1 222opClass=FloatCvt 223opLat=2 224 225[system.cpu.fuPool.FUList3] 226type=FUDesc 227children=opList0 opList1 opList2 228count=2 229opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 230 231[system.cpu.fuPool.FUList3.opList0] 232type=OpDesc 233issueLat=1 234opClass=FloatMult 235opLat=4 236 237[system.cpu.fuPool.FUList3.opList1] 238type=OpDesc 239issueLat=12 240opClass=FloatDiv 241opLat=12 242 243[system.cpu.fuPool.FUList3.opList2] 244type=OpDesc 245issueLat=24 246opClass=FloatSqrt 247opLat=24 248 249[system.cpu.fuPool.FUList4] 250type=FUDesc 251children=opList 252count=0 253opList=system.cpu.fuPool.FUList4.opList 254 255[system.cpu.fuPool.FUList4.opList] 256type=OpDesc 257issueLat=1 258opClass=MemRead 259opLat=1 260 261[system.cpu.fuPool.FUList5] 262type=FUDesc 263children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 264count=4 265opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 266 267[system.cpu.fuPool.FUList5.opList00] 268type=OpDesc 269issueLat=1 270opClass=SimdAdd 271opLat=1 272 273[system.cpu.fuPool.FUList5.opList01] 274type=OpDesc 275issueLat=1 276opClass=SimdAddAcc 277opLat=1 278 279[system.cpu.fuPool.FUList5.opList02] 280type=OpDesc 281issueLat=1 282opClass=SimdAlu 283opLat=1 284 285[system.cpu.fuPool.FUList5.opList03] 286type=OpDesc 287issueLat=1 288opClass=SimdCmp 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList04] 292type=OpDesc 293issueLat=1 294opClass=SimdCvt 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList05] 298type=OpDesc 299issueLat=1 300opClass=SimdMisc 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList06] 304type=OpDesc 305issueLat=1 306opClass=SimdMult 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList07] 310type=OpDesc 311issueLat=1 312opClass=SimdMultAcc 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList08] 316type=OpDesc 317issueLat=1 318opClass=SimdShift 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList09] 322type=OpDesc 323issueLat=1 324opClass=SimdShiftAcc 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList10] 328type=OpDesc 329issueLat=1 330opClass=SimdSqrt 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList11] 334type=OpDesc 335issueLat=1 336opClass=SimdFloatAdd 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList12] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatAlu 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList13] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatCmp 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList14] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatCvt 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList15] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatDiv 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList16] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatMisc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList17] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMult 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList18] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatMultAcc 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList19] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatSqrt 385opLat=1 386 387[system.cpu.fuPool.FUList6] 388type=FUDesc 389children=opList 390count=0 391opList=system.cpu.fuPool.FUList6.opList 392 393[system.cpu.fuPool.FUList6.opList] 394type=OpDesc 395issueLat=1 396opClass=MemWrite 397opLat=1 398 399[system.cpu.fuPool.FUList7] 400type=FUDesc 401children=opList0 opList1 402count=4 403opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 404 405[system.cpu.fuPool.FUList7.opList0] 406type=OpDesc 407issueLat=1 408opClass=MemRead 409opLat=1 410 411[system.cpu.fuPool.FUList7.opList1] 412type=OpDesc 413issueLat=1 414opClass=MemWrite 415opLat=1 416 417[system.cpu.fuPool.FUList8] 418type=FUDesc 419children=opList 420count=1 421opList=system.cpu.fuPool.FUList8.opList 422 423[system.cpu.fuPool.FUList8.opList] 424type=OpDesc 425issueLat=3 426opClass=IprAccess 427opLat=3 428 429[system.cpu.icache] 430type=BaseCache 431addr_ranges=0:18446744073709551615 432assoc=2 433block_size=64 434forward_snoops=true 435hash_delay=1 436is_top_level=true 437latency=1000 438max_miss_count=0 439mshrs=10 440prefetch_on_access=false 441prefetcher=Null 442prioritizeRequests=false 443repl=Null 444size=131072 445subblock_size=0 446system=system 447tgts_per_mshr=20 448trace_addr=0 449two_queue=false 450write_buffers=8 451cpu_side=system.cpu.icache_port 452mem_side=system.cpu.toL2Bus.slave[0] 453 454[system.cpu.interrupts] 455type=ArmInterrupts 456 457[system.cpu.itb] 458type=ArmTLB 459children=walker 460size=64 461walker=system.cpu.itb.walker 462 463[system.cpu.itb.walker] 464type=ArmTableWalker 465max_backoff=100000 466min_backoff=0 467sys=system 468port=system.cpu.toL2Bus.slave[2] 469 470[system.cpu.l2cache] 471type=BaseCache 472addr_ranges=0:18446744073709551615 473assoc=2 474block_size=64 475forward_snoops=true 476hash_delay=1 477is_top_level=false 478latency=1000 479max_miss_count=0 480mshrs=10 481prefetch_on_access=false 482prefetcher=Null 483prioritizeRequests=false 484repl=Null 485size=2097152 486subblock_size=0 487system=system 488tgts_per_mshr=5 489trace_addr=0 490two_queue=false 491write_buffers=8 492cpu_side=system.cpu.toL2Bus.master[0] 493mem_side=system.membus.slave[1] 494 495[system.cpu.toL2Bus] 496type=Bus 497block_size=64 498bus_id=0 499clock=1000 500header_cycles=1 501use_default_range=false 502width=64 503master=system.cpu.l2cache.cpu_side 504slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 505 506[system.cpu.tracer] 507type=ExeTracer 508 509[system.cpu.workload] 510type=LiveProcess 511cmd=hello 512cwd= 513egid=100 514env= 515errout=cerr 516euid=100
| 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 28system_port=system.membus.slave[0] 29 30[system.cpu] 31type=DerivO3CPU 32children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39RASSize=16 40SQEntries=32 41SSITSize=1024 42activity=0 43backComSize=5 44cachePorts=200 45checker=Null 46choiceCtrBits=2 47choicePredictorSize=8192 48clock=500 49commitToDecodeDelay=1 50commitToFetchDelay=1 51commitToIEWDelay=1 52commitToRenameDelay=1 53commitWidth=8 54cpu_id=0 55decodeToFetchDelay=1 56decodeToRenameDelay=1 57decodeWidth=8 58defer_registration=false 59dispatchWidth=8 60do_checkpoint_insts=true 61do_quiesce=true 62do_statistics_insts=true 63dtb=system.cpu.dtb 64fetchToDecodeDelay=1 65fetchTrapLatency=1 66fetchWidth=8 67forwardComSize=5 68fuPool=system.cpu.fuPool 69function_trace=false 70function_trace_start=0 71globalCtrBits=2 72globalHistoryBits=13 73globalPredictorSize=8192 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78instShiftAmt=2 79interrupts=system.cpu.interrupts 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83localCtrBits=2 84localHistoryBits=11 85localHistoryTableSize=2048 86localPredictorSize=2048 87max_insts_all_threads=0 88max_insts_any_thread=0 89max_loads_all_threads=0 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 98phase=0 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 132forward_snoops=true 133hash_delay=1 134is_top_level=true 135latency=1000 136max_miss_count=0 137mshrs=10 138prefetch_on_access=false 139prefetcher=Null 140prioritizeRequests=false 141repl=Null 142size=262144 143subblock_size=0 144system=system 145tgts_per_mshr=20 146trace_addr=0 147two_queue=false 148write_buffers=8 149cpu_side=system.cpu.dcache_port 150mem_side=system.cpu.toL2Bus.slave[1] 151 152[system.cpu.dtb] 153type=ArmTLB 154children=walker 155size=64 156walker=system.cpu.dtb.walker 157 158[system.cpu.dtb.walker] 159type=ArmTableWalker 160max_backoff=100000 161min_backoff=0 162sys=system 163port=system.cpu.toL2Bus.slave[3] 164 165[system.cpu.fuPool] 166type=FUPool 167children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 168FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 169 170[system.cpu.fuPool.FUList0] 171type=FUDesc 172children=opList 173count=6 174opList=system.cpu.fuPool.FUList0.opList 175 176[system.cpu.fuPool.FUList0.opList] 177type=OpDesc 178issueLat=1 179opClass=IntAlu 180opLat=1 181 182[system.cpu.fuPool.FUList1] 183type=FUDesc 184children=opList0 opList1 185count=2 186opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 187 188[system.cpu.fuPool.FUList1.opList0] 189type=OpDesc 190issueLat=1 191opClass=IntMult 192opLat=3 193 194[system.cpu.fuPool.FUList1.opList1] 195type=OpDesc 196issueLat=19 197opClass=IntDiv 198opLat=20 199 200[system.cpu.fuPool.FUList2] 201type=FUDesc 202children=opList0 opList1 opList2 203count=4 204opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 205 206[system.cpu.fuPool.FUList2.opList0] 207type=OpDesc 208issueLat=1 209opClass=FloatAdd 210opLat=2 211 212[system.cpu.fuPool.FUList2.opList1] 213type=OpDesc 214issueLat=1 215opClass=FloatCmp 216opLat=2 217 218[system.cpu.fuPool.FUList2.opList2] 219type=OpDesc 220issueLat=1 221opClass=FloatCvt 222opLat=2 223 224[system.cpu.fuPool.FUList3] 225type=FUDesc 226children=opList0 opList1 opList2 227count=2 228opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 229 230[system.cpu.fuPool.FUList3.opList0] 231type=OpDesc 232issueLat=1 233opClass=FloatMult 234opLat=4 235 236[system.cpu.fuPool.FUList3.opList1] 237type=OpDesc 238issueLat=12 239opClass=FloatDiv 240opLat=12 241 242[system.cpu.fuPool.FUList3.opList2] 243type=OpDesc 244issueLat=24 245opClass=FloatSqrt 246opLat=24 247 248[system.cpu.fuPool.FUList4] 249type=FUDesc 250children=opList 251count=0 252opList=system.cpu.fuPool.FUList4.opList 253 254[system.cpu.fuPool.FUList4.opList] 255type=OpDesc 256issueLat=1 257opClass=MemRead 258opLat=1 259 260[system.cpu.fuPool.FUList5] 261type=FUDesc 262children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 263count=4 264opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 265 266[system.cpu.fuPool.FUList5.opList00] 267type=OpDesc 268issueLat=1 269opClass=SimdAdd 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList01] 273type=OpDesc 274issueLat=1 275opClass=SimdAddAcc 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList02] 279type=OpDesc 280issueLat=1 281opClass=SimdAlu 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList03] 285type=OpDesc 286issueLat=1 287opClass=SimdCmp 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList04] 291type=OpDesc 292issueLat=1 293opClass=SimdCvt 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList05] 297type=OpDesc 298issueLat=1 299opClass=SimdMisc 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList06] 303type=OpDesc 304issueLat=1 305opClass=SimdMult 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList07] 309type=OpDesc 310issueLat=1 311opClass=SimdMultAcc 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList08] 315type=OpDesc 316issueLat=1 317opClass=SimdShift 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList09] 321type=OpDesc 322issueLat=1 323opClass=SimdShiftAcc 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList10] 327type=OpDesc 328issueLat=1 329opClass=SimdSqrt 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList11] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatAdd 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList12] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatAlu 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList13] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatCmp 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList14] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatCvt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList15] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatDiv 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList16] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMisc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList17] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatMult 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList18] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatMultAcc 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList19] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatSqrt 384opLat=1 385 386[system.cpu.fuPool.FUList6] 387type=FUDesc 388children=opList 389count=0 390opList=system.cpu.fuPool.FUList6.opList 391 392[system.cpu.fuPool.FUList6.opList] 393type=OpDesc 394issueLat=1 395opClass=MemWrite 396opLat=1 397 398[system.cpu.fuPool.FUList7] 399type=FUDesc 400children=opList0 opList1 401count=4 402opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 403 404[system.cpu.fuPool.FUList7.opList0] 405type=OpDesc 406issueLat=1 407opClass=MemRead 408opLat=1 409 410[system.cpu.fuPool.FUList7.opList1] 411type=OpDesc 412issueLat=1 413opClass=MemWrite 414opLat=1 415 416[system.cpu.fuPool.FUList8] 417type=FUDesc 418children=opList 419count=1 420opList=system.cpu.fuPool.FUList8.opList 421 422[system.cpu.fuPool.FUList8.opList] 423type=OpDesc 424issueLat=3 425opClass=IprAccess 426opLat=3 427 428[system.cpu.icache] 429type=BaseCache 430addr_ranges=0:18446744073709551615 431assoc=2 432block_size=64 433forward_snoops=true 434hash_delay=1 435is_top_level=true 436latency=1000 437max_miss_count=0 438mshrs=10 439prefetch_on_access=false 440prefetcher=Null 441prioritizeRequests=false 442repl=Null 443size=131072 444subblock_size=0 445system=system 446tgts_per_mshr=20 447trace_addr=0 448two_queue=false 449write_buffers=8 450cpu_side=system.cpu.icache_port 451mem_side=system.cpu.toL2Bus.slave[0] 452 453[system.cpu.interrupts] 454type=ArmInterrupts 455 456[system.cpu.itb] 457type=ArmTLB 458children=walker 459size=64 460walker=system.cpu.itb.walker 461 462[system.cpu.itb.walker] 463type=ArmTableWalker 464max_backoff=100000 465min_backoff=0 466sys=system 467port=system.cpu.toL2Bus.slave[2] 468 469[system.cpu.l2cache] 470type=BaseCache 471addr_ranges=0:18446744073709551615 472assoc=2 473block_size=64 474forward_snoops=true 475hash_delay=1 476is_top_level=false 477latency=1000 478max_miss_count=0 479mshrs=10 480prefetch_on_access=false 481prefetcher=Null 482prioritizeRequests=false 483repl=Null 484size=2097152 485subblock_size=0 486system=system 487tgts_per_mshr=5 488trace_addr=0 489two_queue=false 490write_buffers=8 491cpu_side=system.cpu.toL2Bus.master[0] 492mem_side=system.membus.slave[1] 493 494[system.cpu.toL2Bus] 495type=Bus 496block_size=64 497bus_id=0 498clock=1000 499header_cycles=1 500use_default_range=false 501width=64 502master=system.cpu.l2cache.cpu_side 503slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 504 505[system.cpu.tracer] 506type=ExeTracer 507 508[system.cpu.workload] 509type=LiveProcess 510cmd=hello 511cwd= 512egid=100 513env= 514errout=cerr 515euid=100
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517executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
| 516executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
|
518gid=100 519input=cin 520max_stack_size=67108864 521output=cout 522pid=100 523ppid=99 524simpoint=0 525system=system 526uid=100 527 528[system.membus] 529type=Bus 530block_size=64 531bus_id=0 532clock=1000 533header_cycles=1 534use_default_range=false 535width=64 536master=system.physmem.port[0] 537slave=system.system_port system.cpu.l2cache.mem_side 538 539[system.physmem]
| 517gid=100 518input=cin 519max_stack_size=67108864 520output=cout 521pid=100 522ppid=99 523simpoint=0 524system=system 525uid=100 526 527[system.membus] 528type=Bus 529block_size=64 530bus_id=0 531clock=1000 532header_cycles=1 533use_default_range=false 534width=64 535master=system.physmem.port[0] 536slave=system.system_port system.cpu.l2cache.mem_side 537 538[system.physmem]
|
540type=PhysicalMemory
| 539type=SimpleMemory 540conf_table_reported=false
|
541file=
| 541file=
|
| 542in_addr_map=true
|
542latency=30000 543latency_var=0 544null=false 545range=0:134217727 546zero=false 547port=system.membus.master[0] 548
| 543latency=30000 544latency_var=0 545null=false 546range=0:134217727 547zero=false 548port=system.membus.master[0] 549
|