Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini

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config.ini (10451:3a87241adfb8)	config.ini (10736:4433fb00fa7d)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem
	26mmap_using_noreserve=false
26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=16 51LSQCheckLoads=true 52LSQDepCheckShift=0 53SQEntries=16 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=2 69decodeWidth=3 70dispatchWidth=6 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dstage2_mmu=system.cpu.dstage2_mmu 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=16 78fetchQueueSize=32 79fetchToDecodeDelay=3 80fetchTrapLatency=1 81fetchWidth=3 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94istage2_mmu=system.cpu.istage2_mmu 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=32 102numPhysCCRegs=640 103numPhysFloatRegs=192 104numPhysIntRegs=128 105numROBEntries=40 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=1 113renameToROBDelay=1 114renameWidth=3 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=BranchPredictor 139BTBEntries=2048 140BTBTagSize=18 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152predType=bi-mode 153 154[system.cpu.dcache] 155type=BaseCache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=2 159clk_domain=system.cpu_clk_domain	27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=16 52LSQCheckLoads=true 53LSQDepCheckShift=0 54SQEntries=16 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=2 70decodeWidth=3 71dispatchWidth=6 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dstage2_mmu=system.cpu.dstage2_mmu 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=16 79fetchQueueSize=32 80fetchToDecodeDelay=3 81fetchTrapLatency=1 82fetchWidth=3 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95istage2_mmu=system.cpu.istage2_mmu 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=32 103numPhysCCRegs=640 104numPhysFloatRegs=192 105numPhysIntRegs=128 106numROBEntries=40 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=1 114renameToROBDelay=1 115renameWidth=3 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] 139type=BranchPredictor 140BTBEntries=2048 141BTBTagSize=18 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153predType=bi-mode 154 155[system.cpu.dcache] 156type=BaseCache 157children=tags 158addr_ranges=0:18446744073709551615 159assoc=2 160clk_domain=system.cpu_clk_domain
	161demand_mshr_reserve=1
160eventq_index=0 161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=6 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169sequential_access=false 170size=32768 171system=system 172tags=system.cpu.dcache.tags 173tgts_per_mshr=8 174two_queue=false 175write_buffers=16 176cpu_side=system.cpu.dcache_port 177mem_side=system.cpu.toL2Bus.slave[1] 178 179[system.cpu.dcache.tags] 180type=LRU 181assoc=2 182block_size=64 183clk_domain=system.cpu_clk_domain 184eventq_index=0 185hit_latency=2 186sequential_access=false 187size=32768 188 189[system.cpu.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb	162eventq_index=0 163forward_snoops=true 164hit_latency=2 165is_top_level=true 166max_miss_count=0 167mshrs=6 168prefetch_on_access=false 169prefetcher=Null 170response_latency=2 171sequential_access=false 172size=32768 173system=system 174tags=system.cpu.dcache.tags 175tgts_per_mshr=8 176two_queue=false 177write_buffers=16 178cpu_side=system.cpu.dcache_port 179mem_side=system.cpu.toL2Bus.slave[1] 180 181[system.cpu.dcache.tags] 182type=LRU 183assoc=2 184block_size=64 185clk_domain=system.cpu_clk_domain 186eventq_index=0 187hit_latency=2 188sequential_access=false 189size=32768 190 191[system.cpu.dstage2_mmu] 192type=ArmStage2MMU 193children=stage2_tlb 194eventq_index=0 195stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
	196sys=system
194tlb=system.cpu.dtb 195 196[system.cpu.dstage2_mmu.stage2_tlb] 197type=ArmTLB 198children=walker 199eventq_index=0 200is_stage2=true 201size=32 202walker=system.cpu.dstage2_mmu.stage2_tlb.walker 203 204[system.cpu.dstage2_mmu.stage2_tlb.walker] 205type=ArmTableWalker 206clk_domain=system.cpu_clk_domain 207eventq_index=0 208is_stage2=true 209num_squash_per_cycle=2 210sys=system	197tlb=system.cpu.dtb 198 199[system.cpu.dstage2_mmu.stage2_tlb] 200type=ArmTLB 201children=walker 202eventq_index=0 203is_stage2=true 204size=32 205walker=system.cpu.dstage2_mmu.stage2_tlb.walker 206 207[system.cpu.dstage2_mmu.stage2_tlb.walker] 208type=ArmTableWalker 209clk_domain=system.cpu_clk_domain 210eventq_index=0 211is_stage2=true 212num_squash_per_cycle=2 213sys=system
211port=system.cpu.toL2Bus.slave[5]
212 213[system.cpu.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.dtb.walker 220 221[system.cpu.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system 228port=system.cpu.toL2Bus.slave[3] 229 230[system.cpu.fuPool] 231type=FUPool 232children=FUList0 FUList1 FUList2 FUList3 FUList4 233FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 234eventq_index=0 235 236[system.cpu.fuPool.FUList0] 237type=FUDesc 238children=opList 239count=2 240eventq_index=0 241opList=system.cpu.fuPool.FUList0.opList 242 243[system.cpu.fuPool.FUList0.opList] 244type=OpDesc 245eventq_index=0 246issueLat=1 247opClass=IntAlu 248opLat=1 249 250[system.cpu.fuPool.FUList1] 251type=FUDesc 252children=opList0 opList1 opList2 253count=1 254eventq_index=0 255opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 256 257[system.cpu.fuPool.FUList1.opList0] 258type=OpDesc 259eventq_index=0 260issueLat=1 261opClass=IntMult 262opLat=3 263 264[system.cpu.fuPool.FUList1.opList1] 265type=OpDesc 266eventq_index=0 267issueLat=12 268opClass=IntDiv 269opLat=12 270 271[system.cpu.fuPool.FUList1.opList2] 272type=OpDesc 273eventq_index=0 274issueLat=1 275opClass=IprAccess 276opLat=3 277 278[system.cpu.fuPool.FUList2] 279type=FUDesc 280children=opList 281count=1 282eventq_index=0 283opList=system.cpu.fuPool.FUList2.opList 284 285[system.cpu.fuPool.FUList2.opList] 286type=OpDesc 287eventq_index=0 288issueLat=1 289opClass=MemRead 290opLat=2 291 292[system.cpu.fuPool.FUList3] 293type=FUDesc 294children=opList 295count=1 296eventq_index=0 297opList=system.cpu.fuPool.FUList3.opList 298 299[system.cpu.fuPool.FUList3.opList] 300type=OpDesc 301eventq_index=0 302issueLat=1 303opClass=MemWrite 304opLat=2 305 306[system.cpu.fuPool.FUList4] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 309count=2 310eventq_index=0 311opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 312 313[system.cpu.fuPool.FUList4.opList00] 314type=OpDesc 315eventq_index=0 316issueLat=1 317opClass=SimdAdd 318opLat=4 319 320[system.cpu.fuPool.FUList4.opList01] 321type=OpDesc 322eventq_index=0 323issueLat=1 324opClass=SimdAddAcc 325opLat=4 326 327[system.cpu.fuPool.FUList4.opList02] 328type=OpDesc 329eventq_index=0 330issueLat=1 331opClass=SimdAlu 332opLat=4 333 334[system.cpu.fuPool.FUList4.opList03] 335type=OpDesc 336eventq_index=0 337issueLat=1 338opClass=SimdCmp 339opLat=4 340 341[system.cpu.fuPool.FUList4.opList04] 342type=OpDesc 343eventq_index=0 344issueLat=1 345opClass=SimdCvt 346opLat=3 347 348[system.cpu.fuPool.FUList4.opList05] 349type=OpDesc 350eventq_index=0 351issueLat=1 352opClass=SimdMisc 353opLat=3 354 355[system.cpu.fuPool.FUList4.opList06] 356type=OpDesc 357eventq_index=0 358issueLat=1 359opClass=SimdMult 360opLat=5 361 362[system.cpu.fuPool.FUList4.opList07] 363type=OpDesc 364eventq_index=0 365issueLat=1 366opClass=SimdMultAcc 367opLat=5 368 369[system.cpu.fuPool.FUList4.opList08] 370type=OpDesc 371eventq_index=0 372issueLat=1 373opClass=SimdShift 374opLat=3 375 376[system.cpu.fuPool.FUList4.opList09] 377type=OpDesc 378eventq_index=0 379issueLat=1 380opClass=SimdShiftAcc 381opLat=3 382 383[system.cpu.fuPool.FUList4.opList10] 384type=OpDesc 385eventq_index=0 386issueLat=1 387opClass=SimdSqrt 388opLat=9 389 390[system.cpu.fuPool.FUList4.opList11] 391type=OpDesc 392eventq_index=0 393issueLat=1 394opClass=SimdFloatAdd 395opLat=5 396 397[system.cpu.fuPool.FUList4.opList12] 398type=OpDesc 399eventq_index=0 400issueLat=1 401opClass=SimdFloatAlu 402opLat=5 403 404[system.cpu.fuPool.FUList4.opList13] 405type=OpDesc 406eventq_index=0 407issueLat=1 408opClass=SimdFloatCmp 409opLat=3 410 411[system.cpu.fuPool.FUList4.opList14] 412type=OpDesc 413eventq_index=0 414issueLat=1 415opClass=SimdFloatCvt 416opLat=3 417 418[system.cpu.fuPool.FUList4.opList15] 419type=OpDesc 420eventq_index=0 421issueLat=1 422opClass=SimdFloatDiv 423opLat=3 424 425[system.cpu.fuPool.FUList4.opList16] 426type=OpDesc 427eventq_index=0 428issueLat=1 429opClass=SimdFloatMisc 430opLat=3 431 432[system.cpu.fuPool.FUList4.opList17] 433type=OpDesc 434eventq_index=0 435issueLat=1 436opClass=SimdFloatMult 437opLat=3 438 439[system.cpu.fuPool.FUList4.opList18] 440type=OpDesc 441eventq_index=0 442issueLat=1 443opClass=SimdFloatMultAcc 444opLat=1 445 446[system.cpu.fuPool.FUList4.opList19] 447type=OpDesc 448eventq_index=0 449issueLat=1 450opClass=SimdFloatSqrt 451opLat=9 452 453[system.cpu.fuPool.FUList4.opList20] 454type=OpDesc 455eventq_index=0 456issueLat=1 457opClass=FloatAdd 458opLat=5 459 460[system.cpu.fuPool.FUList4.opList21] 461type=OpDesc 462eventq_index=0 463issueLat=1 464opClass=FloatCmp 465opLat=5 466 467[system.cpu.fuPool.FUList4.opList22] 468type=OpDesc 469eventq_index=0 470issueLat=1 471opClass=FloatCvt 472opLat=5 473 474[system.cpu.fuPool.FUList4.opList23] 475type=OpDesc 476eventq_index=0 477issueLat=9 478opClass=FloatDiv 479opLat=9 480 481[system.cpu.fuPool.FUList4.opList24] 482type=OpDesc 483eventq_index=0 484issueLat=33 485opClass=FloatSqrt 486opLat=33 487 488[system.cpu.fuPool.FUList4.opList25] 489type=OpDesc 490eventq_index=0 491issueLat=1 492opClass=FloatMult 493opLat=4 494 495[system.cpu.icache] 496type=BaseCache 497children=tags 498addr_ranges=0:18446744073709551615 499assoc=2 500clk_domain=system.cpu_clk_domain	214 215[system.cpu.dtb] 216type=ArmTLB 217children=walker 218eventq_index=0 219is_stage2=false 220size=64 221walker=system.cpu.dtb.walker 222 223[system.cpu.dtb.walker] 224type=ArmTableWalker 225clk_domain=system.cpu_clk_domain 226eventq_index=0 227is_stage2=false 228num_squash_per_cycle=2 229sys=system 230port=system.cpu.toL2Bus.slave[3] 231 232[system.cpu.fuPool] 233type=FUPool 234children=FUList0 FUList1 FUList2 FUList3 FUList4 235FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 236eventq_index=0 237 238[system.cpu.fuPool.FUList0] 239type=FUDesc 240children=opList 241count=2 242eventq_index=0 243opList=system.cpu.fuPool.FUList0.opList 244 245[system.cpu.fuPool.FUList0.opList] 246type=OpDesc 247eventq_index=0 248issueLat=1 249opClass=IntAlu 250opLat=1 251 252[system.cpu.fuPool.FUList1] 253type=FUDesc 254children=opList0 opList1 opList2 255count=1 256eventq_index=0 257opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 258 259[system.cpu.fuPool.FUList1.opList0] 260type=OpDesc 261eventq_index=0 262issueLat=1 263opClass=IntMult 264opLat=3 265 266[system.cpu.fuPool.FUList1.opList1] 267type=OpDesc 268eventq_index=0 269issueLat=12 270opClass=IntDiv 271opLat=12 272 273[system.cpu.fuPool.FUList1.opList2] 274type=OpDesc 275eventq_index=0 276issueLat=1 277opClass=IprAccess 278opLat=3 279 280[system.cpu.fuPool.FUList2] 281type=FUDesc 282children=opList 283count=1 284eventq_index=0 285opList=system.cpu.fuPool.FUList2.opList 286 287[system.cpu.fuPool.FUList2.opList] 288type=OpDesc 289eventq_index=0 290issueLat=1 291opClass=MemRead 292opLat=2 293 294[system.cpu.fuPool.FUList3] 295type=FUDesc 296children=opList 297count=1 298eventq_index=0 299opList=system.cpu.fuPool.FUList3.opList 300 301[system.cpu.fuPool.FUList3.opList] 302type=OpDesc 303eventq_index=0 304issueLat=1 305opClass=MemWrite 306opLat=2 307 308[system.cpu.fuPool.FUList4] 309type=FUDesc 310children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 311count=2 312eventq_index=0 313opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 314 315[system.cpu.fuPool.FUList4.opList00] 316type=OpDesc 317eventq_index=0 318issueLat=1 319opClass=SimdAdd 320opLat=4 321 322[system.cpu.fuPool.FUList4.opList01] 323type=OpDesc 324eventq_index=0 325issueLat=1 326opClass=SimdAddAcc 327opLat=4 328 329[system.cpu.fuPool.FUList4.opList02] 330type=OpDesc 331eventq_index=0 332issueLat=1 333opClass=SimdAlu 334opLat=4 335 336[system.cpu.fuPool.FUList4.opList03] 337type=OpDesc 338eventq_index=0 339issueLat=1 340opClass=SimdCmp 341opLat=4 342 343[system.cpu.fuPool.FUList4.opList04] 344type=OpDesc 345eventq_index=0 346issueLat=1 347opClass=SimdCvt 348opLat=3 349 350[system.cpu.fuPool.FUList4.opList05] 351type=OpDesc 352eventq_index=0 353issueLat=1 354opClass=SimdMisc 355opLat=3 356 357[system.cpu.fuPool.FUList4.opList06] 358type=OpDesc 359eventq_index=0 360issueLat=1 361opClass=SimdMult 362opLat=5 363 364[system.cpu.fuPool.FUList4.opList07] 365type=OpDesc 366eventq_index=0 367issueLat=1 368opClass=SimdMultAcc 369opLat=5 370 371[system.cpu.fuPool.FUList4.opList08] 372type=OpDesc 373eventq_index=0 374issueLat=1 375opClass=SimdShift 376opLat=3 377 378[system.cpu.fuPool.FUList4.opList09] 379type=OpDesc 380eventq_index=0 381issueLat=1 382opClass=SimdShiftAcc 383opLat=3 384 385[system.cpu.fuPool.FUList4.opList10] 386type=OpDesc 387eventq_index=0 388issueLat=1 389opClass=SimdSqrt 390opLat=9 391 392[system.cpu.fuPool.FUList4.opList11] 393type=OpDesc 394eventq_index=0 395issueLat=1 396opClass=SimdFloatAdd 397opLat=5 398 399[system.cpu.fuPool.FUList4.opList12] 400type=OpDesc 401eventq_index=0 402issueLat=1 403opClass=SimdFloatAlu 404opLat=5 405 406[system.cpu.fuPool.FUList4.opList13] 407type=OpDesc 408eventq_index=0 409issueLat=1 410opClass=SimdFloatCmp 411opLat=3 412 413[system.cpu.fuPool.FUList4.opList14] 414type=OpDesc 415eventq_index=0 416issueLat=1 417opClass=SimdFloatCvt 418opLat=3 419 420[system.cpu.fuPool.FUList4.opList15] 421type=OpDesc 422eventq_index=0 423issueLat=1 424opClass=SimdFloatDiv 425opLat=3 426 427[system.cpu.fuPool.FUList4.opList16] 428type=OpDesc 429eventq_index=0 430issueLat=1 431opClass=SimdFloatMisc 432opLat=3 433 434[system.cpu.fuPool.FUList4.opList17] 435type=OpDesc 436eventq_index=0 437issueLat=1 438opClass=SimdFloatMult 439opLat=3 440 441[system.cpu.fuPool.FUList4.opList18] 442type=OpDesc 443eventq_index=0 444issueLat=1 445opClass=SimdFloatMultAcc 446opLat=1 447 448[system.cpu.fuPool.FUList4.opList19] 449type=OpDesc 450eventq_index=0 451issueLat=1 452opClass=SimdFloatSqrt 453opLat=9 454 455[system.cpu.fuPool.FUList4.opList20] 456type=OpDesc 457eventq_index=0 458issueLat=1 459opClass=FloatAdd 460opLat=5 461 462[system.cpu.fuPool.FUList4.opList21] 463type=OpDesc 464eventq_index=0 465issueLat=1 466opClass=FloatCmp 467opLat=5 468 469[system.cpu.fuPool.FUList4.opList22] 470type=OpDesc 471eventq_index=0 472issueLat=1 473opClass=FloatCvt 474opLat=5 475 476[system.cpu.fuPool.FUList4.opList23] 477type=OpDesc 478eventq_index=0 479issueLat=9 480opClass=FloatDiv 481opLat=9 482 483[system.cpu.fuPool.FUList4.opList24] 484type=OpDesc 485eventq_index=0 486issueLat=33 487opClass=FloatSqrt 488opLat=33 489 490[system.cpu.fuPool.FUList4.opList25] 491type=OpDesc 492eventq_index=0 493issueLat=1 494opClass=FloatMult 495opLat=4 496 497[system.cpu.icache] 498type=BaseCache 499children=tags 500addr_ranges=0:18446744073709551615 501assoc=2 502clk_domain=system.cpu_clk_domain
	503demand_mshr_reserve=1
501eventq_index=0 502forward_snoops=true 503hit_latency=1 504is_top_level=true 505max_miss_count=0 506mshrs=2 507prefetch_on_access=false 508prefetcher=Null 509response_latency=1 510sequential_access=false 511size=32768 512system=system 513tags=system.cpu.icache.tags 514tgts_per_mshr=8 515two_queue=false 516write_buffers=8 517cpu_side=system.cpu.icache_port 518mem_side=system.cpu.toL2Bus.slave[0] 519 520[system.cpu.icache.tags] 521type=LRU 522assoc=2 523block_size=64 524clk_domain=system.cpu_clk_domain 525eventq_index=0 526hit_latency=1 527sequential_access=false 528size=32768 529 530[system.cpu.interrupts] 531type=ArmInterrupts 532eventq_index=0 533 534[system.cpu.isa] 535type=ArmISA 536eventq_index=0 537fpsid=1090793632 538id_aa64afr0_el1=0 539id_aa64afr1_el1=0 540id_aa64dfr0_el1=1052678 541id_aa64dfr1_el1=0 542id_aa64isar0_el1=0 543id_aa64isar1_el1=0 544id_aa64mmfr0_el1=15728642 545id_aa64mmfr1_el1=0 546id_aa64pfr0_el1=17 547id_aa64pfr1_el1=0 548id_isar0=34607377 549id_isar1=34677009 550id_isar2=555950401 551id_isar3=17899825 552id_isar4=268501314 553id_isar5=0 554id_mmfr0=270536963 555id_mmfr1=0 556id_mmfr2=19070976 557id_mmfr3=34611729 558id_pfr0=49 559id_pfr1=4113 560midr=1091551472	504eventq_index=0 505forward_snoops=true 506hit_latency=1 507is_top_level=true 508max_miss_count=0 509mshrs=2 510prefetch_on_access=false 511prefetcher=Null 512response_latency=1 513sequential_access=false 514size=32768 515system=system 516tags=system.cpu.icache.tags 517tgts_per_mshr=8 518two_queue=false 519write_buffers=8 520cpu_side=system.cpu.icache_port 521mem_side=system.cpu.toL2Bus.slave[0] 522 523[system.cpu.icache.tags] 524type=LRU 525assoc=2 526block_size=64 527clk_domain=system.cpu_clk_domain 528eventq_index=0 529hit_latency=1 530sequential_access=false 531size=32768 532 533[system.cpu.interrupts] 534type=ArmInterrupts 535eventq_index=0 536 537[system.cpu.isa] 538type=ArmISA 539eventq_index=0 540fpsid=1090793632 541id_aa64afr0_el1=0 542id_aa64afr1_el1=0 543id_aa64dfr0_el1=1052678 544id_aa64dfr1_el1=0 545id_aa64isar0_el1=0 546id_aa64isar1_el1=0 547id_aa64mmfr0_el1=15728642 548id_aa64mmfr1_el1=0 549id_aa64pfr0_el1=17 550id_aa64pfr1_el1=0 551id_isar0=34607377 552id_isar1=34677009 553id_isar2=555950401 554id_isar3=17899825 555id_isar4=268501314 556id_isar5=0 557id_mmfr0=270536963 558id_mmfr1=0 559id_mmfr2=19070976 560id_mmfr3=34611729 561id_pfr0=49 562id_pfr1=4113 563midr=1091551472
	564pmu=Null
561system=system 562 563[system.cpu.istage2_mmu] 564type=ArmStage2MMU 565children=stage2_tlb 566eventq_index=0 567stage2_tlb=system.cpu.istage2_mmu.stage2_tlb	565system=system 566 567[system.cpu.istage2_mmu] 568type=ArmStage2MMU 569children=stage2_tlb 570eventq_index=0 571stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
	572sys=system
568tlb=system.cpu.itb 569 570[system.cpu.istage2_mmu.stage2_tlb] 571type=ArmTLB 572children=walker 573eventq_index=0 574is_stage2=true 575size=32 576walker=system.cpu.istage2_mmu.stage2_tlb.walker 577 578[system.cpu.istage2_mmu.stage2_tlb.walker] 579type=ArmTableWalker 580clk_domain=system.cpu_clk_domain 581eventq_index=0 582is_stage2=true 583num_squash_per_cycle=2 584sys=system	573tlb=system.cpu.itb 574 575[system.cpu.istage2_mmu.stage2_tlb] 576type=ArmTLB 577children=walker 578eventq_index=0 579is_stage2=true 580size=32 581walker=system.cpu.istage2_mmu.stage2_tlb.walker 582 583[system.cpu.istage2_mmu.stage2_tlb.walker] 584type=ArmTableWalker 585clk_domain=system.cpu_clk_domain 586eventq_index=0 587is_stage2=true 588num_squash_per_cycle=2 589sys=system
585port=system.cpu.toL2Bus.slave[4]
586 587[system.cpu.itb] 588type=ArmTLB 589children=walker 590eventq_index=0 591is_stage2=false 592size=64 593walker=system.cpu.itb.walker 594 595[system.cpu.itb.walker] 596type=ArmTableWalker 597clk_domain=system.cpu_clk_domain 598eventq_index=0 599is_stage2=false 600num_squash_per_cycle=2 601sys=system 602port=system.cpu.toL2Bus.slave[2] 603 604[system.cpu.l2cache] 605type=BaseCache 606children=prefetcher tags 607addr_ranges=0:18446744073709551615 608assoc=16 609clk_domain=system.cpu_clk_domain	590 591[system.cpu.itb] 592type=ArmTLB 593children=walker 594eventq_index=0 595is_stage2=false 596size=64 597walker=system.cpu.itb.walker 598 599[system.cpu.itb.walker] 600type=ArmTableWalker 601clk_domain=system.cpu_clk_domain 602eventq_index=0 603is_stage2=false 604num_squash_per_cycle=2 605sys=system 606port=system.cpu.toL2Bus.slave[2] 607 608[system.cpu.l2cache] 609type=BaseCache 610children=prefetcher tags 611addr_ranges=0:18446744073709551615 612assoc=16 613clk_domain=system.cpu_clk_domain
	614demand_mshr_reserve=1
610eventq_index=0 611forward_snoops=true 612hit_latency=12 613is_top_level=false 614max_miss_count=0 615mshrs=16 616prefetch_on_access=true 617prefetcher=system.cpu.l2cache.prefetcher 618response_latency=12 619sequential_access=false 620size=1048576 621system=system 622tags=system.cpu.l2cache.tags 623tgts_per_mshr=8 624two_queue=false 625write_buffers=8 626cpu_side=system.cpu.toL2Bus.master[0] 627mem_side=system.membus.slave[1] 628 629[system.cpu.l2cache.prefetcher] 630type=StridePrefetcher	615eventq_index=0 616forward_snoops=true 617hit_latency=12 618is_top_level=false 619max_miss_count=0 620mshrs=16 621prefetch_on_access=true 622prefetcher=system.cpu.l2cache.prefetcher 623response_latency=12 624sequential_access=false 625size=1048576 626system=system 627tags=system.cpu.l2cache.tags 628tgts_per_mshr=8 629two_queue=false 630write_buffers=8 631cpu_side=system.cpu.toL2Bus.master[0] 632mem_side=system.membus.slave[1] 633 634[system.cpu.l2cache.prefetcher] 635type=StridePrefetcher
	636cache_snoop=false
631clk_domain=system.cpu_clk_domain	637clk_domain=system.cpu_clk_domain
632cross_pages=false 633data_accesses_only=false
634degree=8 635eventq_index=0	638degree=8 639eventq_index=0
636inst_tagged=true
637latency=1	640latency=1
638on_miss_only=false 639on_prefetch=true 640on_read_only=false 641serial_squash=false 642size=100	641max_conf=7 642min_conf=0 643on_data=true 644on_inst=true 645on_miss=false 646on_read=true 647on_write=true 648queue_filter=true 649queue_size=32 650queue_squash=true 651start_conf=4
643sys=system	652sys=system
	653table_assoc=4 654table_sets=16 655tag_prefetch=true 656thresh_conf=4
644use_master_id=true 645 646[system.cpu.l2cache.tags] 647type=RandomRepl 648assoc=16 649block_size=64 650clk_domain=system.cpu_clk_domain 651eventq_index=0 652hit_latency=12 653sequential_access=false 654size=1048576 655 656[system.cpu.toL2Bus] 657type=CoherentXBar 658clk_domain=system.cpu_clk_domain 659eventq_index=0	657use_master_id=true 658 659[system.cpu.l2cache.tags] 660type=RandomRepl 661assoc=16 662block_size=64 663clk_domain=system.cpu_clk_domain 664eventq_index=0 665hit_latency=12 666sequential_access=false 667size=1048576 668 669[system.cpu.toL2Bus] 670type=CoherentXBar 671clk_domain=system.cpu_clk_domain 672eventq_index=0
660header_cycles=1	673forward_latency=0 674frontend_latency=1 675response_latency=1
661snoop_filter=Null	676snoop_filter=Null
	677snoop_response_latency=1
662system=system 663use_default_range=false 664width=32 665master=system.cpu.l2cache.cpu_side	678system=system 679use_default_range=false 680width=32 681master=system.cpu.l2cache.cpu_side
666slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port	682slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
667 668[system.cpu.tracer] 669type=ExeTracer 670eventq_index=0 671 672[system.cpu.workload] 673type=LiveProcess 674cmd=hello 675cwd=	683 684[system.cpu.tracer] 685type=ExeTracer 686eventq_index=0 687 688[system.cpu.workload] 689type=LiveProcess 690cmd=hello 691cwd=
	692drivers=
676egid=100 677env= 678errout=cerr 679euid=100 680eventq_index=0 681executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 682gid=100 683input=cin	693egid=100 694env= 695errout=cerr 696euid=100 697eventq_index=0 698executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 699gid=100 700input=cin
	701kvmInSE=false
684max_stack_size=67108864 685output=cout 686pid=100 687ppid=99 688simpoint=0 689system=system 690uid=100 691useArchPT=false 692 693[system.cpu_clk_domain] 694type=SrcClockDomain 695clock=500 696domain_id=-1 697eventq_index=0 698init_perf_level=0 699voltage_domain=system.voltage_domain 700 701[system.dvfs_handler] 702type=DVFSHandler 703domains= 704enable=false 705eventq_index=0 706sys_clk_domain=system.clk_domain 707transition_latency=100000000 708 709[system.membus] 710type=CoherentXBar 711clk_domain=system.clk_domain 712eventq_index=0	702max_stack_size=67108864 703output=cout 704pid=100 705ppid=99 706simpoint=0 707system=system 708uid=100 709useArchPT=false 710 711[system.cpu_clk_domain] 712type=SrcClockDomain 713clock=500 714domain_id=-1 715eventq_index=0 716init_perf_level=0 717voltage_domain=system.voltage_domain 718 719[system.dvfs_handler] 720type=DVFSHandler 721domains= 722enable=false 723eventq_index=0 724sys_clk_domain=system.clk_domain 725transition_latency=100000000 726 727[system.membus] 728type=CoherentXBar 729clk_domain=system.clk_domain 730eventq_index=0
713header_cycles=1	731forward_latency=4 732frontend_latency=3 733response_latency=2
714snoop_filter=Null	734snoop_filter=Null
	735snoop_response_latency=4
715system=system 716use_default_range=false	736system=system 737use_default_range=false
717width=8	738width=16
718master=system.physmem.port 719slave=system.system_port system.cpu.l2cache.mem_side 720 721[system.physmem] 722type=DRAMCtrl 723IDD0=0.075000 724IDD02=0.000000 725IDD2N=0.050000 726IDD2N2=0.000000 727IDD2P0=0.000000 728IDD2P02=0.000000 729IDD2P1=0.000000 730IDD2P12=0.000000 731IDD3N=0.057000 732IDD3N2=0.000000 733IDD3P0=0.000000 734IDD3P02=0.000000 735IDD3P1=0.000000 736IDD3P12=0.000000 737IDD4R=0.187000 738IDD4R2=0.000000 739IDD4W=0.165000 740IDD4W2=0.000000 741IDD5=0.220000 742IDD52=0.000000 743IDD6=0.000000 744IDD62=0.000000 745VDD=1.500000 746VDD2=0.000000 747activation_limit=4	739master=system.physmem.port 740slave=system.system_port system.cpu.l2cache.mem_side 741 742[system.physmem] 743type=DRAMCtrl 744IDD0=0.075000 745IDD02=0.000000 746IDD2N=0.050000 747IDD2N2=0.000000 748IDD2P0=0.000000 749IDD2P02=0.000000 750IDD2P1=0.000000 751IDD2P12=0.000000 752IDD3N=0.057000 753IDD3N2=0.000000 754IDD3P0=0.000000 755IDD3P02=0.000000 756IDD3P1=0.000000 757IDD3P12=0.000000 758IDD4R=0.187000 759IDD4R2=0.000000 760IDD4W=0.165000 761IDD4W2=0.000000 762IDD5=0.220000 763IDD52=0.000000 764IDD6=0.000000 765IDD62=0.000000 766VDD=1.500000 767VDD2=0.000000 768activation_limit=4
748addr_mapping=RoRaBaChCo	769addr_mapping=RoRaBaCoCh
749bank_groups_per_rank=0 750banks_per_rank=8 751burst_length=8 752channels=1 753clk_domain=system.clk_domain 754conf_table_reported=true 755device_bus_width=8 756device_rowbuffer_size=1024	770bank_groups_per_rank=0 771banks_per_rank=8 772burst_length=8 773channels=1 774clk_domain=system.clk_domain 775conf_table_reported=true 776device_bus_width=8 777device_rowbuffer_size=1024
	778device_size=536870912
757devices_per_rank=8 758dll=true 759eventq_index=0 760in_addr_map=true 761max_accesses_per_row=16 762mem_sched_policy=frfcfs 763min_writes_per_switch=16 764null=false 765page_policy=open_adaptive 766range=0:134217727 767ranks_per_channel=2 768read_buffer_size=32 769static_backend_latency=10000 770static_frontend_latency=10000 771tBURST=5000 772tCCD_L=0 773tCK=1250 774tCL=13750 775tCS=2500 776tRAS=35000 777tRCD=13750 778tREFI=7800000 779tRFC=260000 780tRP=13750 781tRRD=6000 782tRRD_L=0 783tRTP=7500 784tRTW=2500 785tWR=15000 786tWTR=7500 787tXAW=30000 788tXP=0 789tXPDLL=0 790tXS=0 791tXSDLL=0 792write_buffer_size=64 793write_high_thresh_perc=85 794write_low_thresh_perc=50 795port=system.membus.master[0] 796 797[system.voltage_domain] 798type=VoltageDomain 799eventq_index=0 800voltage=1.000000 801	779devices_per_rank=8 780dll=true 781eventq_index=0 782in_addr_map=true 783max_accesses_per_row=16 784mem_sched_policy=frfcfs 785min_writes_per_switch=16 786null=false 787page_policy=open_adaptive 788range=0:134217727 789ranks_per_channel=2 790read_buffer_size=32 791static_backend_latency=10000 792static_frontend_latency=10000 793tBURST=5000 794tCCD_L=0 795tCK=1250 796tCL=13750 797tCS=2500 798tRAS=35000 799tRCD=13750 800tREFI=7800000 801tRFC=260000 802tRP=13750 803tRRD=6000 804tRRD_L=0 805tRTP=7500 806tRTW=2500 807tWR=15000 808tWTR=7500 809tXAW=30000 810tXP=0 811tXPDLL=0 812tXS=0 813tXSDLL=0 814write_buffer_size=64 815write_high_thresh_perc=85 816write_low_thresh_perc=50 817port=system.membus.master[0] 818 819[system.voltage_domain] 820type=VoltageDomain 821eventq_index=0 822voltage=1.000000 823