Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini

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config.ini (10038:7eccd14e2610)	config.ini (10242:cb4e86c17767)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=DerivO3CPU 45children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52activity=0 53backComSize=5 54branchPred=system.cpu.branchPred 55cachePorts=200 56checker=Null 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dstage2_mmu=system.cpu.dstage2_mmu 72dtb=system.cpu.dtb 73eventq_index=0 74fetchBufferSize=64 75fetchToDecodeDelay=1 76fetchTrapLatency=1 77fetchWidth=8 78forwardComSize=5 79fuPool=system.cpu.fuPool 80function_trace=false 81function_trace_start=0 82iewToCommitDelay=1 83iewToDecodeDelay=1 84iewToFetchDelay=1 85iewToRenameDelay=1 86interrupts=system.cpu.interrupts 87isa=system.cpu.isa 88issueToExecuteDelay=1 89issueWidth=8 90istage2_mmu=system.cpu.istage2_mmu 91itb=system.cpu.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysCCRegs=0 99numPhysFloatRegs=256 100numPhysIntRegs=256 101numROBEntries=192 102numRobs=1 103numThreads=1 104profile=0 105progress_interval=0 106renameToDecodeDelay=1 107renameToFetchDelay=1 108renameToIEWDelay=2 109renameToROBDelay=1 110renameWidth=8 111simpoint_start_insts= 112smtCommitPolicy=RoundRobin 113smtFetchPolicy=SingleThread 114smtIQPolicy=Partitioned 115smtIQThreshold=100 116smtLSQPolicy=Partitioned 117smtLSQThreshold=100 118smtNumFetchingThreads=1 119smtROBPolicy=Partitioned 120smtROBThreshold=100	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=DerivO3CPU 45children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52activity=0 53backComSize=5 54branchPred=system.cpu.branchPred 55cachePorts=200 56checker=Null 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dstage2_mmu=system.cpu.dstage2_mmu 72dtb=system.cpu.dtb 73eventq_index=0 74fetchBufferSize=64 75fetchToDecodeDelay=1 76fetchTrapLatency=1 77fetchWidth=8 78forwardComSize=5 79fuPool=system.cpu.fuPool 80function_trace=false 81function_trace_start=0 82iewToCommitDelay=1 83iewToDecodeDelay=1 84iewToFetchDelay=1 85iewToRenameDelay=1 86interrupts=system.cpu.interrupts 87isa=system.cpu.isa 88issueToExecuteDelay=1 89issueWidth=8 90istage2_mmu=system.cpu.istage2_mmu 91itb=system.cpu.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysCCRegs=0 99numPhysFloatRegs=256 100numPhysIntRegs=256 101numROBEntries=192 102numRobs=1 103numThreads=1 104profile=0 105progress_interval=0 106renameToDecodeDelay=1 107renameToFetchDelay=1 108renameToIEWDelay=2 109renameToROBDelay=1 110renameWidth=8 111simpoint_start_insts= 112smtCommitPolicy=RoundRobin 113smtFetchPolicy=SingleThread 114smtIQPolicy=Partitioned 115smtIQThreshold=100 116smtLSQPolicy=Partitioned 117smtLSQThreshold=100 118smtNumFetchingThreads=1 119smtROBPolicy=Partitioned 120smtROBThreshold=100
	121socket_id=0
121squashWidth=8 122store_set_clear_period=250000 123switched_out=false 124system=system 125tracer=system.cpu.tracer 126trapLatency=13 127wbDepth=1 128wbWidth=8 129workload=system.cpu.workload 130dcache_port=system.cpu.dcache.cpu_side 131icache_port=system.cpu.icache.cpu_side 132 133[system.cpu.branchPred] 134type=BranchPredictor 135BTBEntries=4096 136BTBTagSize=16 137RASSize=16 138choiceCtrBits=2 139choicePredictorSize=8192 140eventq_index=0 141globalCtrBits=2 142globalPredictorSize=8192 143instShiftAmt=2 144localCtrBits=2 145localHistoryTableSize=2048 146localPredictorSize=2048 147numThreads=1 148predType=tournament 149 150[system.cpu.dcache] 151type=BaseCache 152children=tags 153addr_ranges=0:18446744073709551615 154assoc=2 155clk_domain=system.cpu_clk_domain 156eventq_index=0 157forward_snoops=true 158hit_latency=2 159is_top_level=true 160max_miss_count=0 161mshrs=4 162prefetch_on_access=false 163prefetcher=Null 164response_latency=2 165sequential_access=false 166size=262144 167system=system 168tags=system.cpu.dcache.tags 169tgts_per_mshr=20 170two_queue=false 171write_buffers=8 172cpu_side=system.cpu.dcache_port 173mem_side=system.cpu.toL2Bus.slave[1] 174 175[system.cpu.dcache.tags] 176type=LRU 177assoc=2 178block_size=64 179clk_domain=system.cpu_clk_domain 180eventq_index=0 181hit_latency=2 182sequential_access=false 183size=262144 184 185[system.cpu.dstage2_mmu] 186type=ArmStage2MMU 187children=stage2_tlb 188eventq_index=0 189stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 190tlb=system.cpu.dtb 191 192[system.cpu.dstage2_mmu.stage2_tlb] 193type=ArmTLB 194children=walker 195eventq_index=0 196is_stage2=true 197size=32 198walker=system.cpu.dstage2_mmu.stage2_tlb.walker 199 200[system.cpu.dstage2_mmu.stage2_tlb.walker] 201type=ArmTableWalker 202clk_domain=system.cpu_clk_domain 203eventq_index=0 204is_stage2=true 205num_squash_per_cycle=2 206sys=system 207port=system.cpu.toL2Bus.slave[5] 208 209[system.cpu.dtb] 210type=ArmTLB 211children=walker 212eventq_index=0 213is_stage2=false 214size=64 215walker=system.cpu.dtb.walker 216 217[system.cpu.dtb.walker] 218type=ArmTableWalker 219clk_domain=system.cpu_clk_domain 220eventq_index=0 221is_stage2=false 222num_squash_per_cycle=2 223sys=system 224port=system.cpu.toL2Bus.slave[3] 225 226[system.cpu.fuPool] 227type=FUPool 228children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 229FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 230eventq_index=0 231 232[system.cpu.fuPool.FUList0] 233type=FUDesc 234children=opList 235count=6 236eventq_index=0 237opList=system.cpu.fuPool.FUList0.opList 238 239[system.cpu.fuPool.FUList0.opList] 240type=OpDesc 241eventq_index=0 242issueLat=1 243opClass=IntAlu 244opLat=1 245 246[system.cpu.fuPool.FUList1] 247type=FUDesc 248children=opList0 opList1 249count=2 250eventq_index=0 251opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 252 253[system.cpu.fuPool.FUList1.opList0] 254type=OpDesc 255eventq_index=0 256issueLat=1 257opClass=IntMult 258opLat=3 259 260[system.cpu.fuPool.FUList1.opList1] 261type=OpDesc 262eventq_index=0 263issueLat=19 264opClass=IntDiv 265opLat=20 266 267[system.cpu.fuPool.FUList2] 268type=FUDesc 269children=opList0 opList1 opList2 270count=4 271eventq_index=0 272opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 273 274[system.cpu.fuPool.FUList2.opList0] 275type=OpDesc 276eventq_index=0 277issueLat=1 278opClass=FloatAdd 279opLat=2 280 281[system.cpu.fuPool.FUList2.opList1] 282type=OpDesc 283eventq_index=0 284issueLat=1 285opClass=FloatCmp 286opLat=2 287 288[system.cpu.fuPool.FUList2.opList2] 289type=OpDesc 290eventq_index=0 291issueLat=1 292opClass=FloatCvt 293opLat=2 294 295[system.cpu.fuPool.FUList3] 296type=FUDesc 297children=opList0 opList1 opList2 298count=2 299eventq_index=0 300opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 301 302[system.cpu.fuPool.FUList3.opList0] 303type=OpDesc 304eventq_index=0 305issueLat=1 306opClass=FloatMult 307opLat=4 308 309[system.cpu.fuPool.FUList3.opList1] 310type=OpDesc 311eventq_index=0 312issueLat=12 313opClass=FloatDiv 314opLat=12 315 316[system.cpu.fuPool.FUList3.opList2] 317type=OpDesc 318eventq_index=0 319issueLat=24 320opClass=FloatSqrt 321opLat=24 322 323[system.cpu.fuPool.FUList4] 324type=FUDesc 325children=opList 326count=0 327eventq_index=0 328opList=system.cpu.fuPool.FUList4.opList 329 330[system.cpu.fuPool.FUList4.opList] 331type=OpDesc 332eventq_index=0 333issueLat=1 334opClass=MemRead 335opLat=1 336 337[system.cpu.fuPool.FUList5] 338type=FUDesc 339children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 340count=4 341eventq_index=0 342opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 343 344[system.cpu.fuPool.FUList5.opList00] 345type=OpDesc 346eventq_index=0 347issueLat=1 348opClass=SimdAdd 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList01] 352type=OpDesc 353eventq_index=0 354issueLat=1 355opClass=SimdAddAcc 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList02] 359type=OpDesc 360eventq_index=0 361issueLat=1 362opClass=SimdAlu 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList03] 366type=OpDesc 367eventq_index=0 368issueLat=1 369opClass=SimdCmp 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList04] 373type=OpDesc 374eventq_index=0 375issueLat=1 376opClass=SimdCvt 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList05] 380type=OpDesc 381eventq_index=0 382issueLat=1 383opClass=SimdMisc 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList06] 387type=OpDesc 388eventq_index=0 389issueLat=1 390opClass=SimdMult 391opLat=1 392 393[system.cpu.fuPool.FUList5.opList07] 394type=OpDesc 395eventq_index=0 396issueLat=1 397opClass=SimdMultAcc 398opLat=1 399 400[system.cpu.fuPool.FUList5.opList08] 401type=OpDesc 402eventq_index=0 403issueLat=1 404opClass=SimdShift 405opLat=1 406 407[system.cpu.fuPool.FUList5.opList09] 408type=OpDesc 409eventq_index=0 410issueLat=1 411opClass=SimdShiftAcc 412opLat=1 413 414[system.cpu.fuPool.FUList5.opList10] 415type=OpDesc 416eventq_index=0 417issueLat=1 418opClass=SimdSqrt 419opLat=1 420 421[system.cpu.fuPool.FUList5.opList11] 422type=OpDesc 423eventq_index=0 424issueLat=1 425opClass=SimdFloatAdd 426opLat=1 427 428[system.cpu.fuPool.FUList5.opList12] 429type=OpDesc 430eventq_index=0 431issueLat=1 432opClass=SimdFloatAlu 433opLat=1 434 435[system.cpu.fuPool.FUList5.opList13] 436type=OpDesc 437eventq_index=0 438issueLat=1 439opClass=SimdFloatCmp 440opLat=1 441 442[system.cpu.fuPool.FUList5.opList14] 443type=OpDesc 444eventq_index=0 445issueLat=1 446opClass=SimdFloatCvt 447opLat=1 448 449[system.cpu.fuPool.FUList5.opList15] 450type=OpDesc 451eventq_index=0 452issueLat=1 453opClass=SimdFloatDiv 454opLat=1 455 456[system.cpu.fuPool.FUList5.opList16] 457type=OpDesc 458eventq_index=0 459issueLat=1 460opClass=SimdFloatMisc 461opLat=1 462 463[system.cpu.fuPool.FUList5.opList17] 464type=OpDesc 465eventq_index=0 466issueLat=1 467opClass=SimdFloatMult 468opLat=1 469 470[system.cpu.fuPool.FUList5.opList18] 471type=OpDesc 472eventq_index=0 473issueLat=1 474opClass=SimdFloatMultAcc 475opLat=1 476 477[system.cpu.fuPool.FUList5.opList19] 478type=OpDesc 479eventq_index=0 480issueLat=1 481opClass=SimdFloatSqrt 482opLat=1 483 484[system.cpu.fuPool.FUList6] 485type=FUDesc 486children=opList 487count=0 488eventq_index=0 489opList=system.cpu.fuPool.FUList6.opList 490 491[system.cpu.fuPool.FUList6.opList] 492type=OpDesc 493eventq_index=0 494issueLat=1 495opClass=MemWrite 496opLat=1 497 498[system.cpu.fuPool.FUList7] 499type=FUDesc 500children=opList0 opList1 501count=4 502eventq_index=0 503opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 504 505[system.cpu.fuPool.FUList7.opList0] 506type=OpDesc 507eventq_index=0 508issueLat=1 509opClass=MemRead 510opLat=1 511 512[system.cpu.fuPool.FUList7.opList1] 513type=OpDesc 514eventq_index=0 515issueLat=1 516opClass=MemWrite 517opLat=1 518 519[system.cpu.fuPool.FUList8] 520type=FUDesc 521children=opList 522count=1 523eventq_index=0 524opList=system.cpu.fuPool.FUList8.opList 525 526[system.cpu.fuPool.FUList8.opList] 527type=OpDesc 528eventq_index=0 529issueLat=3 530opClass=IprAccess 531opLat=3 532 533[system.cpu.icache] 534type=BaseCache 535children=tags 536addr_ranges=0:18446744073709551615 537assoc=2 538clk_domain=system.cpu_clk_domain 539eventq_index=0 540forward_snoops=true 541hit_latency=2 542is_top_level=true 543max_miss_count=0 544mshrs=4 545prefetch_on_access=false 546prefetcher=Null 547response_latency=2 548sequential_access=false 549size=131072 550system=system 551tags=system.cpu.icache.tags 552tgts_per_mshr=20 553two_queue=false 554write_buffers=8 555cpu_side=system.cpu.icache_port 556mem_side=system.cpu.toL2Bus.slave[0] 557 558[system.cpu.icache.tags] 559type=LRU 560assoc=2 561block_size=64 562clk_domain=system.cpu_clk_domain 563eventq_index=0 564hit_latency=2 565sequential_access=false 566size=131072 567 568[system.cpu.interrupts] 569type=ArmInterrupts 570eventq_index=0 571 572[system.cpu.isa] 573type=ArmISA 574eventq_index=0 575fpsid=1090793632 576id_aa64afr0_el1=0 577id_aa64afr1_el1=0 578id_aa64dfr0_el1=1052678 579id_aa64dfr1_el1=0 580id_aa64isar0_el1=0 581id_aa64isar1_el1=0 582id_aa64mmfr0_el1=15728642 583id_aa64mmfr1_el1=0 584id_aa64pfr0_el1=17 585id_aa64pfr1_el1=0 586id_isar0=34607377 587id_isar1=34677009 588id_isar2=555950401 589id_isar3=17899825 590id_isar4=268501314 591id_isar5=0 592id_mmfr0=270536963 593id_mmfr1=0 594id_mmfr2=19070976 595id_mmfr3=34611729 596id_pfr0=49 597id_pfr1=4113 598midr=1091551472 599system=system 600 601[system.cpu.istage2_mmu] 602type=ArmStage2MMU 603children=stage2_tlb 604eventq_index=0 605stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 606tlb=system.cpu.itb 607 608[system.cpu.istage2_mmu.stage2_tlb] 609type=ArmTLB 610children=walker 611eventq_index=0 612is_stage2=true 613size=32 614walker=system.cpu.istage2_mmu.stage2_tlb.walker 615 616[system.cpu.istage2_mmu.stage2_tlb.walker] 617type=ArmTableWalker 618clk_domain=system.cpu_clk_domain 619eventq_index=0 620is_stage2=true 621num_squash_per_cycle=2 622sys=system 623port=system.cpu.toL2Bus.slave[4] 624 625[system.cpu.itb] 626type=ArmTLB 627children=walker 628eventq_index=0 629is_stage2=false 630size=64 631walker=system.cpu.itb.walker 632 633[system.cpu.itb.walker] 634type=ArmTableWalker 635clk_domain=system.cpu_clk_domain 636eventq_index=0 637is_stage2=false 638num_squash_per_cycle=2 639sys=system 640port=system.cpu.toL2Bus.slave[2] 641 642[system.cpu.l2cache] 643type=BaseCache 644children=tags 645addr_ranges=0:18446744073709551615 646assoc=8 647clk_domain=system.cpu_clk_domain 648eventq_index=0 649forward_snoops=true 650hit_latency=20 651is_top_level=false 652max_miss_count=0 653mshrs=20 654prefetch_on_access=false 655prefetcher=Null 656response_latency=20 657sequential_access=false 658size=2097152 659system=system 660tags=system.cpu.l2cache.tags 661tgts_per_mshr=12 662two_queue=false 663write_buffers=8 664cpu_side=system.cpu.toL2Bus.master[0] 665mem_side=system.membus.slave[1] 666 667[system.cpu.l2cache.tags] 668type=LRU 669assoc=8 670block_size=64 671clk_domain=system.cpu_clk_domain 672eventq_index=0 673hit_latency=20 674sequential_access=false 675size=2097152 676 677[system.cpu.toL2Bus] 678type=CoherentBus 679clk_domain=system.cpu_clk_domain 680eventq_index=0 681header_cycles=1 682system=system 683use_default_range=false 684width=32 685master=system.cpu.l2cache.cpu_side 686slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 687 688[system.cpu.tracer] 689type=ExeTracer 690eventq_index=0 691 692[system.cpu.workload] 693type=LiveProcess 694cmd=hello 695cwd= 696egid=100 697env= 698errout=cerr 699euid=100 700eventq_index=0	122squashWidth=8 123store_set_clear_period=250000 124switched_out=false 125system=system 126tracer=system.cpu.tracer 127trapLatency=13 128wbDepth=1 129wbWidth=8 130workload=system.cpu.workload 131dcache_port=system.cpu.dcache.cpu_side 132icache_port=system.cpu.icache.cpu_side 133 134[system.cpu.branchPred] 135type=BranchPredictor 136BTBEntries=4096 137BTBTagSize=16 138RASSize=16 139choiceCtrBits=2 140choicePredictorSize=8192 141eventq_index=0 142globalCtrBits=2 143globalPredictorSize=8192 144instShiftAmt=2 145localCtrBits=2 146localHistoryTableSize=2048 147localPredictorSize=2048 148numThreads=1 149predType=tournament 150 151[system.cpu.dcache] 152type=BaseCache 153children=tags 154addr_ranges=0:18446744073709551615 155assoc=2 156clk_domain=system.cpu_clk_domain 157eventq_index=0 158forward_snoops=true 159hit_latency=2 160is_top_level=true 161max_miss_count=0 162mshrs=4 163prefetch_on_access=false 164prefetcher=Null 165response_latency=2 166sequential_access=false 167size=262144 168system=system 169tags=system.cpu.dcache.tags 170tgts_per_mshr=20 171two_queue=false 172write_buffers=8 173cpu_side=system.cpu.dcache_port 174mem_side=system.cpu.toL2Bus.slave[1] 175 176[system.cpu.dcache.tags] 177type=LRU 178assoc=2 179block_size=64 180clk_domain=system.cpu_clk_domain 181eventq_index=0 182hit_latency=2 183sequential_access=false 184size=262144 185 186[system.cpu.dstage2_mmu] 187type=ArmStage2MMU 188children=stage2_tlb 189eventq_index=0 190stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 191tlb=system.cpu.dtb 192 193[system.cpu.dstage2_mmu.stage2_tlb] 194type=ArmTLB 195children=walker 196eventq_index=0 197is_stage2=true 198size=32 199walker=system.cpu.dstage2_mmu.stage2_tlb.walker 200 201[system.cpu.dstage2_mmu.stage2_tlb.walker] 202type=ArmTableWalker 203clk_domain=system.cpu_clk_domain 204eventq_index=0 205is_stage2=true 206num_squash_per_cycle=2 207sys=system 208port=system.cpu.toL2Bus.slave[5] 209 210[system.cpu.dtb] 211type=ArmTLB 212children=walker 213eventq_index=0 214is_stage2=false 215size=64 216walker=system.cpu.dtb.walker 217 218[system.cpu.dtb.walker] 219type=ArmTableWalker 220clk_domain=system.cpu_clk_domain 221eventq_index=0 222is_stage2=false 223num_squash_per_cycle=2 224sys=system 225port=system.cpu.toL2Bus.slave[3] 226 227[system.cpu.fuPool] 228type=FUPool 229children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 230FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 231eventq_index=0 232 233[system.cpu.fuPool.FUList0] 234type=FUDesc 235children=opList 236count=6 237eventq_index=0 238opList=system.cpu.fuPool.FUList0.opList 239 240[system.cpu.fuPool.FUList0.opList] 241type=OpDesc 242eventq_index=0 243issueLat=1 244opClass=IntAlu 245opLat=1 246 247[system.cpu.fuPool.FUList1] 248type=FUDesc 249children=opList0 opList1 250count=2 251eventq_index=0 252opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 253 254[system.cpu.fuPool.FUList1.opList0] 255type=OpDesc 256eventq_index=0 257issueLat=1 258opClass=IntMult 259opLat=3 260 261[system.cpu.fuPool.FUList1.opList1] 262type=OpDesc 263eventq_index=0 264issueLat=19 265opClass=IntDiv 266opLat=20 267 268[system.cpu.fuPool.FUList2] 269type=FUDesc 270children=opList0 opList1 opList2 271count=4 272eventq_index=0 273opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 274 275[system.cpu.fuPool.FUList2.opList0] 276type=OpDesc 277eventq_index=0 278issueLat=1 279opClass=FloatAdd 280opLat=2 281 282[system.cpu.fuPool.FUList2.opList1] 283type=OpDesc 284eventq_index=0 285issueLat=1 286opClass=FloatCmp 287opLat=2 288 289[system.cpu.fuPool.FUList2.opList2] 290type=OpDesc 291eventq_index=0 292issueLat=1 293opClass=FloatCvt 294opLat=2 295 296[system.cpu.fuPool.FUList3] 297type=FUDesc 298children=opList0 opList1 opList2 299count=2 300eventq_index=0 301opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 302 303[system.cpu.fuPool.FUList3.opList0] 304type=OpDesc 305eventq_index=0 306issueLat=1 307opClass=FloatMult 308opLat=4 309 310[system.cpu.fuPool.FUList3.opList1] 311type=OpDesc 312eventq_index=0 313issueLat=12 314opClass=FloatDiv 315opLat=12 316 317[system.cpu.fuPool.FUList3.opList2] 318type=OpDesc 319eventq_index=0 320issueLat=24 321opClass=FloatSqrt 322opLat=24 323 324[system.cpu.fuPool.FUList4] 325type=FUDesc 326children=opList 327count=0 328eventq_index=0 329opList=system.cpu.fuPool.FUList4.opList 330 331[system.cpu.fuPool.FUList4.opList] 332type=OpDesc 333eventq_index=0 334issueLat=1 335opClass=MemRead 336opLat=1 337 338[system.cpu.fuPool.FUList5] 339type=FUDesc 340children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 341count=4 342eventq_index=0 343opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 344 345[system.cpu.fuPool.FUList5.opList00] 346type=OpDesc 347eventq_index=0 348issueLat=1 349opClass=SimdAdd 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList01] 353type=OpDesc 354eventq_index=0 355issueLat=1 356opClass=SimdAddAcc 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList02] 360type=OpDesc 361eventq_index=0 362issueLat=1 363opClass=SimdAlu 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList03] 367type=OpDesc 368eventq_index=0 369issueLat=1 370opClass=SimdCmp 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList04] 374type=OpDesc 375eventq_index=0 376issueLat=1 377opClass=SimdCvt 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList05] 381type=OpDesc 382eventq_index=0 383issueLat=1 384opClass=SimdMisc 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList06] 388type=OpDesc 389eventq_index=0 390issueLat=1 391opClass=SimdMult 392opLat=1 393 394[system.cpu.fuPool.FUList5.opList07] 395type=OpDesc 396eventq_index=0 397issueLat=1 398opClass=SimdMultAcc 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList08] 402type=OpDesc 403eventq_index=0 404issueLat=1 405opClass=SimdShift 406opLat=1 407 408[system.cpu.fuPool.FUList5.opList09] 409type=OpDesc 410eventq_index=0 411issueLat=1 412opClass=SimdShiftAcc 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList10] 416type=OpDesc 417eventq_index=0 418issueLat=1 419opClass=SimdSqrt 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList11] 423type=OpDesc 424eventq_index=0 425issueLat=1 426opClass=SimdFloatAdd 427opLat=1 428 429[system.cpu.fuPool.FUList5.opList12] 430type=OpDesc 431eventq_index=0 432issueLat=1 433opClass=SimdFloatAlu 434opLat=1 435 436[system.cpu.fuPool.FUList5.opList13] 437type=OpDesc 438eventq_index=0 439issueLat=1 440opClass=SimdFloatCmp 441opLat=1 442 443[system.cpu.fuPool.FUList5.opList14] 444type=OpDesc 445eventq_index=0 446issueLat=1 447opClass=SimdFloatCvt 448opLat=1 449 450[system.cpu.fuPool.FUList5.opList15] 451type=OpDesc 452eventq_index=0 453issueLat=1 454opClass=SimdFloatDiv 455opLat=1 456 457[system.cpu.fuPool.FUList5.opList16] 458type=OpDesc 459eventq_index=0 460issueLat=1 461opClass=SimdFloatMisc 462opLat=1 463 464[system.cpu.fuPool.FUList5.opList17] 465type=OpDesc 466eventq_index=0 467issueLat=1 468opClass=SimdFloatMult 469opLat=1 470 471[system.cpu.fuPool.FUList5.opList18] 472type=OpDesc 473eventq_index=0 474issueLat=1 475opClass=SimdFloatMultAcc 476opLat=1 477 478[system.cpu.fuPool.FUList5.opList19] 479type=OpDesc 480eventq_index=0 481issueLat=1 482opClass=SimdFloatSqrt 483opLat=1 484 485[system.cpu.fuPool.FUList6] 486type=FUDesc 487children=opList 488count=0 489eventq_index=0 490opList=system.cpu.fuPool.FUList6.opList 491 492[system.cpu.fuPool.FUList6.opList] 493type=OpDesc 494eventq_index=0 495issueLat=1 496opClass=MemWrite 497opLat=1 498 499[system.cpu.fuPool.FUList7] 500type=FUDesc 501children=opList0 opList1 502count=4 503eventq_index=0 504opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 505 506[system.cpu.fuPool.FUList7.opList0] 507type=OpDesc 508eventq_index=0 509issueLat=1 510opClass=MemRead 511opLat=1 512 513[system.cpu.fuPool.FUList7.opList1] 514type=OpDesc 515eventq_index=0 516issueLat=1 517opClass=MemWrite 518opLat=1 519 520[system.cpu.fuPool.FUList8] 521type=FUDesc 522children=opList 523count=1 524eventq_index=0 525opList=system.cpu.fuPool.FUList8.opList 526 527[system.cpu.fuPool.FUList8.opList] 528type=OpDesc 529eventq_index=0 530issueLat=3 531opClass=IprAccess 532opLat=3 533 534[system.cpu.icache] 535type=BaseCache 536children=tags 537addr_ranges=0:18446744073709551615 538assoc=2 539clk_domain=system.cpu_clk_domain 540eventq_index=0 541forward_snoops=true 542hit_latency=2 543is_top_level=true 544max_miss_count=0 545mshrs=4 546prefetch_on_access=false 547prefetcher=Null 548response_latency=2 549sequential_access=false 550size=131072 551system=system 552tags=system.cpu.icache.tags 553tgts_per_mshr=20 554two_queue=false 555write_buffers=8 556cpu_side=system.cpu.icache_port 557mem_side=system.cpu.toL2Bus.slave[0] 558 559[system.cpu.icache.tags] 560type=LRU 561assoc=2 562block_size=64 563clk_domain=system.cpu_clk_domain 564eventq_index=0 565hit_latency=2 566sequential_access=false 567size=131072 568 569[system.cpu.interrupts] 570type=ArmInterrupts 571eventq_index=0 572 573[system.cpu.isa] 574type=ArmISA 575eventq_index=0 576fpsid=1090793632 577id_aa64afr0_el1=0 578id_aa64afr1_el1=0 579id_aa64dfr0_el1=1052678 580id_aa64dfr1_el1=0 581id_aa64isar0_el1=0 582id_aa64isar1_el1=0 583id_aa64mmfr0_el1=15728642 584id_aa64mmfr1_el1=0 585id_aa64pfr0_el1=17 586id_aa64pfr1_el1=0 587id_isar0=34607377 588id_isar1=34677009 589id_isar2=555950401 590id_isar3=17899825 591id_isar4=268501314 592id_isar5=0 593id_mmfr0=270536963 594id_mmfr1=0 595id_mmfr2=19070976 596id_mmfr3=34611729 597id_pfr0=49 598id_pfr1=4113 599midr=1091551472 600system=system 601 602[system.cpu.istage2_mmu] 603type=ArmStage2MMU 604children=stage2_tlb 605eventq_index=0 606stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 607tlb=system.cpu.itb 608 609[system.cpu.istage2_mmu.stage2_tlb] 610type=ArmTLB 611children=walker 612eventq_index=0 613is_stage2=true 614size=32 615walker=system.cpu.istage2_mmu.stage2_tlb.walker 616 617[system.cpu.istage2_mmu.stage2_tlb.walker] 618type=ArmTableWalker 619clk_domain=system.cpu_clk_domain 620eventq_index=0 621is_stage2=true 622num_squash_per_cycle=2 623sys=system 624port=system.cpu.toL2Bus.slave[4] 625 626[system.cpu.itb] 627type=ArmTLB 628children=walker 629eventq_index=0 630is_stage2=false 631size=64 632walker=system.cpu.itb.walker 633 634[system.cpu.itb.walker] 635type=ArmTableWalker 636clk_domain=system.cpu_clk_domain 637eventq_index=0 638is_stage2=false 639num_squash_per_cycle=2 640sys=system 641port=system.cpu.toL2Bus.slave[2] 642 643[system.cpu.l2cache] 644type=BaseCache 645children=tags 646addr_ranges=0:18446744073709551615 647assoc=8 648clk_domain=system.cpu_clk_domain 649eventq_index=0 650forward_snoops=true 651hit_latency=20 652is_top_level=false 653max_miss_count=0 654mshrs=20 655prefetch_on_access=false 656prefetcher=Null 657response_latency=20 658sequential_access=false 659size=2097152 660system=system 661tags=system.cpu.l2cache.tags 662tgts_per_mshr=12 663two_queue=false 664write_buffers=8 665cpu_side=system.cpu.toL2Bus.master[0] 666mem_side=system.membus.slave[1] 667 668[system.cpu.l2cache.tags] 669type=LRU 670assoc=8 671block_size=64 672clk_domain=system.cpu_clk_domain 673eventq_index=0 674hit_latency=20 675sequential_access=false 676size=2097152 677 678[system.cpu.toL2Bus] 679type=CoherentBus 680clk_domain=system.cpu_clk_domain 681eventq_index=0 682header_cycles=1 683system=system 684use_default_range=false 685width=32 686master=system.cpu.l2cache.cpu_side 687slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 688 689[system.cpu.tracer] 690type=ExeTracer 691eventq_index=0 692 693[system.cpu.workload] 694type=LiveProcess 695cmd=hello 696cwd= 697egid=100 698env= 699errout=cerr 700euid=100 701eventq_index=0
701executable=/dist/test-progs/hello/bin/arm/linux/hello	702executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
702gid=100 703input=cin 704max_stack_size=67108864 705output=cout 706pid=100 707ppid=99 708simpoint=0 709system=system 710uid=100 711 712[system.cpu_clk_domain] 713type=SrcClockDomain 714clock=500 715eventq_index=0 716voltage_domain=system.voltage_domain 717 718[system.membus] 719type=CoherentBus 720clk_domain=system.clk_domain 721eventq_index=0 722header_cycles=1 723system=system 724use_default_range=false 725width=8 726master=system.physmem.port 727slave=system.system_port system.cpu.l2cache.mem_side 728 729[system.physmem]	703gid=100 704input=cin 705max_stack_size=67108864 706output=cout 707pid=100 708ppid=99 709simpoint=0 710system=system 711uid=100 712 713[system.cpu_clk_domain] 714type=SrcClockDomain 715clock=500 716eventq_index=0 717voltage_domain=system.voltage_domain 718 719[system.membus] 720type=CoherentBus 721clk_domain=system.clk_domain 722eventq_index=0 723header_cycles=1 724system=system 725use_default_range=false 726width=8 727master=system.physmem.port 728slave=system.system_port system.cpu.l2cache.mem_side 729 730[system.physmem]
730type=SimpleDRAM	731type=DRAMCtrl
731activation_limit=4	732activation_limit=4
732addr_mapping=RaBaChCo	733addr_mapping=RoRaBaChCo
733banks_per_rank=8 734burst_length=8 735channels=1 736clk_domain=system.clk_domain 737conf_table_reported=true 738device_bus_width=8 739device_rowbuffer_size=1024 740devices_per_rank=8 741eventq_index=0 742in_addr_map=true	734banks_per_rank=8 735burst_length=8 736channels=1 737clk_domain=system.clk_domain 738conf_table_reported=true 739device_bus_width=8 740device_rowbuffer_size=1024 741devices_per_rank=8 742eventq_index=0 743in_addr_map=true
	744max_accesses_per_row=16
743mem_sched_policy=frfcfs	745mem_sched_policy=frfcfs
	746min_writes_per_switch=16
744null=false	747null=false
745page_policy=open	748page_policy=open_adaptive
746range=0:134217727 747ranks_per_channel=2 748read_buffer_size=32 749static_backend_latency=10000 750static_frontend_latency=10000 751tBURST=5000	749range=0:134217727 750ranks_per_channel=2 751read_buffer_size=32 752static_backend_latency=10000 753static_frontend_latency=10000 754tBURST=5000
	755tCK=1250
752tCL=13750 753tRAS=35000 754tRCD=13750 755tREFI=7800000	756tCL=13750 757tRAS=35000 758tRCD=13750 759tREFI=7800000
756tRFC=300000	760tRFC=260000
757tRP=13750	761tRP=13750
758tRRD=6250	762tRRD=6000 763tRTP=7500 764tRTW=2500 765tWR=15000
759tWTR=7500	766tWTR=7500
760tXAW=40000 761write_buffer_size=32 762write_high_thresh_perc=70 763write_low_thresh_perc=0	767tXAW=30000 768write_buffer_size=64 769write_high_thresh_perc=85 770write_low_thresh_perc=50
764port=system.membus.master[0] 765 766[system.voltage_domain] 767type=VoltageDomain 768eventq_index=0 769voltage=1.000000 770	771port=system.membus.master[0] 772 773[system.voltage_domain] 774type=VoltageDomain 775eventq_index=0 776voltage=1.000000 777