1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 162 unchanged lines hidden (view full) ---
171
172[system.cpu.dcache]
173type=Cache
174children=tags
175addr_ranges=0:18446744073709551615:0:0:0:0
176assoc=2
177clk_domain=system.cpu_clk_domain
178clusivity=mostly_incl
179default_p_state=UNDEFINED
180demand_mshr_reserve=1
181eventq_index=0
182hit_latency=2
183is_read_only=false
184max_miss_count=0
185mshrs=6
186p_state_clk_gate_bins=20
187p_state_clk_gate_max=1000000000000
188p_state_clk_gate_min=1000
189power_model=Null
190prefetch_on_access=false
191prefetcher=Null
192response_latency=2
193sequential_access=false
194size=32768
195system=system
196tags=system.cpu.dcache.tags
197tgts_per_mshr=8
198write_buffers=16
199writeback_clean=true
200cpu_side=system.cpu.dcache_port
201mem_side=system.cpu.toL2Bus.slave[1]
202
203[system.cpu.dcache.tags]
204type=LRU
205assoc=2
206block_size=64
207clk_domain=system.cpu_clk_domain
208default_p_state=UNDEFINED
209eventq_index=0
210hit_latency=2
211p_state_clk_gate_bins=20
212p_state_clk_gate_max=1000000000000
213p_state_clk_gate_min=1000
214power_model=Null
215sequential_access=false
216size=32768
217
218[system.cpu.dstage2_mmu]
219type=ArmStage2MMU
220children=stage2_tlb
221eventq_index=0
222stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
223sys=system
224tlb=system.cpu.dtb
--- 86 unchanged lines hidden (view full) ---
311type=OpDesc
312eventq_index=0
313opClass=IprAccess
314opLat=3
315pipelined=true
316
317[system.cpu.fuPool.FUList2]
318type=FUDesc
319children=opList
320count=1
321eventq_index=0
322opList=system.cpu.fuPool.FUList2.opList
323
324[system.cpu.fuPool.FUList2.opList]
325type=OpDesc
326eventq_index=0
327opClass=MemRead
328opLat=2
329pipelined=true
330
331[system.cpu.fuPool.FUList3]
332type=FUDesc
333children=opList
334count=1
335eventq_index=0
336opList=system.cpu.fuPool.FUList3.opList
337
338[system.cpu.fuPool.FUList3.opList]
339type=OpDesc
340eventq_index=0
341opClass=MemWrite
342opLat=2
343pipelined=true
344
345[system.cpu.fuPool.FUList4]
346type=FUDesc
347children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
348count=2
349eventq_index=0
350opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
351
352[system.cpu.fuPool.FUList4.opList00]
353type=OpDesc
354eventq_index=0
355opClass=SimdAdd
356opLat=4
357pipelined=true
358
--- 115 unchanged lines hidden (view full) ---
474opClass=SimdFloatMult
475opLat=3
476pipelined=true
477
478[system.cpu.fuPool.FUList4.opList18]
479type=OpDesc
480eventq_index=0
481opClass=SimdFloatMultAcc
482opLat=1
483pipelined=true
484
485[system.cpu.fuPool.FUList4.opList19]
486type=OpDesc
487eventq_index=0
488opClass=SimdFloatSqrt
489opLat=9
490pipelined=true
--- 35 unchanged lines hidden (view full) ---
526
527[system.cpu.fuPool.FUList4.opList25]
528type=OpDesc
529eventq_index=0
530opClass=FloatMult
531opLat=4
532pipelined=true
533
534[system.cpu.icache]
535type=Cache
536children=tags
537addr_ranges=0:18446744073709551615:0:0:0:0
538assoc=2
539clk_domain=system.cpu_clk_domain
540clusivity=mostly_incl
541default_p_state=UNDEFINED
542demand_mshr_reserve=1
543eventq_index=0
544hit_latency=1
545is_read_only=true
546max_miss_count=0
547mshrs=2
548p_state_clk_gate_bins=20
549p_state_clk_gate_max=1000000000000
550p_state_clk_gate_min=1000
551power_model=Null
552prefetch_on_access=false
553prefetcher=Null
554response_latency=1
555sequential_access=false
556size=32768
557system=system
558tags=system.cpu.icache.tags
559tgts_per_mshr=8
560write_buffers=8
561writeback_clean=true
562cpu_side=system.cpu.icache_port
563mem_side=system.cpu.toL2Bus.slave[0]
564
565[system.cpu.icache.tags]
566type=LRU
567assoc=2
568block_size=64
569clk_domain=system.cpu_clk_domain
570default_p_state=UNDEFINED
571eventq_index=0
572hit_latency=1
573p_state_clk_gate_bins=20
574p_state_clk_gate_max=1000000000000
575p_state_clk_gate_min=1000
576power_model=Null
577sequential_access=false
578size=32768
579
580[system.cpu.interrupts]
581type=ArmInterrupts
582eventq_index=0
583
584[system.cpu.isa]
585type=ArmISA
586decoderFlavour=Generic
--- 78 unchanged lines hidden (view full) ---
665
666[system.cpu.l2cache]
667type=Cache
668children=prefetcher tags
669addr_ranges=0:18446744073709551615:0:0:0:0
670assoc=16
671clk_domain=system.cpu_clk_domain
672clusivity=mostly_excl
673default_p_state=UNDEFINED
674demand_mshr_reserve=1
675eventq_index=0
676hit_latency=12
677is_read_only=false
678max_miss_count=0
679mshrs=16
680p_state_clk_gate_bins=20
681p_state_clk_gate_max=1000000000000
682p_state_clk_gate_min=1000
683power_model=Null
684prefetch_on_access=true
685prefetcher=system.cpu.l2cache.prefetcher
686response_latency=12
687sequential_access=false
688size=1048576
689system=system
690tags=system.cpu.l2cache.tags
691tgts_per_mshr=8
692write_buffers=8
693writeback_clean=false
694cpu_side=system.cpu.toL2Bus.master[0]
695mem_side=system.membus.slave[1]
696
697[system.cpu.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
724thresh_conf=4
725use_master_id=true
726
727[system.cpu.l2cache.tags]
728type=RandomRepl
729assoc=16
730block_size=64
731clk_domain=system.cpu_clk_domain
732default_p_state=UNDEFINED
733eventq_index=0
734hit_latency=12
735p_state_clk_gate_bins=20
736p_state_clk_gate_max=1000000000000
737p_state_clk_gate_min=1000
738power_model=Null
739sequential_access=false
740size=1048576
741
742[system.cpu.toL2Bus]
743type=CoherentXBar
744children=snoop_filter
745clk_domain=system.cpu_clk_domain
746default_p_state=UNDEFINED
747eventq_index=0
748forward_latency=0
--- 28 unchanged lines hidden (view full) ---
777cmd=hello
778cwd=
779drivers=
780egid=100
781env=
782errout=cerr
783euid=100
784eventq_index=0
785executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
786gid=100
787input=cin
788kvmInSE=false
789max_stack_size=67108864
790output=cout
791pid=100
792ppid=99
793simpoint=0
--- 137 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 162 unchanged lines hidden (view full) ---
171
172[system.cpu.dcache]
173type=Cache
174children=tags
175addr_ranges=0:18446744073709551615:0:0:0:0
176assoc=2
177clk_domain=system.cpu_clk_domain
178clusivity=mostly_incl
179default_p_state=UNDEFINED
180demand_mshr_reserve=1
181eventq_index=0
182hit_latency=2
183is_read_only=false
184max_miss_count=0
185mshrs=6
186p_state_clk_gate_bins=20
187p_state_clk_gate_max=1000000000000
188p_state_clk_gate_min=1000
189power_model=Null
190prefetch_on_access=false
191prefetcher=Null
192response_latency=2
193sequential_access=false
194size=32768
195system=system
196tags=system.cpu.dcache.tags
197tgts_per_mshr=8
198write_buffers=16
199writeback_clean=true
200cpu_side=system.cpu.dcache_port
201mem_side=system.cpu.toL2Bus.slave[1]
202
203[system.cpu.dcache.tags]
204type=LRU
205assoc=2
206block_size=64
207clk_domain=system.cpu_clk_domain
208default_p_state=UNDEFINED
209eventq_index=0
210hit_latency=2
211p_state_clk_gate_bins=20
212p_state_clk_gate_max=1000000000000
213p_state_clk_gate_min=1000
214power_model=Null
215sequential_access=false
216size=32768
217
218[system.cpu.dstage2_mmu]
219type=ArmStage2MMU
220children=stage2_tlb
221eventq_index=0
222stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
223sys=system
224tlb=system.cpu.dtb
--- 86 unchanged lines hidden (view full) ---
311type=OpDesc
312eventq_index=0
313opClass=IprAccess
314opLat=3
315pipelined=true
316
317[system.cpu.fuPool.FUList2]
318type=FUDesc
319children=opList
320count=1
321eventq_index=0
322opList=system.cpu.fuPool.FUList2.opList
323
324[system.cpu.fuPool.FUList2.opList]
325type=OpDesc
326eventq_index=0
327opClass=MemRead
328opLat=2
329pipelined=true
330
331[system.cpu.fuPool.FUList3]
332type=FUDesc
333children=opList
334count=1
335eventq_index=0
336opList=system.cpu.fuPool.FUList3.opList
337
338[system.cpu.fuPool.FUList3.opList]
339type=OpDesc
340eventq_index=0
341opClass=MemWrite
342opLat=2
343pipelined=true
344
345[system.cpu.fuPool.FUList4]
346type=FUDesc
347children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
348count=2
349eventq_index=0
350opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
351
352[system.cpu.fuPool.FUList4.opList00]
353type=OpDesc
354eventq_index=0
355opClass=SimdAdd
356opLat=4
357pipelined=true
358
--- 115 unchanged lines hidden (view full) ---
474opClass=SimdFloatMult
475opLat=3
476pipelined=true
477
478[system.cpu.fuPool.FUList4.opList18]
479type=OpDesc
480eventq_index=0
481opClass=SimdFloatMultAcc
482opLat=1
483pipelined=true
484
485[system.cpu.fuPool.FUList4.opList19]
486type=OpDesc
487eventq_index=0
488opClass=SimdFloatSqrt
489opLat=9
490pipelined=true
--- 35 unchanged lines hidden (view full) ---
526
527[system.cpu.fuPool.FUList4.opList25]
528type=OpDesc
529eventq_index=0
530opClass=FloatMult
531opLat=4
532pipelined=true
533
534[system.cpu.icache]
535type=Cache
536children=tags
537addr_ranges=0:18446744073709551615:0:0:0:0
538assoc=2
539clk_domain=system.cpu_clk_domain
540clusivity=mostly_incl
541default_p_state=UNDEFINED
542demand_mshr_reserve=1
543eventq_index=0
544hit_latency=1
545is_read_only=true
546max_miss_count=0
547mshrs=2
548p_state_clk_gate_bins=20
549p_state_clk_gate_max=1000000000000
550p_state_clk_gate_min=1000
551power_model=Null
552prefetch_on_access=false
553prefetcher=Null
554response_latency=1
555sequential_access=false
556size=32768
557system=system
558tags=system.cpu.icache.tags
559tgts_per_mshr=8
560write_buffers=8
561writeback_clean=true
562cpu_side=system.cpu.icache_port
563mem_side=system.cpu.toL2Bus.slave[0]
564
565[system.cpu.icache.tags]
566type=LRU
567assoc=2
568block_size=64
569clk_domain=system.cpu_clk_domain
570default_p_state=UNDEFINED
571eventq_index=0
572hit_latency=1
573p_state_clk_gate_bins=20
574p_state_clk_gate_max=1000000000000
575p_state_clk_gate_min=1000
576power_model=Null
577sequential_access=false
578size=32768
579
580[system.cpu.interrupts]
581type=ArmInterrupts
582eventq_index=0
583
584[system.cpu.isa]
585type=ArmISA
586decoderFlavour=Generic
--- 78 unchanged lines hidden (view full) ---
665
666[system.cpu.l2cache]
667type=Cache
668children=prefetcher tags
669addr_ranges=0:18446744073709551615:0:0:0:0
670assoc=16
671clk_domain=system.cpu_clk_domain
672clusivity=mostly_excl
673default_p_state=UNDEFINED
674demand_mshr_reserve=1
675eventq_index=0
676hit_latency=12
677is_read_only=false
678max_miss_count=0
679mshrs=16
680p_state_clk_gate_bins=20
681p_state_clk_gate_max=1000000000000
682p_state_clk_gate_min=1000
683power_model=Null
684prefetch_on_access=true
685prefetcher=system.cpu.l2cache.prefetcher
686response_latency=12
687sequential_access=false
688size=1048576
689system=system
690tags=system.cpu.l2cache.tags
691tgts_per_mshr=8
692write_buffers=8
693writeback_clean=false
694cpu_side=system.cpu.toL2Bus.master[0]
695mem_side=system.membus.slave[1]
696
697[system.cpu.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
724thresh_conf=4
725use_master_id=true
726
727[system.cpu.l2cache.tags]
728type=RandomRepl
729assoc=16
730block_size=64
731clk_domain=system.cpu_clk_domain
732default_p_state=UNDEFINED
733eventq_index=0
734hit_latency=12
735p_state_clk_gate_bins=20
736p_state_clk_gate_max=1000000000000
737p_state_clk_gate_min=1000
738power_model=Null
739sequential_access=false
740size=1048576
741
742[system.cpu.toL2Bus]
743type=CoherentXBar
744children=snoop_filter
745clk_domain=system.cpu_clk_domain
746default_p_state=UNDEFINED
747eventq_index=0
748forward_latency=0
--- 28 unchanged lines hidden (view full) ---
777cmd=hello
778cwd=
779drivers=
780egid=100
781env=
782errout=cerr
783euid=100
784eventq_index=0
785executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
786gid=100
787input=cin
788kvmInSE=false
789max_stack_size=67108864
790output=cout
791pid=100
792ppid=99
793simpoint=0
--- 137 unchanged lines hidden ---