stats.txt (9481:b0fa6b872f40) stats.txt (9490:e6a09d97bdc9)
1
2---------- Begin Simulation Statistics ----------
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000013 # Number of seconds simulated
4sim_ticks 13354000 # Number of ticks simulated
5final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
3sim_seconds 0.000014 # Number of seconds simulated
4sim_ticks 13709000 # Number of ticks simulated
5final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 22763 # Simulator instruction rate (inst/s)
8host_op_rate 28403 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 66199618 # Simulator tick rate (ticks/s)
10host_mem_usage 285296 # Number of bytes of host memory used
11host_seconds 0.20 # Real time elapsed on the host
7host_inst_rate 51480 # Simulator instruction rate (inst/s)
8host_op_rate 64222 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 153638426 # Simulator tick rate (ticks/s)
10host_mem_usage 239936 # Number of bytes of host memory used
11host_seconds 0.09 # Real time elapsed on the host
12sim_insts 4591 # Number of instructions simulated
13sim_ops 5729 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
12sim_insts 4591 # Number of instructions simulated
13sim_ops 5729 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s)
22system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 394 # Total number of read requests seen
31system.physmem.writeReqs 0 # Total number of write requests seen
32system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 25216 # Total number of bytes read from memory
34system.physmem.bytesWritten 0 # Total number of bytes written to memory
35system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize()
36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
30system.physmem.readReqs 394 # Total number of read requests seen
31system.physmem.writeReqs 0 # Total number of write requests seen
32system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 25216 # Total number of bytes read from memory
34system.physmem.bytesWritten 0 # Total number of bytes written to memory
35system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize()
36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
39system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis
55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73system.physmem.totGap 13296500 # Total gap between requests
73system.physmem.totGap 13651500 # Total gap between requests
74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 394 # Categorize read packet sizes
81system.physmem.readPktSize::7 0 # Categorize read packet sizes

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93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 394 # Categorize read packet sizes
81system.physmem.readPktSize::7 0 # Categorize read packet sizes

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93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
101system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see

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159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see

--- 45 unchanged lines hidden (view full) ---

159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
167system.physmem.totQLat 2460894 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests
169system.physmem.totBusLat 1576000 # Total cycles spent in databus access
170system.physmem.totBankLat 6524000 # Total cycles spent in bank access
171system.physmem.avgQLat 6245.92 # Average queueing delay per request
172system.physmem.avgBankLat 16558.38 # Average bank access latency per request
173system.physmem.avgBusLat 4000.00 # Average bus latency per request
174system.physmem.avgMemAccLat 26804.30 # Average memory access latency
175system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s
167system.physmem.totQLat 2508144 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests
169system.physmem.totBusLat 1970000 # Total cycles spent in databus access
170system.physmem.totBankLat 7273750 # Total cycles spent in bank access
171system.physmem.avgQLat 6365.85 # Average queueing delay per request
172system.physmem.avgBankLat 18461.29 # Average bank access latency per request
173system.physmem.avgBusLat 5000.00 # Average bus latency per request
174system.physmem.avgMemAccLat 29827.14 # Average memory access latency
175system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
177system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s
177system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
180system.physmem.busUtil 11.80 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.79 # Average read queue length over time
179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
180system.physmem.busUtil 14.37 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.86 # Average read queue length over time
182system.physmem.avgWrQLen 0.00 # Average write queue length over time
182system.physmem.avgWrQLen 0.00 # Average write queue length over time
183system.physmem.readRowHits 319 # Number of row buffer hits during reads
183system.physmem.readRowHits 294 # Number of row buffer hits during reads
184system.physmem.writeRowHits 0 # Number of row buffer hits during writes
184system.physmem.writeRowHits 0 # Number of row buffer hits during writes
185system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
185system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads
186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
187system.physmem.avgGap 33747.46 # Average gap between requests
187system.physmem.avgGap 34648.48 # Average gap between requests
188system.cpu.branchPred.lookups 2501 # Number of BP lookups
189system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
190system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
191system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
192system.cpu.branchPred.BTBHits 702 # Number of BTB hits
193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
194system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage
195system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.

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277system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
278system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
279system.cpu.itb.read_accesses 0 # DTB read accesses
280system.cpu.itb.write_accesses 0 # DTB write accesses
281system.cpu.itb.inst_accesses 0 # ITB inst accesses
282system.cpu.itb.hits 0 # DTB hits
283system.cpu.itb.misses 0 # DTB misses
284system.cpu.itb.accesses 0 # DTB accesses
188system.cpu.branchPred.lookups 2501 # Number of BP lookups
189system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
190system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
191system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
192system.cpu.branchPred.BTBHits 702 # Number of BTB hits
193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
194system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage
195system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.

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277system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
278system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
279system.cpu.itb.read_accesses 0 # DTB read accesses
280system.cpu.itb.write_accesses 0 # DTB write accesses
281system.cpu.itb.inst_accesses 0 # ITB inst accesses
282system.cpu.itb.hits 0 # DTB hits
283system.cpu.itb.misses 0 # DTB misses
284system.cpu.itb.accesses 0 # DTB accesses
285system.cpu.numCycles 26709 # number of cpu cycles simulated
285system.cpu.numCycles 27419 # number of cpu cycles simulated
286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
288system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss
288system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss
289system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
290system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
291system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken
292system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked
293system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing
289system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
290system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
291system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken
292system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked
293system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing
294system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked
294system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked
295system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched
295system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched
296system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
297system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total)
298system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total)
299system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
297system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total)
298system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total)
299system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total)
300system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
300system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
301system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total)
302system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total)
303system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total)
304system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total)
305system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total)
306system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total)
307system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total)
308system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total)
309system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total)
301system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total)
302system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total)
303system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total)
304system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total)
305system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total)
306system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total)
307system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total)
308system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total)
309system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total)
310system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
311system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
312system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
310system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
311system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
312system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
313system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total)
314system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle
315system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle
316system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle
317system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked
318system.cpu.decode.RunCycles 2444 # Number of cycles decode is running
313system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total)
314system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle
315system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle
316system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle
317system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked
318system.cpu.decode.RunCycles 2445 # Number of cycles decode is running
319system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
320system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
321system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch
322system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
319system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
320system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
321system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch
322system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
323system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode
323system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode
324system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
325system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
324system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
325system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
326system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle
326system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle
327system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
327system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
328system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst
328system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst
329system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
330system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
331system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename
332system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
333system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
334system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
335system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed
336system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made

--- 5 unchanged lines hidden (view full) ---

342system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
343system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer
344system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit.
345system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
346system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
347system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
348system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec)
349system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
329system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
330system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
331system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename
332system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
333system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
334system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
335system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed
336system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made

--- 5 unchanged lines hidden (view full) ---

342system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
343system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer
344system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit.
345system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
346system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
347system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
348system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec)
349system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
350system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued
350system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued
351system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
352system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling
353system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph
354system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
351system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
352system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling
353system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph
354system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
355system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle
356system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle
357system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle
355system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle
356system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle
357system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle
358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
359system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle
360system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle
361system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle
362system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle
363system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle
364system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle
365system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle
366system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle
359system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle
360system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle
361system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle
362system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle
363system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle
364system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle
365system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle
366system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle
367system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
368system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
369system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
370system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
367system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
368system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
369system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
370system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
371system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle
371system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle
372system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
373system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
374system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
375system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
376system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
377system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
378system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
379system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available

--- 19 unchanged lines hidden (view full) ---

399system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
400system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
401system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
402system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available
403system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available
404system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
405system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
406system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
372system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
373system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
374system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
375system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
376system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
377system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
378system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
379system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available

--- 19 unchanged lines hidden (view full) ---

399system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
400system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
401system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
402system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available
403system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available
404system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
405system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
406system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
407system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued
408system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued
409system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
410system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
411system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
412system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
413system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
414system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
415system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
418system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued
419system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
420system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued
421system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued
422system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
423system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
424system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued
425system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued
426system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
427system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
428system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
429system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
430system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
431system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
432system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued
433system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued
434system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued
435system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued
436system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued
407system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued
408system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued
409system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued
410system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued
411system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued
412system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued
413system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued
414system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued
415system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued
418system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued
419system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued
420system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued
421system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued
422system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued
423system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued
424system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued
425system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued
426system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued
427system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued
428system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued
429system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued
430system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued
431system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued
432system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued
433system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued
434system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued
435system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued
436system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued
437system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued
438system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
439system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
437system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued
438system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
439system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
440system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
441system.cpu.iq.rate 0.336516 # Inst issue rate
440system.cpu.iq.FU_type_0::total 8986 # Type of FU issued
441system.cpu.iq.rate 0.327729 # Inst issue rate
442system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
442system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
443system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
444system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads
443system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst)
444system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads
445system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes
445system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes
446system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses
446system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses
447system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
448system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
449system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
447system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
448system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
449system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
450system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses
450system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses
451system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
452system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
453system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
454system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed
455system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
456system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations
457system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed
458system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address

--- 11 unchanged lines hidden (view full) ---

470system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
471system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
472system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
473system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
474system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly
475system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly
476system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
477system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions
451system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
452system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
453system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
454system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed
455system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
456system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations
457system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed
458system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address

--- 11 unchanged lines hidden (view full) ---

470system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
471system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
472system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
473system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
474system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly
475system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly
476system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
477system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions
478system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
479system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute
478system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed
479system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute
480system.cpu.iew.exec_swp 0 # number of swp insts executed
481system.cpu.iew.exec_nop 0 # number of nop insts executed
480system.cpu.iew.exec_swp 0 # number of swp insts executed
481system.cpu.iew.exec_nop 0 # number of nop insts executed
482system.cpu.iew.exec_refs 3303 # number of memory reference insts executed
483system.cpu.iew.exec_branches 1443 # Number of branches executed
482system.cpu.iew.exec_refs 3302 # number of memory reference insts executed
483system.cpu.iew.exec_branches 1444 # Number of branches executed
484system.cpu.iew.exec_stores 1167 # Number of stores executed
484system.cpu.iew.exec_stores 1167 # Number of stores executed
485system.cpu.iew.exec_rate 0.320604 # Inst execution rate
486system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit
487system.cpu.iew.wb_count 8105 # cumulative count of insts written-back
485system.cpu.iew.exec_rate 0.312302 # Inst execution rate
486system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
487system.cpu.iew.wb_count 8106 # cumulative count of insts written-back
488system.cpu.iew.wb_producers 3904 # num instructions producing a value
489system.cpu.iew.wb_consumers 7842 # num instructions consuming a value
490system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
488system.cpu.iew.wb_producers 3904 # num instructions producing a value
489system.cpu.iew.wb_consumers 7842 # num instructions consuming a value
490system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
491system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle
491system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle
492system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back
493system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
494system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit
495system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
496system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted
492system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back
493system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
494system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit
495system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
496system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted
497system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle
498system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle
499system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle
497system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle
498system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle
499system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle
500system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
500system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
501system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle
502system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle
503system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle
504system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle
505system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle
506system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle
507system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle
508system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle
509system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle
501system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle
502system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle
503system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle
504system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle
505system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle
506system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle
507system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle
508system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
509system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle
510system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
511system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
512system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
510system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
511system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
512system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
513system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle
513system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle
514system.cpu.commit.committedInsts 4591 # Number of instructions committed
515system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
516system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
517system.cpu.commit.refs 2138 # Number of memory references committed
518system.cpu.commit.loads 1200 # Number of loads committed
519system.cpu.commit.membars 12 # Number of memory barriers committed
520system.cpu.commit.branches 1007 # Number of branches committed
521system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
522system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
523system.cpu.commit.function_calls 82 # Number of function calls committed.
524system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
525system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
514system.cpu.commit.committedInsts 4591 # Number of instructions committed
515system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
516system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
517system.cpu.commit.refs 2138 # Number of memory references committed
518system.cpu.commit.loads 1200 # Number of loads committed
519system.cpu.commit.membars 12 # Number of memory barriers committed
520system.cpu.commit.branches 1007 # Number of branches committed
521system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
522system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
523system.cpu.commit.function_calls 82 # Number of function calls committed.
524system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
525system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
526system.cpu.rob.rob_reads 22955 # The number of ROB reads
526system.cpu.rob.rob_reads 23072 # The number of ROB reads
527system.cpu.rob.rob_writes 23605 # The number of ROB writes
528system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
527system.cpu.rob.rob_writes 23605 # The number of ROB writes
528system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
529system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
529system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling
530system.cpu.committedInsts 4591 # Number of Instructions Simulated
531system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
532system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
530system.cpu.committedInsts 4591 # Number of Instructions Simulated
531system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
532system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
533system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction
534system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads
535system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle
536system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads
537system.cpu.int_regfile_reads 39368 # number of integer regfile reads
538system.cpu.int_regfile_writes 8018 # number of integer regfile writes
533system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction
534system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads
535system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle
536system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads
537system.cpu.int_regfile_reads 39366 # number of integer regfile reads
538system.cpu.int_regfile_writes 8019 # number of integer regfile writes
539system.cpu.fp_regfile_reads 16 # number of floating regfile reads
540system.cpu.misc_regfile_reads 2982 # number of misc regfile reads
541system.cpu.misc_regfile_writes 24 # number of misc regfile writes
542system.cpu.icache.replacements 3 # number of replacements
539system.cpu.fp_regfile_reads 16 # number of floating regfile reads
540system.cpu.misc_regfile_reads 2982 # number of misc regfile reads
541system.cpu.misc_regfile_writes 24 # number of misc regfile writes
542system.cpu.icache.replacements 3 # number of replacements
543system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use
544system.cpu.icache.total_refs 1597 # Total number of references to valid blocks.
543system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use
544system.cpu.icache.total_refs 1596 # Total number of references to valid blocks.
545system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
545system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
546system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks.
546system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks.
547system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
547system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
548system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor
549system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy
550system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy
551system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits
552system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits
553system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits
554system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits
555system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits
556system.cpu.icache.overall_hits::total 1597 # number of overall hits
557system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
558system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
559system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
560system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
561system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
562system.cpu.icache.overall_misses::total 359 # number of overall misses
563system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles
564system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles
565system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles
566system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles
567system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles
568system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles
548system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor
549system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy
550system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy
551system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits
552system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits
553system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits
554system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits
555system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits
556system.cpu.icache.overall_hits::total 1596 # number of overall hits
557system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
558system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
559system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
560system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
561system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
562system.cpu.icache.overall_misses::total 360 # number of overall misses
563system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles
564system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles
565system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles
566system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles
567system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles
568system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles
569system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses)
570system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
571system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses
572system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses
573system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses
574system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses
569system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses)
570system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
571system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses
572system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses
573system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses
574system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses
575system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses
576system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses
577system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses
578system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses
579system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses
580system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses
581system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency
582system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency
583system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
584system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency
585system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
586system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency
587system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
575system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses
576system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses
577system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses
578system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses
579system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses
580system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses
581system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency
582system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency
583system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency
584system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency
585system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency
586system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency
587system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked
588system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
589system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
590system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
588system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
589system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
590system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
591system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked
591system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked
592system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
593system.cpu.icache.fast_writes 0 # number of fast writes performed
594system.cpu.icache.cache_copies 0 # number of cache copies performed
592system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
593system.cpu.icache.fast_writes 0 # number of fast writes performed
594system.cpu.icache.cache_copies 0 # number of cache copies performed
595system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
596system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
597system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
598system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
599system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
600system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
595system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
596system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
597system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
598system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
599system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
600system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
601system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
602system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
603system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
604system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
605system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
606system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
601system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
602system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
603system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
604system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
605system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
606system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
607system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles
608system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles
609system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles
610system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles
611system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles
612system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles
607system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles
608system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles
609system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles
610system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles
611system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles
612system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles
613system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses
614system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses
615system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses
616system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses
617system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses
618system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses
613system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses
614system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses
615system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses
616system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses
617system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses
618system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses
619system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency
620system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency
621system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency
622system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency
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--- 4 unchanged lines hidden (view full) ---

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--- 4 unchanged lines hidden (view full) ---

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--- 6 unchanged lines hidden (view full) ---

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--- 6 unchanged lines hidden (view full) ---

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--- 9 unchanged lines hidden (view full) ---

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--- 9 unchanged lines hidden (view full) ---

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738system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
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745system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses
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751system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
752system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
753system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
754system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
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756system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
757system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
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748system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency
749system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency
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753system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
754system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
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756system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
757system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
758system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency
759system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
760system.cpu.dcache.replacements 0 # number of replacements
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761system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use
762system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks.
761system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use
762system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks.
763system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
763system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
764system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks.
764system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks.
765system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
765system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
766system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor
767system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy
768system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy
769system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
770system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
766system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor
767system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy
768system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy
769system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits
770system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits
771system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
772system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
773system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
774system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
775system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
776system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
771system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
772system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
773system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
774system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
775system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
776system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
777system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
778system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits
779system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits
780system.cpu.dcache.overall_hits::total 2373 # number of overall hits
781system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
782system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
777system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits
778system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits
779system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits
780system.cpu.dcache.overall_hits::total 2370 # number of overall hits
781system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses
782system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses
783system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
784system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
785system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
786system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
783system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
784system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
785system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
786system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
787system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
788system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
789system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
790system.cpu.dcache.overall_misses::total 498 # number of overall misses
791system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles
792system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles
793system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
794system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
787system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses
788system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses
789system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses
790system.cpu.dcache.overall_misses::total 500 # number of overall misses
791system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles
792system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles
793system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles
794system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles
795system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
796system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
795system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
796system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
797system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles
798system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
799system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
800system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
801system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses)
802system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses)
797system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles
798system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles
799system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles
800system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles
801system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses)
802system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses)
803system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
804system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
805system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
806system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
807system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
808system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
803system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
804system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
805system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
806system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
807system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
808system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
809system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses
810system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses
811system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses
812system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses
813system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses
814system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses
809system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses
810system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses
811system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses
812system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses
813system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses
814system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses
815system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
816system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
817system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
818system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
815system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
816system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
817system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
818system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
819system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses
820system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses
821system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses
822system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses
823system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
824system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
825system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
826system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
819system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses
820system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses
821system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses
822system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses
823system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency
824system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency
825system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency
826system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency
827system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
828system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
827system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
828system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
829system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
830system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency
831system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
832system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency
833system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
829system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency
830system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency
831system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency
832system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency
833system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked
834system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
835system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
836system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
834system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
835system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
836system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
837system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
837system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked
838system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
839system.cpu.dcache.fast_writes 0 # number of fast writes performed
840system.cpu.dcache.cache_copies 0 # number of cache copies performed
838system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
839system.cpu.dcache.fast_writes 0 # number of fast writes performed
840system.cpu.dcache.cache_copies 0 # number of cache copies performed
841system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
842system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
841system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits
842system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits
843system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
844system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
845system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
846system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
843system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
844system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
845system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
846system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
847system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
848system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
849system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
850system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
847system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits
848system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits
849system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits
850system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits
851system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
852system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
853system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
854system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
855system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
856system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
857system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
858system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
851system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
852system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
853system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
854system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
855system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
856system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
857system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
858system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
859system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles
860system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles
861system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
862system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
863system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles
864system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
865system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
866system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
867system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses
868system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses
859system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles
860system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles
861system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles
862system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles
863system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles
864system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles
865system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles
866system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles
867system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses
868system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses
869system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
870system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
869system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
870system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
871system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses
872system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses
873system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses
874system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses
875system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
876system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
877system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
878system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
879system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
880system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
881system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
882system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
871system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses
872system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses
873system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses
874system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses
875system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency
876system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency
877system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency
878system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency
879system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
880system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
881system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
882system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
883system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
884
885---------- End Simulation Statistics ----------
883system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
884
885---------- End Simulation Statistics ----------