| stats.txt (9449:56610ab73040) | stats.txt (9459:8ca90cef0183) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated |
| 4sim_ticks 13372000 # Number of ticks simulated 5final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 13354000 # Number of ticks simulated 5final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 16216 # Simulator instruction rate (inst/s) 8host_op_rate 20228 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47166036 # Simulator tick rate (ticks/s) 10host_mem_usage 230800 # Number of bytes of host memory used 11host_seconds 0.28 # Real time elapsed on the host 12sim_insts 4596 # Number of instructions simulated 13sim_ops 5734 # Number of ops (including micro ops) simulated | 7host_inst_rate 46154 # Simulator instruction rate (inst/s) 8host_op_rate 57584 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 134203003 # Simulator tick rate (ticks/s) 10host_mem_usage 242404 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 394 # Number of read requests responded to by this memory | 14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 394 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 394 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 25216 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q --- 27 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 30system.physmem.readReqs 394 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 25216 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q --- 27 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 13314500 # Total gap between requests | 73system.physmem.totGap 13296500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 394 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 85 unchanged lines hidden (view full) --- 167system.physmem.totQLat 2460894 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests 169system.physmem.totBusLat 1576000 # Total cycles spent in databus access 170system.physmem.totBankLat 6524000 # Total cycles spent in bank access 171system.physmem.avgQLat 6245.92 # Average queueing delay per request 172system.physmem.avgBankLat 16558.38 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 26804.30 # Average memory access latency | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 394 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 85 unchanged lines hidden (view full) --- 167system.physmem.totQLat 2460894 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests 169system.physmem.totBusLat 1576000 # Total cycles spent in databus access 170system.physmem.totBankLat 6524000 # Total cycles spent in bank access 171system.physmem.avgQLat 6245.92 # Average queueing delay per request 172system.physmem.avgBankLat 16558.38 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 26804.30 # Average memory access latency |
| 175system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s | 175system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s |
| 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 177system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s | 177system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s |
| 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s | 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s |
| 180system.physmem.busUtil 11.79 # Data bus utilization in percentage | 180system.physmem.busUtil 11.80 # Data bus utilization in percentage |
| 181system.physmem.avgRdQLen 0.79 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 319 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 181system.physmem.avgRdQLen 0.79 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 319 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 33793.15 # Average gap between requests | 187system.physmem.avgGap 33747.46 # Average gap between requests |
| 188system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 189system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 190system.cpu.checker.dtb.read_hits 0 # DTB read hits 191system.cpu.checker.dtb.read_misses 0 # DTB read misses 192system.cpu.checker.dtb.write_hits 0 # DTB write hits 193system.cpu.checker.dtb.write_misses 0 # DTB write misses 194system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 223system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 224system.cpu.checker.itb.read_accesses 0 # DTB read accesses 225system.cpu.checker.itb.write_accesses 0 # DTB write accesses 226system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 227system.cpu.checker.itb.hits 0 # DTB hits 228system.cpu.checker.itb.misses 0 # DTB misses 229system.cpu.checker.itb.accesses 0 # DTB accesses 230system.cpu.workload.num_syscalls 13 # Number of system calls | 188system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 189system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 190system.cpu.checker.dtb.read_hits 0 # DTB read hits 191system.cpu.checker.dtb.read_misses 0 # DTB read misses 192system.cpu.checker.dtb.write_hits 0 # DTB write hits 193system.cpu.checker.dtb.write_misses 0 # DTB write misses 194system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 223system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 224system.cpu.checker.itb.read_accesses 0 # DTB read accesses 225system.cpu.checker.itb.write_accesses 0 # DTB write accesses 226system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 227system.cpu.checker.itb.hits 0 # DTB hits 228system.cpu.checker.itb.misses 0 # DTB misses 229system.cpu.checker.itb.accesses 0 # DTB accesses 230system.cpu.workload.num_syscalls 13 # Number of system calls |
| 231system.cpu.checker.numCycles 5747 # number of cpu cycles simulated | 231system.cpu.checker.numCycles 5742 # number of cpu cycles simulated |
| 232system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 234system.cpu.dtb.inst_hits 0 # ITB inst hits 235system.cpu.dtb.inst_misses 0 # ITB inst misses 236system.cpu.dtb.read_hits 0 # DTB read hits 237system.cpu.dtb.read_misses 0 # DTB read misses 238system.cpu.dtb.write_hits 0 # DTB write hits 239system.cpu.dtb.write_misses 0 # DTB write misses --- 28 unchanged lines hidden (view full) --- 268system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 269system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 270system.cpu.itb.read_accesses 0 # DTB read accesses 271system.cpu.itb.write_accesses 0 # DTB write accesses 272system.cpu.itb.inst_accesses 0 # ITB inst accesses 273system.cpu.itb.hits 0 # DTB hits 274system.cpu.itb.misses 0 # DTB misses 275system.cpu.itb.accesses 0 # DTB accesses | 232system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 234system.cpu.dtb.inst_hits 0 # ITB inst hits 235system.cpu.dtb.inst_misses 0 # ITB inst misses 236system.cpu.dtb.read_hits 0 # DTB read hits 237system.cpu.dtb.read_misses 0 # DTB read misses 238system.cpu.dtb.write_hits 0 # DTB write hits 239system.cpu.dtb.write_misses 0 # DTB write misses --- 28 unchanged lines hidden (view full) --- 268system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 269system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 270system.cpu.itb.read_accesses 0 # DTB read accesses 271system.cpu.itb.write_accesses 0 # DTB write accesses 272system.cpu.itb.inst_accesses 0 # ITB inst accesses 273system.cpu.itb.hits 0 # DTB hits 274system.cpu.itb.misses 0 # DTB misses 275system.cpu.itb.accesses 0 # DTB accesses |
| 276system.cpu.numCycles 26745 # number of cpu cycles simulated | 276system.cpu.numCycles 26709 # number of cpu cycles simulated |
| 277system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 278system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 277system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 278system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 279system.cpu.BPredUnit.lookups 2505 # Number of BP lookups 280system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted 281system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect 282system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups 283system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits | 279system.cpu.BPredUnit.lookups 2501 # Number of BP lookups 280system.cpu.BPredUnit.condPredicted 1795 # Number of conditional branches predicted 281system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect 282system.cpu.BPredUnit.BTBLookups 1976 # Number of BTB lookups 283system.cpu.BPredUnit.BTBHits 702 # Number of BTB hits |
| 284system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 284system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 285system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. | 285system.cpu.BPredUnit.usedRAS 292 # Number of times the RAS was used to get a target. |
| 286system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. | 286system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. |
| 287system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss 288system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed 289system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered 290system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken 291system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked 292system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing 293system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked 294system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched 295system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed 296system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total) | 287system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss 288system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed 289system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered 290system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken 291system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked 292system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing 293system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked 294system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched 295system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed 296system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total) |
| 299system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 299system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 300system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total) | 300system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total) |
| 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 312system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle 315system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked 317system.cpu.decode.RunCycles 2446 # Number of cycles decode is running | 312system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle 315system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked 317system.cpu.decode.RunCycles 2444 # Number of cycles decode is running |
| 318system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 319system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing | 318system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 319system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing |
| 320system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch | 320system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch |
| 321system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction | 321system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction |
| 322system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode | 322system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode |
| 323system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 324system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing | 323system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 324system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing |
| 325system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle | 325system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle |
| 326system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking | 326system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking |
| 327system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst 328system.cpu.rename.RunCycles 2247 # Number of cycles rename is running 329system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 330system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename | 327system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst 328system.cpu.rename.RunCycles 2245 # Number of cycles rename is running 329system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking 330system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename |
| 331system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 332system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 333system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full | 331system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 332system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 333system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full |
| 334system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed 335system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made 336system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups | 334system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed 335system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made 336system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups |
| 337system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups | 337system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups |
| 338system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed 339system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing 340system.cpu.rename.serializingInsts 44 # count of serializing insts renamed 341system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed 342system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer 343system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit. 344system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit. 345system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. | 338system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 339system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing 340system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 341system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 342system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer 343system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit. 344system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. 345system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. |
| 346system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. | 346system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. |
| 347system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec) 348system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ | 347system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) 348system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ |
| 349system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued 350system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued | 349system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued 350system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued |
| 351system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling 352system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph 353system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed 354system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle | 351system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling 352system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph 353system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 354system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle |
| 357system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 357system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 358system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle | 358system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle |
| 365system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 365system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 370system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle | 370system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle |
| 371system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 398system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 371system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 398system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 406system.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued 407system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued 408system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued | 406system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued 407system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued 408system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued |
| 437system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::total 8988 # Type of FU issued | 437system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::total 8988 # Type of FU issued |
| 440system.cpu.iq.rate 0.336063 # Inst issue rate | 440system.cpu.iq.rate 0.336516 # Inst issue rate |
| 441system.cpu.iq.fu_busy_cnt 228 # FU busy when requested 442system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) | 441system.cpu.iq.fu_busy_cnt 228 # FU busy when requested 442system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) |
| 443system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads 444system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes 445system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses | 443system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads 444system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes 445system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses |
| 446system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 447system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 448system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 449system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses 450system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 451system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores 452system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 453system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed 454system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed | 446system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 447system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 448system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 449system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses 450system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 451system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores 452system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 453system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed 454system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed |
| 455system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 456system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed | 455system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations 456system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed |
| 457system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 458system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 459system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 460system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 461system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 462system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing 463system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 464system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking | 457system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 458system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 459system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 460system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 461system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 462system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing 463system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 464system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking |
| 465system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ 466system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch 467system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions 468system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions 469system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions | 465system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ 466system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch 467system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions 468system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions 469system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions |
| 470system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 471system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 470system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 471system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 472system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 473system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly 474system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly 475system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute 476system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions | 472system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations 473system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly 474system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly 475system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute 476system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions |
| 477system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed | 477system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed |
| 478system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute | 478system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute |
| 479system.cpu.iew.exec_swp 0 # number of swp insts executed 480system.cpu.iew.exec_nop 0 # number of nop insts executed | 479system.cpu.iew.exec_swp 0 # number of swp insts executed 480system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 481system.cpu.iew.exec_refs 3300 # number of memory reference insts executed 482system.cpu.iew.exec_branches 1446 # Number of branches executed 483system.cpu.iew.exec_stores 1164 # Number of stores executed 484system.cpu.iew.exec_rate 0.320209 # Inst execution rate 485system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit 486system.cpu.iew.wb_count 8109 # cumulative count of insts written-back 487system.cpu.iew.wb_producers 3899 # num instructions producing a value 488system.cpu.iew.wb_consumers 7837 # num instructions consuming a value | 481system.cpu.iew.exec_refs 3303 # number of memory reference insts executed 482system.cpu.iew.exec_branches 1443 # Number of branches executed 483system.cpu.iew.exec_stores 1167 # Number of stores executed 484system.cpu.iew.exec_rate 0.320604 # Inst execution rate 485system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit 486system.cpu.iew.wb_count 8105 # cumulative count of insts written-back 487system.cpu.iew.wb_producers 3904 # num instructions producing a value 488system.cpu.iew.wb_consumers 7842 # num instructions consuming a value |
| 489system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 489system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 490system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle 491system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back | 490system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle 491system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back |
| 492system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 492system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 493system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit 494system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards 495system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle | 493system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit 494system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 495system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle |
| 499system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 499system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 500system.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle | 500system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle |
| 505system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 505system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 512system.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle 513system.cpu.commit.committedInsts 4596 # Number of instructions committed 514system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed | 512system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle 513system.cpu.commit.committedInsts 4591 # Number of instructions committed 514system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed |
| 515system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 515system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 516system.cpu.commit.refs 2140 # Number of memory references committed 517system.cpu.commit.loads 1201 # Number of loads committed | 516system.cpu.commit.refs 2138 # Number of memory references committed 517system.cpu.commit.loads 1200 # Number of loads committed |
| 518system.cpu.commit.membars 12 # Number of memory barriers committed | 518system.cpu.commit.membars 12 # Number of memory barriers committed |
| 519system.cpu.commit.branches 1008 # Number of branches committed | 519system.cpu.commit.branches 1007 # Number of branches committed |
| 520system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. | 520system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. |
| 521system.cpu.commit.int_insts 4980 # Number of committed integer instructions. | 521system.cpu.commit.int_insts 4976 # Number of committed integer instructions. |
| 522system.cpu.commit.function_calls 82 # Number of function calls committed. 523system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached 524system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 522system.cpu.commit.function_calls 82 # Number of function calls committed. 523system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached 524system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 525system.cpu.rob.rob_reads 22988 # The number of ROB reads 526system.cpu.rob.rob_writes 23599 # The number of ROB writes | 525system.cpu.rob.rob_reads 22955 # The number of ROB reads 526system.cpu.rob.rob_writes 23605 # The number of ROB writes |
| 527system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself 528system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling | 527system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself 528system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 529system.cpu.committedInsts 4596 # Number of Instructions Simulated 530system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated 531system.cpu.committedInsts_total 4596 # Number of Instructions Simulated 532system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction 533system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads 534system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle 535system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads 536system.cpu.int_regfile_reads 39369 # number of integer regfile reads 537system.cpu.int_regfile_writes 8027 # number of integer regfile writes | 529system.cpu.committedInsts 4591 # Number of Instructions Simulated 530system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 531system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 532system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction 533system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads 534system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle 535system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads 536system.cpu.int_regfile_reads 39368 # number of integer regfile reads 537system.cpu.int_regfile_writes 8018 # number of integer regfile writes |
| 538system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 538system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 539system.cpu.misc_regfile_reads 2981 # number of misc regfile reads 540system.cpu.misc_regfile_writes 26 # number of misc regfile writes 541system.cpu.icache.replacements 4 # number of replacements 542system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use 543system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. 544system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. 545system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. | 539system.cpu.misc_regfile_reads 2982 # number of misc regfile reads 540system.cpu.misc_regfile_writes 24 # number of misc regfile writes 541system.cpu.icache.replacements 3 # number of replacements 542system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use 543system.cpu.icache.total_refs 1597 # Total number of references to valid blocks. 544system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. 545system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks. |
| 546system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 546system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 547system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor 548system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy 549system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy 550system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits 551system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits 552system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits 553system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits 554system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits 555system.cpu.icache.overall_hits::total 1601 # number of overall hits 556system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses 557system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses 558system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses 559system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses 560system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses 561system.cpu.icache.overall_misses::total 360 # number of overall misses 562system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles 563system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles 564system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles 565system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles 566system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles 567system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles 568system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) 569system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) 570system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses 571system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses 572system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses 573system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses 574system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses 576system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses 577system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses 578system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses 579system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses 580system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency 581system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency 582system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency 583system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency 584system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency 585system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency | 547system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor 548system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy 549system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy 550system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits 551system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits 552system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits 553system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits 554system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits 555system.cpu.icache.overall_hits::total 1597 # number of overall hits 556system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses 557system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses 558system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses 559system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses 560system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses 561system.cpu.icache.overall_misses::total 359 # number of overall misses 562system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles 563system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles 564system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles 565system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles 566system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles 567system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles 568system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) 569system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 570system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses 571system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses 572system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses 573system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses 574system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses 576system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses 577system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses 578system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses 579system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses 580system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency 581system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency 582system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency 583system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency 584system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency 585system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency |
| 586system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked 587system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 589system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked 591system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.icache.fast_writes 0 # number of fast writes performed 593system.cpu.icache.cache_copies 0 # number of cache copies performed 594system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 595system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 596system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 597system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 598system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 599system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits | 586system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked 587system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 589system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked 591system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.icache.fast_writes 0 # number of fast writes performed 593system.cpu.icache.cache_copies 0 # number of cache copies performed 594system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 595system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 596system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 597system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 598system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 599system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits |
| 600system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses 601system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses 602system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses 603system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses 604system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses 605system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses 606system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles 607system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles 608system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles 609system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles 610system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles 611system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles 612system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses 613system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses 614system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses 615system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses 616system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses 617system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses 618system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency 619system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency 620system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency 621system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency 622system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency 623system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency | 600system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses 601system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses 602system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses 603system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses 604system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses 605system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses 606system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles 607system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles 608system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles 609system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles 610system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles 611system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles 612system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses 613system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses 614system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses 615system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses 616system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses 617system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses 618system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency 619system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency 620system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency 621system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency 622system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency 623system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency |
| 624system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 625system.cpu.l2cache.replacements 0 # number of replacements | 624system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 625system.cpu.l2cache.replacements 0 # number of replacements |
| 626system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use 627system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. | 626system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use 627system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. |
| 628system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. | 628system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. |
| 629system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks. | 629system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. |
| 630system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 630system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 631system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor 632system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor 633system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy 634system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy 635system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy 636system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits | 631system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor 632system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor 633system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy 634system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy 635system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy 636system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits |
| 637system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits | 637system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits |
| 638system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 639system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits | 638system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 639system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits |
| 640system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits | 640system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits |
| 641system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 642system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits | 641system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 642system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits |
| 643system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits | 643system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits |
| 644system.cpu.l2cache.overall_hits::total 40 # number of overall hits | 644system.cpu.l2cache.overall_hits::total 39 # number of overall hits |
| 645system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses 646system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 647system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses 648system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 649system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 650system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses 651system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 652system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses --- 6 unchanged lines hidden (view full) --- 659system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles 660system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles 661system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles 662system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles 663system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles 664system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles 665system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles 666system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles | 645system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses 646system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 647system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses 648system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 649system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 650system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses 651system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 652system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses --- 6 unchanged lines hidden (view full) --- 659system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles 660system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles 661system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles 662system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles 663system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles 664system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles 665system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles 666system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles |
| 667system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses) | 667system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) |
| 668system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) | 668system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) |
| 669system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) | 669system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) |
| 670system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 671system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) | 670system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 671system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) |
| 672system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses | 672system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses |
| 673system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses | 673system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses |
| 674system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses 675system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses | 674system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses 675system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses |
| 676system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses | 676system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses |
| 677system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses 678system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses | 677system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses 678system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.934708 # miss rate for ReadReq accesses |
| 679system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses | 679system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses |
| 680system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses | 680system.cpu.l2cache.ReadReq_miss_rate::total 0.901763 # miss rate for ReadReq accesses |
| 681system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 682system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 681system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 682system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 683system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses | 683system.cpu.l2cache.demand_miss_rate::cpu.inst 0.934708 # miss rate for demand accesses |
| 684system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses | 684system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses |
| 685system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses 686system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses | 685system.cpu.l2cache.demand_miss_rate::total 0.910959 # miss rate for demand accesses 686system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses |
| 687system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses | 687system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses |
| 688system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses | 688system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses |
| 689system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency 690system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency 691system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency 692system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency 693system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency 694system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 695system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 696system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency --- 31 unchanged lines hidden (view full) --- 728system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles 729system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles 730system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles 731system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles 732system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles 733system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles 734system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles 735system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles | 689system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency 690system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency 691system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency 692system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency 693system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency 694system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 695system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 696system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency --- 31 unchanged lines hidden (view full) --- 728system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles 729system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles 730system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles 731system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles 732system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles 733system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles 734system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles 735system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles |
| 736system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses | 736system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses |
| 737system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses | 737system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses |
| 738system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses | 738system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses |
| 739system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 740system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 739system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 740system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 741system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses | 741system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for demand accesses |
| 742system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses | 742system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses |
| 743system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses 744system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses | 743system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 # mshr miss rate for demand accesses 744system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses |
| 745system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses | 745system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses |
| 746system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses | 746system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses |
| 747system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency 748system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency 749system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency 750system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency 751system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency 752system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 753system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 754system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 755system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 756system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 757system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 758system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 759system.cpu.dcache.replacements 0 # number of replacements | 747system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency 748system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency 749system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency 750system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency 751system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency 752system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 753system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 754system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 755system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 756system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 757system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 758system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 759system.cpu.dcache.replacements 0 # number of replacements |
| 760system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use 761system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. | 760system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use 761system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks. |
| 762system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. | 762system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. |
| 763system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. | 763system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks. |
| 764system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 764system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 765system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor 766system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy 767system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy 768system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits 769system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits | 765system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor 766system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy 767system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy 768system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 769system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits |
| 770system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 771system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits | 770system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 771system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits |
| 772system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits 773system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits 774system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits 775system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits 776system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits 777system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits 778system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits 779system.cpu.dcache.overall_hits::total 2371 # number of overall hits | 772system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 773system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 774system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 775system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 776system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 777system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 778system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 779system.cpu.dcache.overall_hits::total 2373 # number of overall hits |
| 780system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses 781system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses 782system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 783system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 784system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 785system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 786system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 787system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses --- 4 unchanged lines hidden (view full) --- 792system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles 793system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles 794system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 795system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles 796system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles 797system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles 798system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles 799system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles | 780system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses 781system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses 782system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 783system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 784system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 785system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 786system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 787system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses --- 4 unchanged lines hidden (view full) --- 792system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles 793system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles 794system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 795system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles 796system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles 797system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles 798system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles 799system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles |
| 800system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 801system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) | 800system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses) 801system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses) |
| 802system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 803system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) | 802system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 803system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) |
| 804system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) 805system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) 806system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) 807system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) 808system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 809system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 810system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 811system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 812system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses 813system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses | 804system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 805system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 806system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 807system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 808system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses 809system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses 810system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses 811system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses 812system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses 813system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses |
| 814system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 815system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses | 814system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 815system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses |
| 816system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses 817system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses 818system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses 819system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses 820system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses 821system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses | 816system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 817system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 818system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses 819system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses 820system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses 821system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses |
| 822system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency 823system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency 824system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency 825system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency 826system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 827system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency 828system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 829system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency --- 28 unchanged lines hidden (view full) --- 858system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles 859system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles 860system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles 861system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles 862system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles 863system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles 864system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles 865system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles | 822system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency 823system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency 824system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency 825system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency 826system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 827system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency 828system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 829system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency --- 28 unchanged lines hidden (view full) --- 858system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles 859system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles 860system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles 861system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles 862system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles 863system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles 864system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles 865system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles |
| 866system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 867system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses | 866system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses 867system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses |
| 868system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 869system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses | 868system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 869system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses |
| 870system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 871system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 872system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 873system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses | 870system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses 871system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses 872system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses 873system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses |
| 874system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency 875system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency 876system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency 877system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency 878system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 879system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 880system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 881system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 882system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 883 884---------- End Simulation Statistics ---------- | 874system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency 875system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency 876system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency 877system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency 878system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 879system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 880system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 881system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 882system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 883 884---------- End Simulation Statistics ---------- |