| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10303500 # Number of ticks simulated 5final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10303500 # Number of ticks simulated 5final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 46836 # Simulator instruction rate (inst/s) 8host_op_rate 58425 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 104878029 # Simulator tick rate (ticks/s) 10host_mem_usage 222544 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host | 7host_inst_rate 20985 # Simulator instruction rate (inst/s) 8host_op_rate 26178 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46991642 # Simulator tick rate (ticks/s) 10host_mem_usage 229632 # Number of bytes of host memory used 11host_seconds 0.22 # Real time elapsed on the host |
| 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 25664 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 401 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 394 unchanged lines hidden (view full) --- 414system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses 415system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency 416system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 417system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 418system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 419system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 420system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 421system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 25664 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 401 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 394 unchanged lines hidden (view full) --- 414system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses 415system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency 416system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 417system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 418system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 419system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 420system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 421system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 422system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 423system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 422system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 423system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 424system.cpu.icache.fast_writes 0 # number of fast writes performed 425system.cpu.icache.cache_copies 0 # number of cache copies performed 426system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits 427system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 428system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits 429system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 430system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits 431system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 510system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency 511system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency 512system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 513system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 514system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 517system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 424system.cpu.icache.fast_writes 0 # number of fast writes performed 425system.cpu.icache.cache_copies 0 # number of cache copies performed 426system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits 427system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 428system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits 429system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 430system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits 431system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 510system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency 511system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency 512system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 513system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 514system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 517system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 518system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 519system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 518system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 519system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 520system.cpu.dcache.fast_writes 0 # number of fast writes performed 521system.cpu.dcache.cache_copies 0 # number of cache copies performed 522system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 523system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 524system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits 525system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits 526system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 527system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits --- 92 unchanged lines hidden (view full) --- 620system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 621system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 622system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 623system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 624system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 520system.cpu.dcache.fast_writes 0 # number of fast writes performed 521system.cpu.dcache.cache_copies 0 # number of cache copies performed 522system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 523system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 524system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits 525system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits 526system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 527system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits --- 92 unchanged lines hidden (view full) --- 620system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 621system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 622system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 623system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 624system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 628system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 629system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 628system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 629system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 630system.cpu.l2cache.fast_writes 0 # number of fast writes performed 631system.cpu.l2cache.cache_copies 0 # number of cache copies performed 632system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 633system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 634system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 635system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 636system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 637system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits --- 39 unchanged lines hidden --- | 630system.cpu.l2cache.fast_writes 0 # number of fast writes performed 631system.cpu.l2cache.cache_copies 0 # number of cache copies performed 632system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 633system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 634system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 635system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 636system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 637system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits --- 39 unchanged lines hidden --- |