| stats.txt (11687:b3d5f0e9e258) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 18422500 # Number of ticks simulated 5final_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18517500 # Number of ticks simulated 5final_tick 18517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 76941 # Simulator instruction rate (inst/s) 8host_op_rate 90095 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 308579581 # Simulator tick rate (ticks/s) 10host_mem_usage 270584 # Number of bytes of host memory used | 7host_inst_rate 74881 # Simulator instruction rate (inst/s) 8host_op_rate 87684 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 301872470 # Simulator tick rate (ticks/s) 10host_mem_usage 270416 # Number of bytes of host memory used |
| 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 25344 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory | 23system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::total 397 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 958827521 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 420355543 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1379183064 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 958827521 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 958827521 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 958827521 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 420355543 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1379183064 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 397 # Number of read requests accepted | 24system.physmem.num_reads::total 396 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 950452275 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 418199001 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1368651276 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 950452275 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 950452275 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 950452275 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 418199001 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1368651276 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 396 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 89 # Per bank write bursts 46system.physmem.perBankRdBursts::1 45 # Per bank write bursts 47system.physmem.perBankRdBursts::2 20 # Per bank write bursts 48system.physmem.perBankRdBursts::3 43 # Per bank write bursts 49system.physmem.perBankRdBursts::4 18 # Per bank write bursts 50system.physmem.perBankRdBursts::5 32 # Per bank write bursts 51system.physmem.perBankRdBursts::6 35 # Per bank write bursts 52system.physmem.perBankRdBursts::7 10 # Per bank write bursts 53system.physmem.perBankRdBursts::8 4 # Per bank write bursts | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 89 # Per bank write bursts 46system.physmem.perBankRdBursts::1 45 # Per bank write bursts 47system.physmem.perBankRdBursts::2 20 # Per bank write bursts 48system.physmem.perBankRdBursts::3 43 # Per bank write bursts 49system.physmem.perBankRdBursts::4 18 # Per bank write bursts 50system.physmem.perBankRdBursts::5 32 # Per bank write bursts 51system.physmem.perBankRdBursts::6 35 # Per bank write bursts 52system.physmem.perBankRdBursts::7 10 # Per bank write bursts 53system.physmem.perBankRdBursts::8 4 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::9 9 # Per bank write bursts | 54system.physmem.perBankRdBursts::9 8 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::10 28 # Per bank write bursts 56system.physmem.perBankRdBursts::11 42 # Per bank write bursts 57system.physmem.perBankRdBursts::12 10 # Per bank write bursts 58system.physmem.perBankRdBursts::13 6 # Per bank write bursts 59system.physmem.perBankRdBursts::14 0 # Per bank write bursts 60system.physmem.perBankRdBursts::15 6 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts --- 8 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 55system.physmem.perBankRdBursts::10 28 # Per bank write bursts 56system.physmem.perBankRdBursts::11 42 # Per bank write bursts 57system.physmem.perBankRdBursts::12 10 # Per bank write bursts 58system.physmem.perBankRdBursts::13 6 # Per bank write bursts 59system.physmem.perBankRdBursts::14 0 # Per bank write bursts 60system.physmem.perBankRdBursts::15 6 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts --- 8 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 18337000 # Total gap between requests | 79system.physmem.totGap 18432000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 397 # Read request sizes (log2) | 86system.physmem.readPktSize::6 396 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 204 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see | 95system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see | 96system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation | 98system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation |
| 191system.physmem.bytesPerActivate::mean 407.864407 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 273.934367 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 344.219630 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 10 16.95% 16.95% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 17 28.81% 45.76% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 8 13.56% 59.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 7 11.86% 71.19% # Bytes accessed per row activation | 191system.physmem.bytesPerActivate::mean 406.779661 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 269.610222 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 346.645206 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% # Bytes accessed per row activation |
| 198system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation | 198system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation |
| 199system.physmem.bytesPerActivate::640-767 2 3.39% 76.27% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 3 5.08% 81.36% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 5.08% 86.44% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 8 13.56% 100.00% # Bytes accessed per row activation | 199system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation |
| 203system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation | 203system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation |
| 204system.physmem.totQLat 5196750 # Total ticks spent queuing 205system.physmem.totMemAccLat 12640500 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 13090.05 # Average queueing delay per DRAM burst | 204system.physmem.totQLat 5212000 # Total ticks spent queuing 205system.physmem.totMemAccLat 12637000 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 13161.62 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 31840.05 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1379.18 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 31911.62 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1368.65 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1379.18 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 1368.65 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 10.77 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.77 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 10.69 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.69 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 218system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing | 218system.physmem.avgRdQLen 1.87 # Average read queue length when enqueuing |
| 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 330 # Number of row buffer hits during reads | 220system.physmem.readRowHits 329 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 46188.92 # Average gap between requests 225system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined | 224system.physmem.avgGap 46545.45 # Average gap between requests 225system.physmem.pageHitRate 83.08 # Row buffer hit rate, read and write combined |
| 226system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) | 226system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 3077430 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 36000 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 5255970 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) | 231system.physmem_0.actBackEnergy 3085980 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 37920 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 5290170 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 19200 # Energy for precharge power-down per rank (pJ) |
| 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 236system.physmem_0.totalEnergy 12170160 # Total energy per rank (pJ) 237system.physmem_0.averagePower 660.613923 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 11420000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states | 236system.physmem_0.totalEnergy 12213390 # Total energy per rank (pJ) 237system.physmem_0.averagePower 659.559336 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 11496500 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 29500 # Time in different power states |
| 240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states | 240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 53500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 6303750 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 11521750 # Time in different power states | 242system.physmem_0.memoryStateTime::PRE_PDN 49250 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 6316250 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 11602500 # Time in different power states |
| 245system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) | 245system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) |
| 247system.physmem_1.readEnergy 749700 # Energy for read commands per rank (pJ) | 247system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) |
| 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) | 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 1466040 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 65760 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6124080 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 616800 # Energy for precharge power-down per rank (pJ) | 250system.physmem_1.actBackEnergy 1457490 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 66240 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6092730 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 686400 # Energy for precharge power-down per rank (pJ) |
| 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 255system.physmem_1.totalEnergy 10487985 # Total energy per rank (pJ) 256system.physmem_1.averagePower 569.303026 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 14986000 # Total Idle time Per DRAM Rank | 255system.physmem_1.totalEnergy 10511025 # Total energy per rank (pJ) 256system.physmem_1.averagePower 567.626569 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 15098500 # Total Idle time Per DRAM Rank |
| 258system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states | 258system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states |
| 261system.physmem_1.memoryStateTime::PRE_PDN 1605250 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 2751250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 13430000 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2844 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1749 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 2408 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 867 # Number of BTB hits | 261system.physmem_1.memoryStateTime::PRE_PDN 1787250 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 2733750 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 13360500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2820 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1728 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 468 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 2384 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 844 # Number of BTB hits |
| 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 271system.cpu.branchPred.BTBHitPct 36.004983 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. | 271system.cpu.branchPred.BTBHitPct 35.402685 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 322 # Number of times the RAS was used to get a target. |
| 273system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. | 273system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. |
| 274system.cpu.branchPred.indirectLookups 266 # Number of indirect predictor lookups. | 274system.cpu.branchPred.indirectLookups 260 # Number of indirect predictor lookups. |
| 275system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. | 275system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. |
| 276system.cpu.branchPred.indirectMisses 253 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. | 276system.cpu.branchPred.indirectMisses 247 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. |
| 278system.cpu_clk_domain.clock 500 # Clock period in ticks | 278system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 279system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 279system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 280system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 281system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 282system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 283system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 284system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 285system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 286system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 287system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 301system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 280system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 281system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 282system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 283system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 284system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 285system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 286system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 287system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 301system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 309system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 309system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 310system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 311system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 331system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 334system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 335system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 336system.cpu.checker.dtb.hits 0 # DTB hits 337system.cpu.checker.dtb.misses 0 # DTB misses 338system.cpu.checker.dtb.accesses 0 # DTB accesses | 310system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 311system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 331system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 334system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 335system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 336system.cpu.checker.dtb.hits 0 # DTB hits 337system.cpu.checker.dtb.misses 0 # DTB misses 338system.cpu.checker.dtb.accesses 0 # DTB accesses |
| 339system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 339system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 340system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 361system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 340system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 361system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 369system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 369system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 370system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 371system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 392system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.checker.itb.read_accesses 0 # DTB read accesses 394system.cpu.checker.itb.write_accesses 0 # DTB write accesses 395system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 396system.cpu.checker.itb.hits 0 # DTB hits 397system.cpu.checker.itb.misses 0 # DTB misses 398system.cpu.checker.itb.accesses 0 # DTB accesses 399system.cpu.workload.num_syscalls 13 # Number of system calls | 370system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 371system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 392system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.checker.itb.read_accesses 0 # DTB read accesses 394system.cpu.checker.itb.write_accesses 0 # DTB write accesses 395system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 396system.cpu.checker.itb.hits 0 # DTB hits 397system.cpu.checker.itb.misses 0 # DTB misses 398system.cpu.checker.itb.accesses 0 # DTB accesses 399system.cpu.workload.num_syscalls 13 # Number of system calls |
| 400system.cpu.checker.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states | 400system.cpu.checker.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states |
| 401system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 402system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 403system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed | 401system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 402system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 403system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 404system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 404system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 405system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 406system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 407system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 408system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 409system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 410system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 411system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 412system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 426system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 427system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 428system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 429system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 430system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 431system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 432system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 433system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 405system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 406system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 407system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 408system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 409system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 410system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 411system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 412system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 426system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 427system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 428system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 429system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 430system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 431system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 432system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 433system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 434system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 434system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 435system.cpu.dtb.walker.walks 0 # Table walker walks requested 436system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 437system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 438system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 441system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 442system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 456system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 457system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458system.cpu.dtb.read_accesses 0 # DTB read accesses 459system.cpu.dtb.write_accesses 0 # DTB write accesses 460system.cpu.dtb.inst_accesses 0 # ITB inst accesses 461system.cpu.dtb.hits 0 # DTB hits 462system.cpu.dtb.misses 0 # DTB misses 463system.cpu.dtb.accesses 0 # DTB accesses | 435system.cpu.dtb.walker.walks 0 # Table walker walks requested 436system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 437system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 438system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 441system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 442system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 456system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 457system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458system.cpu.dtb.read_accesses 0 # DTB read accesses 459system.cpu.dtb.write_accesses 0 # DTB write accesses 460system.cpu.dtb.inst_accesses 0 # ITB inst accesses 461system.cpu.dtb.hits 0 # DTB hits 462system.cpu.dtb.misses 0 # DTB misses 463system.cpu.dtb.accesses 0 # DTB accesses |
| 464system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 464system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 465system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 472system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 486system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 487system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 488system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 489system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 490system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 491system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 492system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 493system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 465system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 472system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 486system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 487system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 488system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 489system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 490system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 491system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 492system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 493system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 494system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 494system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 495system.cpu.itb.walker.walks 0 # Table walker walks requested 496system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 498system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 501system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 516system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 517system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 518system.cpu.itb.read_accesses 0 # DTB read accesses 519system.cpu.itb.write_accesses 0 # DTB write accesses 520system.cpu.itb.inst_accesses 0 # ITB inst accesses 521system.cpu.itb.hits 0 # DTB hits 522system.cpu.itb.misses 0 # DTB misses 523system.cpu.itb.accesses 0 # DTB accesses | 495system.cpu.itb.walker.walks 0 # Table walker walks requested 496system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 498system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 501system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 516system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 517system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 518system.cpu.itb.read_accesses 0 # DTB read accesses 519system.cpu.itb.write_accesses 0 # DTB write accesses 520system.cpu.itb.inst_accesses 0 # ITB inst accesses 521system.cpu.itb.hits 0 # DTB hits 522system.cpu.itb.misses 0 # DTB misses 523system.cpu.itb.accesses 0 # DTB accesses |
| 524system.cpu.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states 525system.cpu.numCycles 36846 # number of cpu cycles simulated | 524system.cpu.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states 525system.cpu.numCycles 37036 # number of cpu cycles simulated |
| 526system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 527system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 526system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 527system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 528system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss 529system.cpu.fetch.Insts 12314 # Number of instructions fetch has processed 530system.cpu.fetch.Branches 2844 # Number of branches that fetch encountered 531system.cpu.fetch.predictedBranches 1194 # Number of branches that fetch has predicted taken 532system.cpu.fetch.Cycles 5108 # Number of cycles fetch has run and was not squashing or blocked 533system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing | 528system.cpu.fetch.icacheStallCycles 7733 # Number of cycles fetch is stalled on an Icache miss 529system.cpu.fetch.Insts 12373 # Number of instructions fetch has processed 530system.cpu.fetch.Branches 2820 # Number of branches that fetch encountered 531system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken 532system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked 533system.cpu.fetch.SquashCycles 985 # Number of cycles fetch has spent squashing |
| 534system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 535system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps 536system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR | 534system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 535system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps 536system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR |
| 537system.cpu.fetch.CacheLines 1962 # Number of cache lines fetched 538system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed 539system.cpu.fetch.rateDist::samples 13535 # Number of instructions fetched each cycle (Total) 540system.cpu.fetch.rateDist::mean 1.094422 # Number of instructions fetched each cycle (Total) 541system.cpu.fetch.rateDist::stdev 2.458272 # Number of instructions fetched each cycle (Total) | 537system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched 538system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed 539system.cpu.fetch.rateDist::samples 13616 # Number of instructions fetched each cycle (Total) 540system.cpu.fetch.rateDist::mean 1.093052 # Number of instructions fetched each cycle (Total) 541system.cpu.fetch.rateDist::stdev 2.461769 # Number of instructions fetched each cycle (Total) |
| 542system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 542system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 543system.cpu.fetch.rateDist::0 10839 80.08% 80.08% # Number of instructions fetched each cycle (Total) 544system.cpu.fetch.rateDist::1 264 1.95% 82.03% # Number of instructions fetched each cycle (Total) 545system.cpu.fetch.rateDist::2 185 1.37% 83.40% # Number of instructions fetched each cycle (Total) 546system.cpu.fetch.rateDist::3 204 1.51% 84.91% # Number of instructions fetched each cycle (Total) 547system.cpu.fetch.rateDist::4 283 2.09% 87.00% # Number of instructions fetched each cycle (Total) 548system.cpu.fetch.rateDist::5 398 2.94% 89.94% # Number of instructions fetched each cycle (Total) 549system.cpu.fetch.rateDist::6 139 1.03% 90.96% # Number of instructions fetched each cycle (Total) 550system.cpu.fetch.rateDist::7 173 1.28% 92.24% # Number of instructions fetched each cycle (Total) 551system.cpu.fetch.rateDist::8 1050 7.76% 100.00% # Number of instructions fetched each cycle (Total) | 543system.cpu.fetch.rateDist::0 10916 80.17% 80.17% # Number of instructions fetched each cycle (Total) 544system.cpu.fetch.rateDist::1 271 1.99% 82.16% # Number of instructions fetched each cycle (Total) 545system.cpu.fetch.rateDist::2 182 1.34% 83.50% # Number of instructions fetched each cycle (Total) 546system.cpu.fetch.rateDist::3 206 1.51% 85.01% # Number of instructions fetched each cycle (Total) 547system.cpu.fetch.rateDist::4 259 1.90% 86.91% # Number of instructions fetched each cycle (Total) 548system.cpu.fetch.rateDist::5 398 2.92% 89.84% # Number of instructions fetched each cycle (Total) 549system.cpu.fetch.rateDist::6 138 1.01% 90.85% # Number of instructions fetched each cycle (Total) 550system.cpu.fetch.rateDist::7 192 1.41% 92.26% # Number of instructions fetched each cycle (Total) 551system.cpu.fetch.rateDist::8 1054 7.74% 100.00% # Number of instructions fetched each cycle (Total) |
| 552system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 553system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 554system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 552system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 553system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 554system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 555system.cpu.fetch.rateDist::total 13535 # Number of instructions fetched each cycle (Total) 556system.cpu.fetch.branchRate 0.077186 # Number of branch fetches per cycle 557system.cpu.fetch.rate 0.334202 # Number of inst fetches per cycle 558system.cpu.decode.IdleCycles 6279 # Number of cycles decode is idle 559system.cpu.decode.BlockedCycles 4644 # Number of cycles decode is blocked 560system.cpu.decode.RunCycles 2146 # Number of cycles decode is running 561system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 562system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing 563system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch | 555system.cpu.fetch.rateDist::total 13616 # Number of instructions fetched each cycle (Total) 556system.cpu.fetch.branchRate 0.076142 # Number of branch fetches per cycle 557system.cpu.fetch.rate 0.334080 # Number of inst fetches per cycle 558system.cpu.decode.IdleCycles 6341 # Number of cycles decode is idle 559system.cpu.decode.BlockedCycles 4657 # Number of cycles decode is blocked 560system.cpu.decode.RunCycles 2138 # Number of cycles decode is running 561system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking 562system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing 563system.cpu.decode.BranchResolved 909 # Number of times decode resolved a branch |
| 564system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction | 564system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction |
| 565system.cpu.decode.DecodedInsts 12150 # Number of instructions handled by decode | 565system.cpu.decode.DecodedInsts 12250 # Number of instructions handled by decode |
| 566system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode | 566system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode |
| 567system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing 568system.cpu.rename.IdleCycles 6511 # Number of cycles rename is idle 569system.cpu.rename.BlockCycles 826 # Number of cycles rename is blocking | 567system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing 568system.cpu.rename.IdleCycles 6573 # Number of cycles rename is idle 569system.cpu.rename.BlockCycles 835 # Number of cycles rename is blocking |
| 570system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst | 570system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst |
| 571system.cpu.rename.RunCycles 2033 # Number of cycles rename is running 572system.cpu.rename.UnblockCycles 1361 # Number of cycles rename is unblocking 573system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename | 571system.cpu.rename.RunCycles 2036 # Number of cycles rename is running 572system.cpu.rename.UnblockCycles 1364 # Number of cycles rename is unblocking 573system.cpu.rename.RenamedInsts 11552 # Number of instructions processed by rename |
| 574system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full | 574system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full |
| 575system.cpu.rename.IQFullEvents 178 # Number of times rename has blocked due to IQ full | 575system.cpu.rename.IQFullEvents 181 # Number of times rename has blocked due to IQ full |
| 576system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full | 576system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full |
| 577system.cpu.rename.SQFullEvents 1169 # Number of times rename has blocked due to SQ full 578system.cpu.rename.RenamedOperands 11641 # Number of destination operands rename has renamed 579system.cpu.rename.RenameLookups 52345 # Number of register rename lookups that rename has made 580system.cpu.rename.int_rename_lookups 12355 # Number of integer rename lookups | 577system.cpu.rename.SQFullEvents 1170 # Number of times rename has blocked due to SQ full 578system.cpu.rename.RenamedOperands 11673 # Number of destination operands rename has renamed 579system.cpu.rename.RenameLookups 53030 # Number of register rename lookups that rename has made 580system.cpu.rename.int_rename_lookups 12530 # Number of integer rename lookups |
| 581system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups 582system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed | 581system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups 582system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed |
| 583system.cpu.rename.UndoneMaps 6147 # Number of HB maps that are undone due to squashing | 583system.cpu.rename.UndoneMaps 6179 # Number of HB maps that are undone due to squashing |
| 584system.cpu.rename.serializingInsts 40 # count of serializing insts renamed 585system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed | 584system.cpu.rename.serializingInsts 40 # count of serializing insts renamed 585system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed |
| 586system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer 587system.cpu.memDep0.insertedLoads 2197 # Number of loads inserted to the mem dependence unit. 588system.cpu.memDep0.insertedStores 1543 # Number of stores inserted to the mem dependence unit. | 586system.cpu.rename.skidInsts 442 # count of insts added to the skid buffer 587system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. 588system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. |
| 589system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. 590system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. | 589system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. 590system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. |
| 591system.cpu.iq.iqInstsAdded 10169 # Number of instructions added to the IQ (excludes non-spec) | 591system.cpu.iq.iqInstsAdded 10296 # Number of instructions added to the IQ (excludes non-spec) |
| 592system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ | 592system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ |
| 593system.cpu.iq.iqInstsIssued 8096 # Number of instructions issued 594system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued 595system.cpu.iq.iqSquashedInstsExamined 4835 # Number of squashed instructions iterated over during squash; mainly for profiling 596system.cpu.iq.iqSquashedOperandsExamined 12334 # Number of squashed operands that are examined and possibly removed from graph | 593system.cpu.iq.iqInstsIssued 8207 # Number of instructions issued 594system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued 595system.cpu.iq.iqSquashedInstsExamined 4962 # Number of squashed instructions iterated over during squash; mainly for profiling 596system.cpu.iq.iqSquashedOperandsExamined 12830 # Number of squashed operands that are examined and possibly removed from graph |
| 597system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed | 597system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed |
| 598system.cpu.iq.issued_per_cycle::samples 13535 # Number of insts issued each cycle 599system.cpu.iq.issued_per_cycle::mean 0.598153 # Number of insts issued each cycle 600system.cpu.iq.issued_per_cycle::stdev 1.329974 # Number of insts issued each cycle | 598system.cpu.iq.issued_per_cycle::samples 13616 # Number of insts issued each cycle 599system.cpu.iq.issued_per_cycle::mean 0.602747 # Number of insts issued each cycle 600system.cpu.iq.issued_per_cycle::stdev 1.340306 # Number of insts issued each cycle |
| 601system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 601system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 602system.cpu.iq.issued_per_cycle::0 10320 76.25% 76.25% # Number of insts issued each cycle 603system.cpu.iq.issued_per_cycle::1 1163 8.59% 84.84% # Number of insts issued each cycle 604system.cpu.iq.issued_per_cycle::2 763 5.64% 90.48% # Number of insts issued each cycle 605system.cpu.iq.issued_per_cycle::3 482 3.56% 94.04% # Number of insts issued each cycle 606system.cpu.iq.issued_per_cycle::4 344 2.54% 96.58% # Number of insts issued each cycle 607system.cpu.iq.issued_per_cycle::5 273 2.02% 98.60% # Number of insts issued each cycle 608system.cpu.iq.issued_per_cycle::6 120 0.89% 99.48% # Number of insts issued each cycle 609system.cpu.iq.issued_per_cycle::7 60 0.44% 99.93% # Number of insts issued each cycle | 602system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% # Number of insts issued each cycle 603system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% # Number of insts issued each cycle 604system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% # Number of insts issued each cycle 605system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% # Number of insts issued each cycle 606system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% # Number of insts issued each cycle 607system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% # Number of insts issued each cycle 608system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% # Number of insts issued each cycle 609system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% # Number of insts issued each cycle |
| 610system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle 611system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 612system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 613system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 610system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle 611system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 612system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 613system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 614system.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle | 614system.cpu.iq.issued_per_cycle::total 13616 # Number of insts issued each cycle |
| 615system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 615system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 616system.cpu.iq.fu_full::IntAlu 9 6.00% 6.00% # attempts to use FU when none available 617system.cpu.iq.fu_full::IntMult 0 0.00% 6.00% # attempts to use FU when none available 618system.cpu.iq.fu_full::IntDiv 0 0.00% 6.00% # attempts to use FU when none available 619system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.00% # attempts to use FU when none available 620system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.00% # attempts to use FU when none available 621system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.00% # attempts to use FU when none available 622system.cpu.iq.fu_full::FloatMult 0 0.00% 6.00% # attempts to use FU when none available 623system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available 624system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.00% # attempts to use FU when none available 625system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.00% # attempts to use FU when none available 626system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.00% # attempts to use FU when none available 627system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.00% # attempts to use FU when none available 628system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.00% # attempts to use FU when none available 629system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.00% # attempts to use FU when none available 630system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.00% # attempts to use FU when none available 631system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.00% # attempts to use FU when none available 632system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.00% # attempts to use FU when none available 633system.cpu.iq.fu_full::SimdMult 0 0.00% 6.00% # attempts to use FU when none available 634system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.00% # attempts to use FU when none available 635system.cpu.iq.fu_full::SimdShift 0 0.00% 6.00% # attempts to use FU when none available 636system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.00% # attempts to use FU when none available 637system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.00% # attempts to use FU when none available 638system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.00% # attempts to use FU when none available 639system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.00% # attempts to use FU when none available 640system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.00% # attempts to use FU when none available 641system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.00% # attempts to use FU when none available 642system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.00% # attempts to use FU when none available 643system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.00% # attempts to use FU when none available 644system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.00% # attempts to use FU when none available 645system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available 646system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.00% # attempts to use FU when none available 647system.cpu.iq.fu_full::MemRead 66 44.00% 50.00% # attempts to use FU when none available 648system.cpu.iq.fu_full::MemWrite 62 41.33% 91.33% # attempts to use FU when none available 649system.cpu.iq.fu_full::FloatMemRead 0 0.00% 91.33% # attempts to use FU when none available 650system.cpu.iq.fu_full::FloatMemWrite 13 8.67% 100.00% # attempts to use FU when none available | 616system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% # attempts to use FU when none available 617system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% # attempts to use FU when none available 618system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% # attempts to use FU when none available 619system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% # attempts to use FU when none available 620system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% # attempts to use FU when none available 621system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% # attempts to use FU when none available 622system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% # attempts to use FU when none available 623system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available 624system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% # attempts to use FU when none available 625system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% # attempts to use FU when none available 626system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% # attempts to use FU when none available 627system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% # attempts to use FU when none available 628system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% # attempts to use FU when none available 629system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% # attempts to use FU when none available 630system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% # attempts to use FU when none available 631system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% # attempts to use FU when none available 632system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% # attempts to use FU when none available 633system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% # attempts to use FU when none available 634system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% # attempts to use FU when none available 635system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% # attempts to use FU when none available 636system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% # attempts to use FU when none available 637system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% # attempts to use FU when none available 638system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% # attempts to use FU when none available 639system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% # attempts to use FU when none available 640system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% # attempts to use FU when none available 641system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% # attempts to use FU when none available 642system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% # attempts to use FU when none available 643system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% # attempts to use FU when none available 644system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% # attempts to use FU when none available 645system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available 646system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% # attempts to use FU when none available 647system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% # attempts to use FU when none available 648system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% # attempts to use FU when none available 649system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% # attempts to use FU when none available 650system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% # attempts to use FU when none available |
| 651system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 652system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 653system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 651system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 652system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 653system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 654system.cpu.iq.FU_type_0::IntAlu 5023 62.04% 62.04% # Type of FU issued 655system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued 656system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued 657system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued 658system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued 659system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued 660system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued 661system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.13% # Type of FU issued 662system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued 663system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.13% # Type of FU issued 664system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued 665system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued 666system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued 667system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued 668system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued 669system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued 670system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued 671system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued 672system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued 673system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued 674system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued 675system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued 676system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued 677system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued 678system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued 679system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued 680system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued 681system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued 682system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued 683system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued 684system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued 685system.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued 686system.cpu.iq.FU_type_0::MemWrite 1154 14.25% 99.59% # Type of FU issued 687system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.59% # Type of FU issued 688system.cpu.iq.FU_type_0::FloatMemWrite 33 0.41% 100.00% # Type of FU issued | 654system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% # Type of FU issued 655system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% # Type of FU issued 656system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued 657system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% # Type of FU issued 658system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% # Type of FU issued 659system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% # Type of FU issued 660system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% # Type of FU issued 661system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% # Type of FU issued 662system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% # Type of FU issued 663system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% # Type of FU issued 664system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% # Type of FU issued 665system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% # Type of FU issued 666system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% # Type of FU issued 667system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% # Type of FU issued 668system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% # Type of FU issued 669system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% # Type of FU issued 670system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% # Type of FU issued 671system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% # Type of FU issued 672system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% # Type of FU issued 673system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% # Type of FU issued 674system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% # Type of FU issued 675system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% # Type of FU issued 676system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% # Type of FU issued 677system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% # Type of FU issued 678system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% # Type of FU issued 679system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% # Type of FU issued 680system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% # Type of FU issued 681system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% # Type of FU issued 682system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% # Type of FU issued 683system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued 684system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued 685system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% # Type of FU issued 686system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% # Type of FU issued 687system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% # Type of FU issued 688system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% # Type of FU issued |
| 689system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 690system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 689system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 690system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 691system.cpu.iq.FU_type_0::total 8096 # Type of FU issued 692system.cpu.iq.rate 0.219725 # Inst issue rate 693system.cpu.iq.fu_busy_cnt 150 # FU busy when requested 694system.cpu.iq.fu_busy_rate 0.018528 # FU busy rate (busy events/executed inst) 695system.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads 696system.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes 697system.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses | 691system.cpu.iq.FU_type_0::total 8207 # Type of FU issued 692system.cpu.iq.rate 0.221595 # Inst issue rate 693system.cpu.iq.fu_busy_cnt 166 # FU busy when requested 694system.cpu.iq.fu_busy_rate 0.020227 # FU busy rate (busy events/executed inst) 695system.cpu.iq.int_inst_queue_reads 30145 # Number of integer instruction queue reads 696system.cpu.iq.int_inst_queue_writes 15189 # Number of integer instruction queue writes 697system.cpu.iq.int_inst_queue_wakeup_accesses 7438 # Number of integer instruction queue wakeup accesses |
| 698system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads 699system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes 700system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses | 698system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads 699system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes 700system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses |
| 701system.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses | 701system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses |
| 702system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses | 702system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses |
| 703system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores | 703system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores |
| 704system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 704system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 705system.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed | 705system.cpu.iew.lsq.thread0.squashedLoads 1266 # Number of loads squashed |
| 706system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 707system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations | 706system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 707system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations |
| 708system.cpu.iew.lsq.thread0.squashedStores 605 # Number of stores squashed | 708system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed |
| 709system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 710system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 709system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 710system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 711system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled | 711system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled |
| 712system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 713system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 712system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 713system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 714system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing 715system.cpu.iew.iewBlockCycles 696 # Number of cycles IEW is blocking 716system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking 717system.cpu.iew.iewDispatchedInsts 10222 # Number of instructions dispatched to IQ 718system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch 719system.cpu.iew.iewDispLoadInsts 2197 # Number of dispatched load instructions 720system.cpu.iew.iewDispStoreInsts 1543 # Number of dispatched store instructions | 714system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing 715system.cpu.iew.iewBlockCycles 707 # Number of cycles IEW is blocking 716system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 717system.cpu.iew.iewDispatchedInsts 10349 # Number of instructions dispatched to IQ 718system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch 719system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions 720system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions |
| 721system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions | 721system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions |
| 722system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall | 722system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall |
| 723system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 724system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations | 723system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 724system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations |
| 725system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly 726system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly 727system.cpu.iew.branchMispredicts 356 # Number of branch mispredicts detected at execute 728system.cpu.iew.iewExecutedInsts 7806 # Number of executed instructions 729system.cpu.iew.iewExecLoadInsts 1768 # Number of load instructions executed 730system.cpu.iew.iewExecSquashedInsts 290 # Number of squashed instructions skipped in execute | 725system.cpu.iew.predictedTakenIncorrect 93 # Number of branches that were predicted taken incorrectly 726system.cpu.iew.predictedNotTakenIncorrect 267 # Number of branches that were predicted not taken incorrectly 727system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute 728system.cpu.iew.iewExecutedInsts 7885 # Number of executed instructions 729system.cpu.iew.iewExecLoadInsts 1840 # Number of load instructions executed 730system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute |
| 731system.cpu.iew.exec_swp 0 # number of swp insts executed 732system.cpu.iew.exec_nop 9 # number of nop insts executed | 731system.cpu.iew.exec_swp 0 # number of swp insts executed 732system.cpu.iew.exec_nop 9 # number of nop insts executed |
| 733system.cpu.iew.exec_refs 2921 # number of memory reference insts executed 734system.cpu.iew.exec_branches 1491 # Number of branches executed 735system.cpu.iew.exec_stores 1153 # Number of stores executed 736system.cpu.iew.exec_rate 0.211855 # Inst execution rate 737system.cpu.iew.wb_sent 7533 # cumulative count of insts sent to commit 738system.cpu.iew.wb_count 7436 # cumulative count of insts written-back 739system.cpu.iew.wb_producers 3503 # num instructions producing a value 740system.cpu.iew.wb_consumers 6835 # num instructions consuming a value 741system.cpu.iew.wb_rate 0.201813 # insts written-back per cycle 742system.cpu.iew.wb_fanout 0.512509 # average fanout of values written-back 743system.cpu.commit.commitSquashedInsts 4843 # The number of squashed insts skipped by commit | 733system.cpu.iew.exec_refs 3007 # number of memory reference insts executed 734system.cpu.iew.exec_branches 1490 # Number of branches executed 735system.cpu.iew.exec_stores 1167 # Number of stores executed 736system.cpu.iew.exec_rate 0.212901 # Inst execution rate 737system.cpu.iew.wb_sent 7581 # cumulative count of insts sent to commit 738system.cpu.iew.wb_count 7470 # cumulative count of insts written-back 739system.cpu.iew.wb_producers 3518 # num instructions producing a value 740system.cpu.iew.wb_consumers 6872 # num instructions consuming a value 741system.cpu.iew.wb_rate 0.201696 # insts written-back per cycle 742system.cpu.iew.wb_fanout 0.511932 # average fanout of values written-back 743system.cpu.commit.commitSquashedInsts 4970 # The number of squashed insts skipped by commit |
| 744system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards | 744system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards |
| 745system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted 746system.cpu.commit.committed_per_cycle::samples 12682 # Number of insts commited each cycle 747system.cpu.commit.committed_per_cycle::mean 0.424066 # Number of insts commited each cycle 748system.cpu.commit.committed_per_cycle::stdev 1.266213 # Number of insts commited each cycle | 745system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted 746system.cpu.commit.committed_per_cycle::samples 12743 # Number of insts commited each cycle 747system.cpu.commit.committed_per_cycle::mean 0.422036 # Number of insts commited each cycle 748system.cpu.commit.committed_per_cycle::stdev 1.264076 # Number of insts commited each cycle |
| 749system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 749system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 750system.cpu.commit.committed_per_cycle::0 10636 83.87% 83.87% # Number of insts commited each cycle 751system.cpu.commit.committed_per_cycle::1 879 6.93% 90.80% # Number of insts commited each cycle 752system.cpu.commit.committed_per_cycle::2 416 3.28% 94.08% # Number of insts commited each cycle 753system.cpu.commit.committed_per_cycle::3 218 1.72% 95.80% # Number of insts commited each cycle 754system.cpu.commit.committed_per_cycle::4 111 0.88% 96.67% # Number of insts commited each cycle | 750system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% # Number of insts commited each cycle 751system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% # Number of insts commited each cycle 752system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% # Number of insts commited each cycle 753system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% # Number of insts commited each cycle 754system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% # Number of insts commited each cycle |
| 755system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle | 755system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle |
| 756system.cpu.commit.committed_per_cycle::6 54 0.43% 98.83% # Number of insts commited each cycle | 756system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% # Number of insts commited each cycle |
| 757system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle 758system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle 759system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 760system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 761system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 757system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle 758system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle 759system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 760system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 761system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 762system.cpu.commit.committed_per_cycle::total 12682 # Number of insts commited each cycle | 762system.cpu.commit.committed_per_cycle::total 12743 # Number of insts commited each cycle |
| 763system.cpu.commit.committedInsts 4592 # Number of instructions committed 764system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 765system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 766system.cpu.commit.refs 1965 # Number of memory references committed 767system.cpu.commit.loads 1027 # Number of loads committed 768system.cpu.commit.membars 12 # Number of memory barriers committed 769system.cpu.commit.branches 1008 # Number of branches committed 770system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 34 unchanged lines hidden (view full) --- 805system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 806system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction 807system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction 808system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction 809system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 810system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 811system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 812system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached | 763system.cpu.commit.committedInsts 4592 # Number of instructions committed 764system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 765system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 766system.cpu.commit.refs 1965 # Number of memory references committed 767system.cpu.commit.loads 1027 # Number of loads committed 768system.cpu.commit.membars 12 # Number of memory barriers committed 769system.cpu.commit.branches 1008 # Number of branches committed 770system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 34 unchanged lines hidden (view full) --- 805system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 806system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction 807system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction 808system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction 809system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 810system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 811system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 812system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached |
| 813system.cpu.rob.rob_reads 22637 # The number of ROB reads 814system.cpu.rob.rob_writes 21308 # The number of ROB writes 815system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself 816system.cpu.idleCycles 23311 # Total number of cycles that the CPU has spent unscheduled due to idling | 813system.cpu.rob.rob_reads 22825 # The number of ROB reads 814system.cpu.rob.rob_writes 21580 # The number of ROB writes 815system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself 816system.cpu.idleCycles 23420 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 817system.cpu.committedInsts 4592 # Number of Instructions Simulated 818system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated | 817system.cpu.committedInsts 4592 # Number of Instructions Simulated 818system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated |
| 819system.cpu.cpi 8.023955 # CPI: Cycles Per Instruction 820system.cpu.cpi_total 8.023955 # CPI: Total CPI of All Threads 821system.cpu.ipc 0.124627 # IPC: Instructions Per Cycle 822system.cpu.ipc_total 0.124627 # IPC: Total IPC of All Threads 823system.cpu.int_regfile_reads 7656 # number of integer regfile reads 824system.cpu.int_regfile_writes 4268 # number of integer regfile writes | 819system.cpu.cpi 8.065331 # CPI: Cycles Per Instruction 820system.cpu.cpi_total 8.065331 # CPI: Total CPI of All Threads 821system.cpu.ipc 0.123987 # IPC: Instructions Per Cycle 822system.cpu.ipc_total 0.123987 # IPC: Total IPC of All Threads 823system.cpu.int_regfile_reads 7779 # number of integer regfile reads 824system.cpu.int_regfile_writes 4297 # number of integer regfile writes |
| 825system.cpu.fp_regfile_reads 32 # number of floating regfile reads | 825system.cpu.fp_regfile_reads 32 # number of floating regfile reads |
| 826system.cpu.cc_regfile_reads 27780 # number of cc regfile reads 827system.cpu.cc_regfile_writes 3273 # number of cc regfile writes 828system.cpu.misc_regfile_reads 2974 # number of misc regfile reads | 826system.cpu.cc_regfile_reads 28140 # number of cc regfile reads 827system.cpu.cc_regfile_writes 3276 # number of cc regfile writes 828system.cpu.misc_regfile_reads 3029 # number of misc regfile reads |
| 829system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 829system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 830system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 830system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 831system.cpu.dcache.tags.replacements 0 # number of replacements | 831system.cpu.dcache.tags.replacements 0 # number of replacements |
| 832system.cpu.dcache.tags.tagsinuse 88.014551 # Cycle average of tags in use 833system.cpu.dcache.tags.total_refs 2093 # Total number of references to valid blocks. | 832system.cpu.dcache.tags.tagsinuse 87.889702 # Cycle average of tags in use 833system.cpu.dcache.tags.total_refs 2158 # Total number of references to valid blocks. |
| 834system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. | 834system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. |
| 835system.cpu.dcache.tags.avg_refs 14.238095 # Average number of references to valid blocks. | 835system.cpu.dcache.tags.avg_refs 14.680272 # Average number of references to valid blocks. |
| 836system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 836system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 837system.cpu.dcache.tags.occ_blocks::cpu.data 88.014551 # Average occupied blocks per requestor 838system.cpu.dcache.tags.occ_percent::cpu.data 0.021488 # Average percentage of cache occupancy 839system.cpu.dcache.tags.occ_percent::total 0.021488 # Average percentage of cache occupancy | 837system.cpu.dcache.tags.occ_blocks::cpu.data 87.889702 # Average occupied blocks per requestor 838system.cpu.dcache.tags.occ_percent::cpu.data 0.021457 # Average percentage of cache occupancy 839system.cpu.dcache.tags.occ_percent::total 0.021457 # Average percentage of cache occupancy |
| 840system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 841system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 842system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 843system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id | 840system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 841system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 842system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 843system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id |
| 844system.cpu.dcache.tags.tag_accesses 5335 # Number of tag accesses 845system.cpu.dcache.tags.data_accesses 5335 # Number of data accesses 846system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 847system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits 848system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits | 844system.cpu.dcache.tags.tag_accesses 5471 # Number of tag accesses 845system.cpu.dcache.tags.data_accesses 5471 # Number of data accesses 846system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states 847system.cpu.dcache.ReadReq_hits::cpu.data 1540 # number of ReadReq hits 848system.cpu.dcache.ReadReq_hits::total 1540 # number of ReadReq hits |
| 849system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 850system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 851system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 852system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 853system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 854system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits | 849system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 850system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 851system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 852system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 853system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 854system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| 855system.cpu.dcache.demand_hits::cpu.data 2072 # number of demand (read+write) hits 856system.cpu.dcache.demand_hits::total 2072 # number of demand (read+write) hits 857system.cpu.dcache.overall_hits::cpu.data 2072 # number of overall hits 858system.cpu.dcache.overall_hits::total 2072 # number of overall hits 859system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses 860system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses | 855system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits 856system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits 857system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits 858system.cpu.dcache.overall_hits::total 2137 # number of overall hits 859system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses 860system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses |
| 861system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 862system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 863system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 864system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 861system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 862system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 863system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 864system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 865system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses 866system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses 867system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses 868system.cpu.dcache.overall_misses::total 499 # number of overall misses 869system.cpu.dcache.ReadReq_miss_latency::cpu.data 11345000 # number of ReadReq miss cycles 870system.cpu.dcache.ReadReq_miss_latency::total 11345000 # number of ReadReq miss cycles 871system.cpu.dcache.WriteReq_miss_latency::cpu.data 24463500 # number of WriteReq miss cycles 872system.cpu.dcache.WriteReq_miss_latency::total 24463500 # number of WriteReq miss cycles | 865system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses 866system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses 867system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses 868system.cpu.dcache.overall_misses::total 502 # number of overall misses 869system.cpu.dcache.ReadReq_miss_latency::cpu.data 11381500 # number of ReadReq miss cycles 870system.cpu.dcache.ReadReq_miss_latency::total 11381500 # number of ReadReq miss cycles 871system.cpu.dcache.WriteReq_miss_latency::cpu.data 24478000 # number of WriteReq miss cycles 872system.cpu.dcache.WriteReq_miss_latency::total 24478000 # number of WriteReq miss cycles |
| 873system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles 874system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles | 873system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles 874system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles |
| 875system.cpu.dcache.demand_miss_latency::cpu.data 35808500 # number of demand (read+write) miss cycles 876system.cpu.dcache.demand_miss_latency::total 35808500 # number of demand (read+write) miss cycles 877system.cpu.dcache.overall_miss_latency::cpu.data 35808500 # number of overall miss cycles 878system.cpu.dcache.overall_miss_latency::total 35808500 # number of overall miss cycles 879system.cpu.dcache.ReadReq_accesses::cpu.data 1658 # number of ReadReq accesses(hits+misses) 880system.cpu.dcache.ReadReq_accesses::total 1658 # number of ReadReq accesses(hits+misses) | 875system.cpu.dcache.demand_miss_latency::cpu.data 35859500 # number of demand (read+write) miss cycles 876system.cpu.dcache.demand_miss_latency::total 35859500 # number of demand (read+write) miss cycles 877system.cpu.dcache.overall_miss_latency::cpu.data 35859500 # number of overall miss cycles 878system.cpu.dcache.overall_miss_latency::total 35859500 # number of overall miss cycles 879system.cpu.dcache.ReadReq_accesses::cpu.data 1726 # number of ReadReq accesses(hits+misses) 880system.cpu.dcache.ReadReq_accesses::total 1726 # number of ReadReq accesses(hits+misses) |
| 881system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 882system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 883system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 884system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 885system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 886system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 881system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 882system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 883system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 884system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 885system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 886system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 887system.cpu.dcache.demand_accesses::cpu.data 2571 # number of demand (read+write) accesses 888system.cpu.dcache.demand_accesses::total 2571 # number of demand (read+write) accesses 889system.cpu.dcache.overall_accesses::cpu.data 2571 # number of overall (read+write) accesses 890system.cpu.dcache.overall_accesses::total 2571 # number of overall (read+write) accesses 891system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110374 # miss rate for ReadReq accesses 892system.cpu.dcache.ReadReq_miss_rate::total 0.110374 # miss rate for ReadReq accesses | 887system.cpu.dcache.demand_accesses::cpu.data 2639 # number of demand (read+write) accesses 888system.cpu.dcache.demand_accesses::total 2639 # number of demand (read+write) accesses 889system.cpu.dcache.overall_accesses::cpu.data 2639 # number of overall (read+write) accesses 890system.cpu.dcache.overall_accesses::total 2639 # number of overall (read+write) accesses 891system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107764 # miss rate for ReadReq accesses 892system.cpu.dcache.ReadReq_miss_rate::total 0.107764 # miss rate for ReadReq accesses |
| 893system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 894system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 895system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 896system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses | 893system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 894system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 895system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 896system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses |
| 897system.cpu.dcache.demand_miss_rate::cpu.data 0.194088 # miss rate for demand accesses 898system.cpu.dcache.demand_miss_rate::total 0.194088 # miss rate for demand accesses 899system.cpu.dcache.overall_miss_rate::cpu.data 0.194088 # miss rate for overall accesses 900system.cpu.dcache.overall_miss_rate::total 0.194088 # miss rate for overall accesses 901system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519 # average ReadReq miss latency 902system.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519 # average ReadReq miss latency 903system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241 # average WriteReq miss latency 904system.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241 # average WriteReq miss latency | 897system.cpu.dcache.demand_miss_rate::cpu.data 0.190224 # miss rate for demand accesses 898system.cpu.dcache.demand_miss_rate::total 0.190224 # miss rate for demand accesses 899system.cpu.dcache.overall_miss_rate::cpu.data 0.190224 # miss rate for overall accesses 900system.cpu.dcache.overall_miss_rate::total 0.190224 # miss rate for overall accesses 901system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61190.860215 # average ReadReq miss latency 902system.cpu.dcache.ReadReq_avg_miss_latency::total 61190.860215 # average ReadReq miss latency 903system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77462.025316 # average WriteReq miss latency 904system.cpu.dcache.WriteReq_avg_miss_latency::total 77462.025316 # average WriteReq miss latency |
| 905system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency 906system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency | 905system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency 906system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency |
| 907system.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency 908system.cpu.dcache.demand_avg_miss_latency::total 71760.521042 # average overall miss latency 909system.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency 910system.cpu.dcache.overall_avg_miss_latency::total 71760.521042 # average overall miss latency | 907system.cpu.dcache.demand_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency 908system.cpu.dcache.demand_avg_miss_latency::total 71433.266932 # average overall miss latency 909system.cpu.dcache.overall_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency 910system.cpu.dcache.overall_avg_miss_latency::total 71433.266932 # average overall miss latency |
| 911system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked 912system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 913system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 914system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 915system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked 916system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 911system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked 912system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 913system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 914system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 915system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked 916system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 917system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 918system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits | 917system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits 918system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits |
| 919system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 920system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 921system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 922system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 919system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 920system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 921system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 922system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 923system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 924system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits 925system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits 926system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits | 923system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 924system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 925system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 926system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits |
| 927system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 928system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 929system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 930system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 931system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 932system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 933system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 934system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses | 927system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 928system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 929system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 930system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 931system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 932system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 933system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 934system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses |
| 935system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7355500 # number of ReadReq MSHR miss cycles 936system.cpu.dcache.ReadReq_mshr_miss_latency::total 7355500 # number of ReadReq MSHR miss cycles | 935system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7338000 # number of ReadReq MSHR miss cycles 936system.cpu.dcache.ReadReq_mshr_miss_latency::total 7338000 # number of ReadReq MSHR miss cycles |
| 937system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles 938system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles | 937system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles 938system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles |
| 939system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11023500 # number of demand (read+write) MSHR miss cycles 940system.cpu.dcache.demand_mshr_miss_latency::total 11023500 # number of demand (read+write) MSHR miss cycles 941system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11023500 # number of overall MSHR miss cycles 942system.cpu.dcache.overall_mshr_miss_latency::total 11023500 # number of overall MSHR miss cycles 943system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063329 # mshr miss rate for ReadReq accesses 944system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063329 # mshr miss rate for ReadReq accesses | 939system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11006000 # number of demand (read+write) MSHR miss cycles 940system.cpu.dcache.demand_mshr_miss_latency::total 11006000 # number of demand (read+write) MSHR miss cycles 941system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11006000 # number of overall MSHR miss cycles 942system.cpu.dcache.overall_mshr_miss_latency::total 11006000 # number of overall MSHR miss cycles 943system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060834 # mshr miss rate for ReadReq accesses 944system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060834 # mshr miss rate for ReadReq accesses |
| 945system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 946system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses | 945system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 946system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses |
| 947system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for demand accesses 948system.cpu.dcache.demand_mshr_miss_rate::total 0.057176 # mshr miss rate for demand accesses 949system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for overall accesses 950system.cpu.dcache.overall_mshr_miss_rate::total 0.057176 # mshr miss rate for overall accesses 951system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952 # average ReadReq mshr miss latency 952system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952 # average ReadReq mshr miss latency | 947system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for demand accesses 948system.cpu.dcache.demand_mshr_miss_rate::total 0.055703 # mshr miss rate for demand accesses 949system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for overall accesses 950system.cpu.dcache.overall_mshr_miss_rate::total 0.055703 # mshr miss rate for overall accesses 951system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69885.714286 # average ReadReq mshr miss latency 952system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69885.714286 # average ReadReq mshr miss latency |
| 953system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency 954system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency | 953system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency 954system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency |
| 955system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency 956system.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency 957system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency 958system.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency 959system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 955system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency 956system.cpu.dcache.demand_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency 957system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency 958system.cpu.dcache.overall_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency 959system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 960system.cpu.icache.tags.replacements 2 # number of replacements | 960system.cpu.icache.tags.replacements 2 # number of replacements |
| 961system.cpu.icache.tags.tagsinuse 149.507349 # Cycle average of tags in use 962system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. 963system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 964system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. | 961system.cpu.icache.tags.tagsinuse 148.671994 # Cycle average of tags in use 962system.cpu.icache.tags.total_refs 1587 # Total number of references to valid blocks. 963system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. 964system.cpu.icache.tags.avg_refs 5.416382 # Average number of references to valid blocks. |
| 965system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 965system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 966system.cpu.icache.tags.occ_blocks::cpu.inst 149.507349 # Average occupied blocks per requestor 967system.cpu.icache.tags.occ_percent::cpu.inst 0.073002 # Average percentage of cache occupancy 968system.cpu.icache.tags.occ_percent::total 0.073002 # Average percentage of cache occupancy 969system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 970system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id | 966system.cpu.icache.tags.occ_blocks::cpu.inst 148.671994 # Average occupied blocks per requestor 967system.cpu.icache.tags.occ_percent::cpu.inst 0.072594 # Average percentage of cache occupancy 968system.cpu.icache.tags.occ_percent::total 0.072594 # Average percentage of cache occupancy 969system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id 970system.cpu.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id |
| 971system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id | 971system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id |
| 972system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 973system.cpu.icache.tags.tag_accesses 4218 # Number of tag accesses 974system.cpu.icache.tags.data_accesses 4218 # Number of data accesses 975system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 976system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits 977system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits 978system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits 979system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits 980system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits 981system.cpu.icache.overall_hits::total 1577 # number of overall hits 982system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 983system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses 984system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses 985system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses 986system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses 987system.cpu.icache.overall_misses::total 385 # number of overall misses 988system.cpu.icache.ReadReq_miss_latency::cpu.inst 28997500 # number of ReadReq miss cycles 989system.cpu.icache.ReadReq_miss_latency::total 28997500 # number of ReadReq miss cycles 990system.cpu.icache.demand_miss_latency::cpu.inst 28997500 # number of demand (read+write) miss cycles 991system.cpu.icache.demand_miss_latency::total 28997500 # number of demand (read+write) miss cycles 992system.cpu.icache.overall_miss_latency::cpu.inst 28997500 # number of overall miss cycles 993system.cpu.icache.overall_miss_latency::total 28997500 # number of overall miss cycles 994system.cpu.icache.ReadReq_accesses::cpu.inst 1962 # number of ReadReq accesses(hits+misses) 995system.cpu.icache.ReadReq_accesses::total 1962 # number of ReadReq accesses(hits+misses) 996system.cpu.icache.demand_accesses::cpu.inst 1962 # number of demand (read+write) accesses 997system.cpu.icache.demand_accesses::total 1962 # number of demand (read+write) accesses 998system.cpu.icache.overall_accesses::cpu.inst 1962 # number of overall (read+write) accesses 999system.cpu.icache.overall_accesses::total 1962 # number of overall (read+write) accesses 1000system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196228 # miss rate for ReadReq accesses 1001system.cpu.icache.ReadReq_miss_rate::total 0.196228 # miss rate for ReadReq accesses 1002system.cpu.icache.demand_miss_rate::cpu.inst 0.196228 # miss rate for demand accesses 1003system.cpu.icache.demand_miss_rate::total 0.196228 # miss rate for demand accesses 1004system.cpu.icache.overall_miss_rate::cpu.inst 0.196228 # miss rate for overall accesses 1005system.cpu.icache.overall_miss_rate::total 0.196228 # miss rate for overall accesses 1006system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75318.181818 # average ReadReq miss latency 1007system.cpu.icache.ReadReq_avg_miss_latency::total 75318.181818 # average ReadReq miss latency 1008system.cpu.icache.demand_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency 1009system.cpu.icache.demand_avg_miss_latency::total 75318.181818 # average overall miss latency 1010system.cpu.icache.overall_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency 1011system.cpu.icache.overall_avg_miss_latency::total 75318.181818 # average overall miss latency 1012system.cpu.icache.blocked_cycles::no_mshrs 493 # number of cycles access was blocked | 972system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id 973system.cpu.icache.tags.tag_accesses 4257 # Number of tag accesses 974system.cpu.icache.tags.data_accesses 4257 # Number of data accesses 975system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states 976system.cpu.icache.ReadReq_hits::cpu.inst 1587 # number of ReadReq hits 977system.cpu.icache.ReadReq_hits::total 1587 # number of ReadReq hits 978system.cpu.icache.demand_hits::cpu.inst 1587 # number of demand (read+write) hits 979system.cpu.icache.demand_hits::total 1587 # number of demand (read+write) hits 980system.cpu.icache.overall_hits::cpu.inst 1587 # number of overall hits 981system.cpu.icache.overall_hits::total 1587 # number of overall hits 982system.cpu.icache.ReadReq_misses::cpu.inst 395 # number of ReadReq misses 983system.cpu.icache.ReadReq_misses::total 395 # number of ReadReq misses 984system.cpu.icache.demand_misses::cpu.inst 395 # number of demand (read+write) misses 985system.cpu.icache.demand_misses::total 395 # number of demand (read+write) misses 986system.cpu.icache.overall_misses::cpu.inst 395 # number of overall misses 987system.cpu.icache.overall_misses::total 395 # number of overall misses 988system.cpu.icache.ReadReq_miss_latency::cpu.inst 29663500 # number of ReadReq miss cycles 989system.cpu.icache.ReadReq_miss_latency::total 29663500 # number of ReadReq miss cycles 990system.cpu.icache.demand_miss_latency::cpu.inst 29663500 # number of demand (read+write) miss cycles 991system.cpu.icache.demand_miss_latency::total 29663500 # number of demand (read+write) miss cycles 992system.cpu.icache.overall_miss_latency::cpu.inst 29663500 # number of overall miss cycles 993system.cpu.icache.overall_miss_latency::total 29663500 # number of overall miss cycles 994system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses) 995system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) 996system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses 997system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses 998system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses 999system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses 1000system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199294 # miss rate for ReadReq accesses 1001system.cpu.icache.ReadReq_miss_rate::total 0.199294 # miss rate for ReadReq accesses 1002system.cpu.icache.demand_miss_rate::cpu.inst 0.199294 # miss rate for demand accesses 1003system.cpu.icache.demand_miss_rate::total 0.199294 # miss rate for demand accesses 1004system.cpu.icache.overall_miss_rate::cpu.inst 0.199294 # miss rate for overall accesses 1005system.cpu.icache.overall_miss_rate::total 0.199294 # miss rate for overall accesses 1006system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75097.468354 # average ReadReq miss latency 1007system.cpu.icache.ReadReq_avg_miss_latency::total 75097.468354 # average ReadReq miss latency 1008system.cpu.icache.demand_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency 1009system.cpu.icache.demand_avg_miss_latency::total 75097.468354 # average overall miss latency 1010system.cpu.icache.overall_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency 1011system.cpu.icache.overall_avg_miss_latency::total 75097.468354 # average overall miss latency 1012system.cpu.icache.blocked_cycles::no_mshrs 422 # number of cycles access was blocked |
| 1013system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1013system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1014system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked | 1014system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked |
| 1015system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 1015system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1016system.cpu.icache.avg_blocked_cycles::no_mshrs 98.600000 # average number of cycles each access was blocked | 1016system.cpu.icache.avg_blocked_cycles::no_mshrs 105.500000 # average number of cycles each access was blocked |
| 1017system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1018system.cpu.icache.writebacks::writebacks 2 # number of writebacks 1019system.cpu.icache.writebacks::total 2 # number of writebacks | 1017system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1018system.cpu.icache.writebacks::writebacks 2 # number of writebacks 1019system.cpu.icache.writebacks::total 2 # number of writebacks |
| 1020system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits 1021system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits 1022system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits 1023system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits 1024system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits 1025system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits 1026system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 1027system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 1028system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 1029system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 1030system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 1031system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses 1032system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23482000 # number of ReadReq MSHR miss cycles 1033system.cpu.icache.ReadReq_mshr_miss_latency::total 23482000 # number of ReadReq MSHR miss cycles 1034system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23482000 # number of demand (read+write) MSHR miss cycles 1035system.cpu.icache.demand_mshr_miss_latency::total 23482000 # number of demand (read+write) MSHR miss cycles 1036system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23482000 # number of overall MSHR miss cycles 1037system.cpu.icache.overall_mshr_miss_latency::total 23482000 # number of overall MSHR miss cycles 1038system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for ReadReq accesses 1039system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149847 # mshr miss rate for ReadReq accesses 1040system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for demand accesses 1041system.cpu.icache.demand_mshr_miss_rate::total 0.149847 # mshr miss rate for demand accesses 1042system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for overall accesses 1043system.cpu.icache.overall_mshr_miss_rate::total 0.149847 # mshr miss rate for overall accesses 1044system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79870.748299 # average ReadReq mshr miss latency 1045system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79870.748299 # average ReadReq mshr miss latency 1046system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency 1047system.cpu.icache.demand_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency 1048system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency 1049system.cpu.icache.overall_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency 1050system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 1020system.cpu.icache.ReadReq_mshr_hits::cpu.inst 102 # number of ReadReq MSHR hits 1021system.cpu.icache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits 1022system.cpu.icache.demand_mshr_hits::cpu.inst 102 # number of demand (read+write) MSHR hits 1023system.cpu.icache.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits 1024system.cpu.icache.overall_mshr_hits::cpu.inst 102 # number of overall MSHR hits 1025system.cpu.icache.overall_mshr_hits::total 102 # number of overall MSHR hits 1026system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses 1027system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses 1028system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 1029system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses 1030system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 1031system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses 1032system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23439000 # number of ReadReq MSHR miss cycles 1033system.cpu.icache.ReadReq_mshr_miss_latency::total 23439000 # number of ReadReq MSHR miss cycles 1034system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23439000 # number of demand (read+write) MSHR miss cycles 1035system.cpu.icache.demand_mshr_miss_latency::total 23439000 # number of demand (read+write) MSHR miss cycles 1036system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23439000 # number of overall MSHR miss cycles 1037system.cpu.icache.overall_mshr_miss_latency::total 23439000 # number of overall MSHR miss cycles 1038system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for ReadReq accesses 1039system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147830 # mshr miss rate for ReadReq accesses 1040system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for demand accesses 1041system.cpu.icache.demand_mshr_miss_rate::total 0.147830 # mshr miss rate for demand accesses 1042system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for overall accesses 1043system.cpu.icache.overall_mshr_miss_rate::total 0.147830 # mshr miss rate for overall accesses 1044system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79996.587031 # average ReadReq mshr miss latency 1045system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79996.587031 # average ReadReq mshr miss latency 1046system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency 1047system.cpu.icache.demand_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency 1048system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency 1049system.cpu.icache.overall_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency 1050system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 1051system.cpu.l2cache.tags.replacements 0 # number of replacements | 1051system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 1052system.cpu.l2cache.tags.tagsinuse 214.408451 # Cycle average of tags in use | 1052system.cpu.l2cache.tags.tagsinuse 213.492112 # Cycle average of tags in use |
| 1053system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. | 1053system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. |
| 1054system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 1055system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. | 1054system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. 1055system.cpu.l2cache.tags.avg_refs 0.098485 # Average number of references to valid blocks. |
| 1056system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1056system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1057system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.281348 # Average occupied blocks per requestor 1058system.cpu.l2cache.tags.occ_blocks::cpu.data 74.127103 # Average occupied blocks per requestor 1059system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004281 # Average percentage of cache occupancy 1060system.cpu.l2cache.tags.occ_percent::cpu.data 0.002262 # Average percentage of cache occupancy 1061system.cpu.l2cache.tags.occ_percent::total 0.006543 # Average percentage of cache occupancy 1062system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id 1063system.cpu.l2cache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id | 1057system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.462705 # Average occupied blocks per requestor 1058system.cpu.l2cache.tags.occ_blocks::cpu.data 74.029407 # Average occupied blocks per requestor 1059system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004256 # Average percentage of cache occupancy 1060system.cpu.l2cache.tags.occ_percent::cpu.data 0.002259 # Average percentage of cache occupancy 1061system.cpu.l2cache.tags.occ_percent::total 0.006515 # Average percentage of cache occupancy 1062system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id 1063system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id |
| 1064system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id | 1064system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id |
| 1065system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 1066system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses 1067system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses 1068system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states | 1065system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id 1066system.cpu.l2cache.tags.tag_accesses 3924 # Number of tag accesses 1067system.cpu.l2cache.tags.data_accesses 3924 # Number of data accesses 1068system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states |
| 1069system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 1070system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 1071system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 1072system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 1073system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 1074system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 1075system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 1076system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 1077system.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits 1078system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits 1079system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 1080system.cpu.l2cache.overall_hits::total 38 # number of overall hits 1081system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 1082system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses | 1069system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 1070system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 1071system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 1072system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 1073system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 1074system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 1075system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 1076system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 1077system.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits 1078system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits 1079system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 1080system.cpu.l2cache.overall_hits::total 38 # number of overall hits 1081system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 1082system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses |
| 1083system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses 1084system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses | 1083system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses 1084system.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses |
| 1085system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses 1086system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses | 1085system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses 1086system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses |
| 1087system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses | 1087system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses |
| 1088system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses | 1088system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses |
| 1089system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses 1090system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses | 1089system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses 1090system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses |
| 1091system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses | 1091system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses |
| 1092system.cpu.l2cache.overall_misses::total 403 # number of overall misses | 1092system.cpu.l2cache.overall_misses::total 402 # number of overall misses |
| 1093system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3603000 # number of ReadExReq miss cycles 1094system.cpu.l2cache.ReadExReq_miss_latency::total 3603000 # number of ReadExReq miss cycles | 1093system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3603000 # number of ReadExReq miss cycles 1094system.cpu.l2cache.ReadExReq_miss_latency::total 3603000 # number of ReadExReq miss cycles |
| 1095system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22833000 # number of ReadCleanReq miss cycles 1096system.cpu.l2cache.ReadCleanReq_miss_latency::total 22833000 # number of ReadCleanReq miss cycles 1097system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6961000 # number of ReadSharedReq miss cycles 1098system.cpu.l2cache.ReadSharedReq_miss_latency::total 6961000 # number of ReadSharedReq miss cycles 1099system.cpu.l2cache.demand_miss_latency::cpu.inst 22833000 # number of demand (read+write) miss cycles 1100system.cpu.l2cache.demand_miss_latency::cpu.data 10564000 # number of demand (read+write) miss cycles 1101system.cpu.l2cache.demand_miss_latency::total 33397000 # number of demand (read+write) miss cycles 1102system.cpu.l2cache.overall_miss_latency::cpu.inst 22833000 # number of overall miss cycles 1103system.cpu.l2cache.overall_miss_latency::cpu.data 10564000 # number of overall miss cycles 1104system.cpu.l2cache.overall_miss_latency::total 33397000 # number of overall miss cycles | 1095system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22791500 # number of ReadCleanReq miss cycles 1096system.cpu.l2cache.ReadCleanReq_miss_latency::total 22791500 # number of ReadCleanReq miss cycles 1097system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6943500 # number of ReadSharedReq miss cycles 1098system.cpu.l2cache.ReadSharedReq_miss_latency::total 6943500 # number of ReadSharedReq miss cycles 1099system.cpu.l2cache.demand_miss_latency::cpu.inst 22791500 # number of demand (read+write) miss cycles 1100system.cpu.l2cache.demand_miss_latency::cpu.data 10546500 # number of demand (read+write) miss cycles 1101system.cpu.l2cache.demand_miss_latency::total 33338000 # number of demand (read+write) miss cycles 1102system.cpu.l2cache.overall_miss_latency::cpu.inst 22791500 # number of overall miss cycles 1103system.cpu.l2cache.overall_miss_latency::cpu.data 10546500 # number of overall miss cycles 1104system.cpu.l2cache.overall_miss_latency::total 33338000 # number of overall miss cycles |
| 1105system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 1106system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 1107system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 1108system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) | 1105system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 1106system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 1107system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 1108system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) |
| 1109system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) 1110system.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) | 1109system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) 1110system.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses) |
| 1111system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) 1112system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) | 1111system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) 1112system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) |
| 1113system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses | 1113system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses |
| 1114system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses | 1114system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses |
| 1115system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 1116system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses | 1115system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses 1116system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses |
| 1117system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses | 1117system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses |
| 1118system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses | 1118system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses |
| 1119system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1120system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 1119system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1120system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 1121system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses 1122system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses | 1121system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses 1122system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses |
| 1123system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses 1124system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses | 1123system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses 1124system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses |
| 1125system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses | 1125system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses |
| 1126system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses | 1126system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses |
| 1127system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses 1128system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses | 1127system.cpu.l2cache.demand_miss_rate::total 0.913636 # miss rate for demand accesses 1128system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses |
| 1129system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses | 1129system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses |
| 1130system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses | 1130system.cpu.l2cache.overall_miss_rate::total 0.913636 # miss rate for overall accesses |
| 1131system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency 1132system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency | 1131system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency 1132system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency |
| 1133system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870 # average ReadCleanReq miss latency 1134system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82728.260870 # average ReadCleanReq miss latency 1135system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81894.117647 # average ReadSharedReq miss latency 1136system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81894.117647 # average ReadSharedReq miss latency 1137system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency 1138system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency 1139system.cpu.l2cache.demand_avg_miss_latency::total 82870.967742 # average overall miss latency 1140system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency 1141system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency 1142system.cpu.l2cache.overall_avg_miss_latency::total 82870.967742 # average overall miss latency | 1133system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82878.181818 # average ReadCleanReq miss latency 1134system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82878.181818 # average ReadCleanReq miss latency 1135system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.235294 # average ReadSharedReq miss latency 1136system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.235294 # average ReadSharedReq miss latency 1137system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency 1138system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency 1139system.cpu.l2cache.demand_avg_miss_latency::total 82930.348259 # average overall miss latency 1140system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency 1141system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency 1142system.cpu.l2cache.overall_avg_miss_latency::total 82930.348259 # average overall miss latency |
| 1143system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1144system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1145system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1146system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1147system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1148system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1149system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 1150system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 1151system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 1152system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1153system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 1154system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 1155system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 1156system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses | 1143system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1144system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1145system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1146system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1147system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1148system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1149system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 1150system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 1151system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 1152system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1153system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 1154system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 1155system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 1156system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses |
| 1157system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses 1158system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses | 1157system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses 1158system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses |
| 1159system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses 1160system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses | 1159system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses 1160system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses |
| 1161system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses | 1161system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses |
| 1162system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses | 1162system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses |
| 1163system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 1164system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses | 1163system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses 1164system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses |
| 1165system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses | 1165system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses |
| 1166system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses | 1166system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses |
| 1167system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles 1168system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles | 1167system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles 1168system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles |
| 1169system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20073000 # number of ReadCleanReq MSHR miss cycles 1170system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20073000 # number of ReadCleanReq MSHR miss cycles 1171system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5729500 # number of ReadSharedReq MSHR miss cycles 1172system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5729500 # number of ReadSharedReq MSHR miss cycles 1173system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20073000 # number of demand (read+write) MSHR miss cycles 1174system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912500 # number of demand (read+write) MSHR miss cycles 1175system.cpu.l2cache.demand_mshr_miss_latency::total 28985500 # number of demand (read+write) MSHR miss cycles 1176system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20073000 # number of overall MSHR miss cycles 1177system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912500 # number of overall MSHR miss cycles 1178system.cpu.l2cache.overall_mshr_miss_latency::total 28985500 # number of overall MSHR miss cycles | 1169system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 # number of ReadCleanReq MSHR miss cycles 1170system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 # number of ReadCleanReq MSHR miss cycles 1171system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 # number of ReadSharedReq MSHR miss cycles 1172system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 # number of ReadSharedReq MSHR miss cycles 1173system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 # number of demand (read+write) MSHR miss cycles 1174system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 # number of demand (read+write) MSHR miss cycles 1175system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 # number of demand (read+write) MSHR miss cycles 1176system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 # number of overall MSHR miss cycles 1177system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 # number of overall MSHR miss cycles 1178system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 # number of overall MSHR miss cycles |
| 1179system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1180system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 1179system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1180system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 1181system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses 1182system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses | 1181system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses 1182system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses |
| 1183system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses 1184system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses | 1183system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses 1184system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses |
| 1185system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses | 1185system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses |
| 1186system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses | 1186system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses |
| 1187system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 1188system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses | 1187system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses 1188system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses |
| 1189system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses | 1189system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses |
| 1190system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses | 1190system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses |
| 1191system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency 1192system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency | 1191system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency 1192system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency |
| 1193system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870 # average ReadCleanReq mshr miss latency 1194system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870 # average ReadCleanReq mshr miss latency 1195system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456 # average ReadSharedReq mshr miss latency 1196system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456 # average ReadSharedReq mshr miss latency 1197system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency 1198system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency 1199system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency 1200system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency 1201system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency 1202system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency 1203system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. | 1193system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 # average ReadCleanReq mshr miss latency 1194system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 # average ReadCleanReq mshr miss latency 1195system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 # average ReadSharedReq mshr miss latency 1196system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 # average ReadSharedReq mshr miss latency 1197system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency 1198system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency 1199system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency 1200system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency 1201system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency 1202system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency 1203system.cpu.toL2Bus.snoop_filter.tot_requests 442 # Total number of requests made to the snoop filter. |
| 1204system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1205system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1206system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1207system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1208system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1204system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1205system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1206system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1207system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1208system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1209system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 1210system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution | 1209system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states 1210system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution |
| 1211system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 1212system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution | 1211system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 1212system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution |
| 1214system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution | 1214system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution |
| 1215system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution | 1215system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution |
| 1216system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) | 1216system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) |
| 1217system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) | 1217system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) |
| 1218system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) 1219system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) | 1218system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) 1219system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) |
| 1220system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) | 1220system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) |
| 1221system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) | 1221system.cpu.toL2Bus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) |
| 1222system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1223system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 1222system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1223system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1224system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 1225system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram 1226system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram | 1224system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram 1225system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram 1226system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram |
| 1227system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1227system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1228system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram 1229system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram | 1228system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram 1229system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram |
| 1230system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1231system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1232system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1233system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1230system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1231system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1232system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1233system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1234system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 1235system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) | 1234system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram 1235system.cpu.toL2Bus.reqLayer0.occupancy 223000 # Layer occupancy (ticks) |
| 1236system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) | 1236system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) |
| 1237system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) | 1237system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) |
| 1238system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 1239system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) 1240system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) | 1238system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 1239system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) 1240system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) |
| 1241system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. | 1241system.membus.snoop_filter.tot_requests 396 # Total number of requests made to the snoop filter. |
| 1242system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1243system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1244system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1245system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1246system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1242system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1243system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1244system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1245system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1246system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1247system.membus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 1248system.membus.trans_dist::ReadResp 355 # Transaction distribution | 1247system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states 1248system.membus.trans_dist::ReadResp 354 # Transaction distribution |
| 1249system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1250system.membus.trans_dist::ReadExResp 42 # Transaction distribution | 1249system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1250system.membus.trans_dist::ReadExResp 42 # Transaction distribution |
| 1251system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution 1252system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 1253system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 1254system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 1255system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) | 1251system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution 1252system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) 1253system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) 1254system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) 1255system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) |
| 1256system.membus.snoops 0 # Total snoops (count) 1257system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1256system.membus.snoops 0 # Total snoops (count) 1257system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1258system.membus.snoop_fanout::samples 397 # Request fanout histogram | 1258system.membus.snoop_fanout::samples 396 # Request fanout histogram |
| 1259system.membus.snoop_fanout::mean 0 # Request fanout histogram 1260system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1261system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1259system.membus.snoop_fanout::mean 0 # Request fanout histogram 1260system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1261system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1262system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram | 1262system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram |
| 1263system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1264system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1265system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1266system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1263system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1264system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1265system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1266system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1267system.membus.snoop_fanout::total 397 # Request fanout histogram 1268system.membus.reqLayer0.occupancy 486500 # Layer occupancy (ticks) | 1267system.membus.snoop_fanout::total 396 # Request fanout histogram 1268system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) |
| 1269system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) | 1269system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) |
| 1270system.membus.respLayer1.occupancy 2098750 # Layer occupancy (ticks) 1271system.membus.respLayer1.utilization 11.4 # Layer utilization (%) | 1270system.membus.respLayer1.occupancy 2091500 # Layer occupancy (ticks) 1271system.membus.respLayer1.utilization 11.3 # Layer utilization (%) |
| 1272 1273---------- End Simulation Statistics ---------- | 1272 1273---------- End Simulation Statistics ---------- |