| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17458500 # Number of ticks simulated 5final_tick 17458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 18422500 # Number of ticks simulated 5final_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 52261 # Simulator instruction rate (inst/s) 8host_op_rate 61197 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 198636102 # Simulator tick rate (ticks/s) 10host_mem_usage 269760 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host | 7host_inst_rate 65137 # Simulator instruction rate (inst/s) 8host_op_rate 76274 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 261240377 # Simulator tick rate (ticks/s) 10host_mem_usage 268360 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host |
| 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 397 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 397 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 1011770771 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 443566171 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1455336942 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 1011770771 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 1011770771 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 1011770771 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 443566171 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1455336942 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 958827521 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 420355543 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1379183064 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 958827521 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 958827521 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 958827521 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 420355543 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1379183064 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 397 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 397 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 17373000 # Total gap between requests | 79system.physmem.totGap 18337000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 397 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 397 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 398.688525 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 264.215339 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 341.944807 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 12 19.67% 19.67% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 15 24.59% 44.26% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 9 14.75% 59.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 7 11.48% 70.49% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 3 4.92% 75.41% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 2 3.28% 78.69% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 3.28% 81.97% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 2 3.28% 85.25% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 14.75% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation 204system.physmem.totQLat 3455750 # Total ticks spent queuing 205system.physmem.totMemAccLat 10899500 # Total ticks spent from burst creation until serviced by the DRAM | 190system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 407.864407 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 273.934367 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 344.219630 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 10 16.95% 16.95% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 17 28.81% 45.76% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 8 13.56% 59.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 7 11.86% 71.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 2 3.39% 76.27% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 3 5.08% 81.36% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 5.08% 86.44% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 8 13.56% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation 204system.physmem.totQLat 5196750 # Total ticks spent queuing 205system.physmem.totMemAccLat 12640500 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 8704.66 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 13090.05 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 27454.66 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1455.34 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 31840.05 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1379.18 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1455.34 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 1379.18 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 11.37 # Data bus utilization in percentage 216system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 10.77 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.77 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 218system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing | 218system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing |
| 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 330 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 330 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 43760.71 # Average gap between requests | 224system.physmem.avgGap 46188.92 # Average gap between requests |
| 225system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined | 225system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined |
| 226system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) | 226system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 230system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 14349150 # Total energy per rank (pJ) 234system.physmem_0.averagePower 906.309806 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states | 230system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 3077430 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 36000 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 5255970 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 12170160 # Total energy per rank (pJ) 237system.physmem_0.averagePower 660.613923 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 11420000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states |
| 236system.physmem_0.memoryStateTime::REF 520000 # Time in different power states | 240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states |
| 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 238system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 240system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) | 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 53500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 6303750 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 11521750 # Time in different power states 245system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 749700 # Energy for read commands per rank (pJ) |
| 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 244system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 466500 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 12753765 # Total energy per rank (pJ) 248system.physmem_1.averagePower 805.416167 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 734500 # Time in different power states | 249system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 1466040 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 65760 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6124080 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 616800 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 10487985 # Total energy per rank (pJ) 256system.physmem_1.averagePower 569.303026 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 14986000 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states |
| 250system.physmem_1.memoryStateTime::REF 520000 # Time in different power states | 259system.physmem_1.memoryStateTime::REF 520000 # Time in different power states |
| 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 14593500 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 254system.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 2836 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted | 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 1605250 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 2751250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 13430000 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2844 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1749 # Number of conditional branches predicted |
| 257system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect | 267system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect |
| 258system.cpu.branchPred.BTBLookups 2400 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 864 # Number of BTB hits | 268system.cpu.branchPred.BTBLookups 2408 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 867 # Number of BTB hits |
| 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 261system.cpu.branchPred.BTBHitPct 36.000000 # BTB Hit Percentage | 271system.cpu.branchPred.BTBHitPct 36.004983 # BTB Hit Percentage |
| 262system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. | 272system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. |
| 264system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. | 274system.cpu.branchPred.indirectLookups 266 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 253 # Number of indirect misses. |
| 267system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks | 277system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 279system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 270system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 280system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 281system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 282system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 283system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 284system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 285system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 286system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 287system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 301system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 299system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 309system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 300system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 324system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 325system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.checker.dtb.hits 0 # DTB hits 327system.cpu.checker.dtb.misses 0 # DTB misses 328system.cpu.checker.dtb.accesses 0 # DTB accesses | 310system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 311system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 331system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 334system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 335system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 336system.cpu.checker.dtb.hits 0 # DTB hits 337system.cpu.checker.dtb.misses 0 # DTB misses 338system.cpu.checker.dtb.accesses 0 # DTB accesses |
| 329system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 339system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 330system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 340system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 361system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 359system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 369system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 360system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 361system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.checker.itb.read_accesses 0 # DTB read accesses 384system.cpu.checker.itb.write_accesses 0 # DTB write accesses 385system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.checker.itb.hits 0 # DTB hits 387system.cpu.checker.itb.misses 0 # DTB misses 388system.cpu.checker.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 13 # Number of system calls | 370system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 371system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 392system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.checker.itb.read_accesses 0 # DTB read accesses 394system.cpu.checker.itb.write_accesses 0 # DTB write accesses 395system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 396system.cpu.checker.itb.hits 0 # DTB hits 397system.cpu.checker.itb.misses 0 # DTB misses 398system.cpu.checker.itb.accesses 0 # DTB accesses 399system.cpu.workload.num_syscalls 13 # Number of system calls |
| 390system.cpu.checker.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states | 400system.cpu.checker.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states |
| 391system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 392system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed | 401system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 402system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 403system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 394system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 404system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 395system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 396system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 397system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 399system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 400system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 402system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 416system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 417system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 418system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 419system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 420system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 421system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 422system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 423system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 405system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 406system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 407system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 408system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 409system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 410system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 411system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 412system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 426system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 427system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 428system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 429system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 430system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 431system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 432system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 433system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 424system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 434system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 425system.cpu.dtb.walker.walks 0 # Table walker walks requested 426system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 430system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 432system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 446system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 448system.cpu.dtb.read_accesses 0 # DTB read accesses 449system.cpu.dtb.write_accesses 0 # DTB write accesses 450system.cpu.dtb.inst_accesses 0 # ITB inst accesses 451system.cpu.dtb.hits 0 # DTB hits 452system.cpu.dtb.misses 0 # DTB misses 453system.cpu.dtb.accesses 0 # DTB accesses | 435system.cpu.dtb.walker.walks 0 # Table walker walks requested 436system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 437system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 438system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 441system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 442system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 456system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 457system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458system.cpu.dtb.read_accesses 0 # DTB read accesses 459system.cpu.dtb.write_accesses 0 # DTB write accesses 460system.cpu.dtb.inst_accesses 0 # ITB inst accesses 461system.cpu.dtb.hits 0 # DTB hits 462system.cpu.dtb.misses 0 # DTB misses 463system.cpu.dtb.accesses 0 # DTB accesses |
| 454system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 464system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 455system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 462system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 476system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 478system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 479system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 480system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 481system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 482system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 483system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 465system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 472system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 486system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 487system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 488system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 489system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 490system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 491system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 492system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 493system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 484system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 494system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 485system.cpu.itb.walker.walks 0 # Table walker walks requested 486system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 487system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 488system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 489system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 490system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 491system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 492system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 506system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 507system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 508system.cpu.itb.read_accesses 0 # DTB read accesses 509system.cpu.itb.write_accesses 0 # DTB write accesses 510system.cpu.itb.inst_accesses 0 # ITB inst accesses 511system.cpu.itb.hits 0 # DTB hits 512system.cpu.itb.misses 0 # DTB misses 513system.cpu.itb.accesses 0 # DTB accesses | 495system.cpu.itb.walker.walks 0 # Table walker walks requested 496system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 498system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 501system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 516system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 517system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 518system.cpu.itb.read_accesses 0 # DTB read accesses 519system.cpu.itb.write_accesses 0 # DTB write accesses 520system.cpu.itb.inst_accesses 0 # ITB inst accesses 521system.cpu.itb.hits 0 # DTB hits 522system.cpu.itb.misses 0 # DTB misses 523system.cpu.itb.accesses 0 # DTB accesses |
| 514system.cpu.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states 515system.cpu.numCycles 34918 # number of cpu cycles simulated | 524system.cpu.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states 525system.cpu.numCycles 36846 # number of cpu cycles simulated |
| 516system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 517system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 526system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 527system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 518system.cpu.fetch.icacheStallCycles 7601 # Number of cycles fetch is stalled on an Icache miss 519system.cpu.fetch.Insts 12293 # Number of instructions fetch has processed 520system.cpu.fetch.Branches 2836 # Number of branches that fetch encountered 521system.cpu.fetch.predictedBranches 1192 # Number of branches that fetch has predicted taken 522system.cpu.fetch.Cycles 4902 # Number of cycles fetch has run and was not squashing or blocked | 528system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss 529system.cpu.fetch.Insts 12314 # Number of instructions fetch has processed 530system.cpu.fetch.Branches 2844 # Number of branches that fetch encountered 531system.cpu.fetch.predictedBranches 1194 # Number of branches that fetch has predicted taken 532system.cpu.fetch.Cycles 5108 # Number of cycles fetch has run and was not squashing or blocked |
| 523system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing 524system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 533system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing 534system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 525system.cpu.fetch.PendingTrapStallCycles 248 # Number of stall cycles due to pending traps | 535system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps |
| 526system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR | 536system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR |
| 527system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched | 537system.cpu.fetch.CacheLines 1962 # Number of cache lines fetched |
| 528system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed | 538system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed |
| 529system.cpu.fetch.rateDist::samples 13257 # Number of instructions fetched each cycle (Total) 530system.cpu.fetch.rateDist::mean 1.116542 # Number of instructions fetched each cycle (Total) 531system.cpu.fetch.rateDist::stdev 2.478893 # Number of instructions fetched each cycle (Total) | 539system.cpu.fetch.rateDist::samples 13535 # Number of instructions fetched each cycle (Total) 540system.cpu.fetch.rateDist::mean 1.094422 # Number of instructions fetched each cycle (Total) 541system.cpu.fetch.rateDist::stdev 2.458272 # Number of instructions fetched each cycle (Total) |
| 532system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 542system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 533system.cpu.fetch.rateDist::0 10565 79.69% 79.69% # Number of instructions fetched each cycle (Total) 534system.cpu.fetch.rateDist::1 264 1.99% 81.69% # Number of instructions fetched each cycle (Total) 535system.cpu.fetch.rateDist::2 184 1.39% 83.07% # Number of instructions fetched each cycle (Total) 536system.cpu.fetch.rateDist::3 203 1.53% 84.60% # Number of instructions fetched each cycle (Total) 537system.cpu.fetch.rateDist::4 282 2.13% 86.73% # Number of instructions fetched each cycle (Total) 538system.cpu.fetch.rateDist::5 396 2.99% 89.72% # Number of instructions fetched each cycle (Total) 539system.cpu.fetch.rateDist::6 139 1.05% 90.77% # Number of instructions fetched each cycle (Total) 540system.cpu.fetch.rateDist::7 173 1.30% 92.07% # Number of instructions fetched each cycle (Total) 541system.cpu.fetch.rateDist::8 1051 7.93% 100.00% # Number of instructions fetched each cycle (Total) | 543system.cpu.fetch.rateDist::0 10839 80.08% 80.08% # Number of instructions fetched each cycle (Total) 544system.cpu.fetch.rateDist::1 264 1.95% 82.03% # Number of instructions fetched each cycle (Total) 545system.cpu.fetch.rateDist::2 185 1.37% 83.40% # Number of instructions fetched each cycle (Total) 546system.cpu.fetch.rateDist::3 204 1.51% 84.91% # Number of instructions fetched each cycle (Total) 547system.cpu.fetch.rateDist::4 283 2.09% 87.00% # Number of instructions fetched each cycle (Total) 548system.cpu.fetch.rateDist::5 398 2.94% 89.94% # Number of instructions fetched each cycle (Total) 549system.cpu.fetch.rateDist::6 139 1.03% 90.96% # Number of instructions fetched each cycle (Total) 550system.cpu.fetch.rateDist::7 173 1.28% 92.24% # Number of instructions fetched each cycle (Total) 551system.cpu.fetch.rateDist::8 1050 7.76% 100.00% # Number of instructions fetched each cycle (Total) |
| 542system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 543system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 544system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 552system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 553system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 554system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 545system.cpu.fetch.rateDist::total 13257 # Number of instructions fetched each cycle (Total) 546system.cpu.fetch.branchRate 0.081219 # Number of branch fetches per cycle 547system.cpu.fetch.rate 0.352053 # Number of inst fetches per cycle 548system.cpu.decode.IdleCycles 6292 # Number of cycles decode is idle 549system.cpu.decode.BlockedCycles 4354 # Number of cycles decode is blocked 550system.cpu.decode.RunCycles 2143 # Number of cycles decode is running 551system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking | 555system.cpu.fetch.rateDist::total 13535 # Number of instructions fetched each cycle (Total) 556system.cpu.fetch.branchRate 0.077186 # Number of branch fetches per cycle 557system.cpu.fetch.rate 0.334202 # Number of inst fetches per cycle 558system.cpu.decode.IdleCycles 6279 # Number of cycles decode is idle 559system.cpu.decode.BlockedCycles 4644 # Number of cycles decode is blocked 560system.cpu.decode.RunCycles 2146 # Number of cycles decode is running 561system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking |
| 552system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing 553system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch 554system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction | 562system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing 563system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch 564system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction |
| 555system.cpu.decode.DecodedInsts 12137 # Number of instructions handled by decode | 565system.cpu.decode.DecodedInsts 12150 # Number of instructions handled by decode |
| 556system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode 557system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing | 566system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode 567system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing |
| 558system.cpu.rename.IdleCycles 6521 # Number of cycles rename is idle 559system.cpu.rename.BlockCycles 773 # Number of cycles rename is blocking 560system.cpu.rename.serializeStallCycles 2325 # count of cycles rename stalled for serializing inst 561system.cpu.rename.RunCycles 2036 # Number of cycles rename is running 562system.cpu.rename.UnblockCycles 1268 # Number of cycles rename is unblocking 563system.cpu.rename.RenamedInsts 11426 # Number of instructions processed by rename | 568system.cpu.rename.IdleCycles 6511 # Number of cycles rename is idle 569system.cpu.rename.BlockCycles 826 # Number of cycles rename is blocking 570system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst 571system.cpu.rename.RunCycles 2033 # Number of cycles rename is running 572system.cpu.rename.UnblockCycles 1361 # Number of cycles rename is unblocking 573system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename |
| 564system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full | 574system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full |
| 565system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full 566system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full 567system.cpu.rename.SQFullEvents 1090 # Number of times rename has blocked due to SQ full 568system.cpu.rename.RenamedOperands 11634 # Number of destination operands rename has renamed 569system.cpu.rename.RenameLookups 52309 # Number of register rename lookups that rename has made 570system.cpu.rename.int_rename_lookups 12345 # Number of integer rename lookups | 575system.cpu.rename.IQFullEvents 178 # Number of times rename has blocked due to IQ full 576system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full 577system.cpu.rename.SQFullEvents 1169 # Number of times rename has blocked due to SQ full 578system.cpu.rename.RenamedOperands 11641 # Number of destination operands rename has renamed 579system.cpu.rename.RenameLookups 52345 # Number of register rename lookups that rename has made 580system.cpu.rename.int_rename_lookups 12355 # Number of integer rename lookups |
| 571system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups 572system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed | 581system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups 582system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed |
| 573system.cpu.rename.UndoneMaps 6140 # Number of HB maps that are undone due to squashing | 583system.cpu.rename.UndoneMaps 6147 # Number of HB maps that are undone due to squashing |
| 574system.cpu.rename.serializingInsts 40 # count of serializing insts renamed 575system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed | 584system.cpu.rename.serializingInsts 40 # count of serializing insts renamed 585system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed |
| 576system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer 577system.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit. 578system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. 579system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. | 586system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer 587system.cpu.memDep0.insertedLoads 2197 # Number of loads inserted to the mem dependence unit. 588system.cpu.memDep0.insertedStores 1543 # Number of stores inserted to the mem dependence unit. 589system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. |
| 580system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. | 590system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. |
| 581system.cpu.iq.iqInstsAdded 10163 # Number of instructions added to the IQ (excludes non-spec) 582system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ 583system.cpu.iq.iqInstsIssued 8100 # Number of instructions issued 584system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued 585system.cpu.iq.iqSquashedInstsExamined 4828 # Number of squashed instructions iterated over during squash; mainly for profiling 586system.cpu.iq.iqSquashedOperandsExamined 12342 # Number of squashed operands that are examined and possibly removed from graph 587system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed 588system.cpu.iq.issued_per_cycle::samples 13257 # Number of insts issued each cycle 589system.cpu.iq.issued_per_cycle::mean 0.610998 # Number of insts issued each cycle 590system.cpu.iq.issued_per_cycle::stdev 1.340069 # Number of insts issued each cycle | 591system.cpu.iq.iqInstsAdded 10169 # Number of instructions added to the IQ (excludes non-spec) 592system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ 593system.cpu.iq.iqInstsIssued 8096 # Number of instructions issued 594system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued 595system.cpu.iq.iqSquashedInstsExamined 4835 # Number of squashed instructions iterated over during squash; mainly for profiling 596system.cpu.iq.iqSquashedOperandsExamined 12334 # Number of squashed operands that are examined and possibly removed from graph 597system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed 598system.cpu.iq.issued_per_cycle::samples 13535 # Number of insts issued each cycle 599system.cpu.iq.issued_per_cycle::mean 0.598153 # Number of insts issued each cycle 600system.cpu.iq.issued_per_cycle::stdev 1.329974 # Number of insts issued each cycle |
| 591system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 601system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 592system.cpu.iq.issued_per_cycle::0 10033 75.68% 75.68% # Number of insts issued each cycle 593system.cpu.iq.issued_per_cycle::1 1170 8.83% 84.51% # Number of insts issued each cycle 594system.cpu.iq.issued_per_cycle::2 770 5.81% 90.31% # Number of insts issued each cycle 595system.cpu.iq.issued_per_cycle::3 479 3.61% 93.93% # Number of insts issued each cycle 596system.cpu.iq.issued_per_cycle::4 341 2.57% 96.50% # Number of insts issued each cycle 597system.cpu.iq.issued_per_cycle::5 274 2.07% 98.57% # Number of insts issued each cycle 598system.cpu.iq.issued_per_cycle::6 121 0.91% 99.48% # Number of insts issued each cycle 599system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle 600system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle | 602system.cpu.iq.issued_per_cycle::0 10320 76.25% 76.25% # Number of insts issued each cycle 603system.cpu.iq.issued_per_cycle::1 1163 8.59% 84.84% # Number of insts issued each cycle 604system.cpu.iq.issued_per_cycle::2 763 5.64% 90.48% # Number of insts issued each cycle 605system.cpu.iq.issued_per_cycle::3 482 3.56% 94.04% # Number of insts issued each cycle 606system.cpu.iq.issued_per_cycle::4 344 2.54% 96.58% # Number of insts issued each cycle 607system.cpu.iq.issued_per_cycle::5 273 2.02% 98.60% # Number of insts issued each cycle 608system.cpu.iq.issued_per_cycle::6 120 0.89% 99.48% # Number of insts issued each cycle 609system.cpu.iq.issued_per_cycle::7 60 0.44% 99.93% # Number of insts issued each cycle 610system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle |
| 601system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 602system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 603system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 611system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 612system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 613system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 604system.cpu.iq.issued_per_cycle::total 13257 # Number of insts issued each cycle | 614system.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle |
| 605system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 615system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 606system.cpu.iq.fu_full::IntAlu 9 6.16% 6.16% # attempts to use FU when none available 607system.cpu.iq.fu_full::IntMult 0 0.00% 6.16% # attempts to use FU when none available 608system.cpu.iq.fu_full::IntDiv 0 0.00% 6.16% # attempts to use FU when none available 609system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.16% # attempts to use FU when none available 610system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.16% # attempts to use FU when none available 611system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.16% # attempts to use FU when none available 612system.cpu.iq.fu_full::FloatMult 0 0.00% 6.16% # attempts to use FU when none available 613system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.16% # attempts to use FU when none available 614system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.16% # attempts to use FU when none available 615system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.16% # attempts to use FU when none available 616system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.16% # attempts to use FU when none available 617system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.16% # attempts to use FU when none available 618system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.16% # attempts to use FU when none available 619system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.16% # attempts to use FU when none available 620system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.16% # attempts to use FU when none available 621system.cpu.iq.fu_full::SimdMult 0 0.00% 6.16% # attempts to use FU when none available 622system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.16% # attempts to use FU when none available 623system.cpu.iq.fu_full::SimdShift 0 0.00% 6.16% # attempts to use FU when none available 624system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.16% # attempts to use FU when none available 625system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.16% # attempts to use FU when none available 626system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.16% # attempts to use FU when none available 627system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.16% # attempts to use FU when none available 628system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.16% # attempts to use FU when none available 629system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.16% # attempts to use FU when none available 630system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.16% # attempts to use FU when none available 631system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.16% # attempts to use FU when none available 632system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.16% # attempts to use FU when none available 633system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.16% # attempts to use FU when none available 634system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.16% # attempts to use FU when none available 635system.cpu.iq.fu_full::MemRead 65 44.52% 50.68% # attempts to use FU when none available 636system.cpu.iq.fu_full::MemWrite 72 49.32% 100.00% # attempts to use FU when none available | 616system.cpu.iq.fu_full::IntAlu 9 6.12% 6.12% # attempts to use FU when none available 617system.cpu.iq.fu_full::IntMult 0 0.00% 6.12% # attempts to use FU when none available 618system.cpu.iq.fu_full::IntDiv 0 0.00% 6.12% # attempts to use FU when none available 619system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.12% # attempts to use FU when none available 620system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.12% # attempts to use FU when none available 621system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.12% # attempts to use FU when none available 622system.cpu.iq.fu_full::FloatMult 0 0.00% 6.12% # attempts to use FU when none available 623system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.12% # attempts to use FU when none available 624system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.12% # attempts to use FU when none available 625system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.12% # attempts to use FU when none available 626system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.12% # attempts to use FU when none available 627system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.12% # attempts to use FU when none available 628system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.12% # attempts to use FU when none available 629system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.12% # attempts to use FU when none available 630system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.12% # attempts to use FU when none available 631system.cpu.iq.fu_full::SimdMult 0 0.00% 6.12% # attempts to use FU when none available 632system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.12% # attempts to use FU when none available 633system.cpu.iq.fu_full::SimdShift 0 0.00% 6.12% # attempts to use FU when none available 634system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.12% # attempts to use FU when none available 635system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.12% # attempts to use FU when none available 636system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.12% # attempts to use FU when none available 637system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.12% # attempts to use FU when none available 638system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.12% # attempts to use FU when none available 639system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.12% # attempts to use FU when none available 640system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.12% # attempts to use FU when none available 641system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.12% # attempts to use FU when none available 642system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.12% # attempts to use FU when none available 643system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.12% # attempts to use FU when none available 644system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.12% # attempts to use FU when none available 645system.cpu.iq.fu_full::MemRead 66 44.90% 51.02% # attempts to use FU when none available 646system.cpu.iq.fu_full::MemWrite 72 48.98% 100.00% # attempts to use FU when none available |
| 637system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 638system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 639system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 647system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 648system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 649system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 640system.cpu.iq.FU_type_0::IntAlu 5026 62.05% 62.05% # Type of FU issued 641system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.14% # Type of FU issued 642system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued 643system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.14% # Type of FU issued 644system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.14% # Type of FU issued 645system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.14% # Type of FU issued 646system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.14% # Type of FU issued 647system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.14% # Type of FU issued 648system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.14% # Type of FU issued 649system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.14% # Type of FU issued 650system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.14% # Type of FU issued 651system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.14% # Type of FU issued 652system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.14% # Type of FU issued 653system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.14% # Type of FU issued 654system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.14% # Type of FU issued 655system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.14% # Type of FU issued 656system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.14% # Type of FU issued 657system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.14% # Type of FU issued 658system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.14% # Type of FU issued 659system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.14% # Type of FU issued 660system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.14% # Type of FU issued 661system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.14% # Type of FU issued 662system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.14% # Type of FU issued 663system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.14% # Type of FU issued 664system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.14% # Type of FU issued | 650system.cpu.iq.FU_type_0::IntAlu 5023 62.04% 62.04% # Type of FU issued 651system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued 652system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued 653system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued 654system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued 655system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued 656system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued 657system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued 658system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued 659system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued 660system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued 661system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued 662system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued 663system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued 664system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued 665system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued 666system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued 667system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued 668system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued 669system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued 670system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued 671system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued 672system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued 673system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued 674system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued |
| 665system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued 666system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued 667system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued 668system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued | 675system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued 676system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued 677system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued 678system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued |
| 669system.cpu.iq.FU_type_0::MemRead 1881 23.22% 85.40% # Type of FU issued 670system.cpu.iq.FU_type_0::MemWrite 1183 14.60% 100.00% # Type of FU issued | 679system.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued 680system.cpu.iq.FU_type_0::MemWrite 1187 14.66% 100.00% # Type of FU issued |
| 671system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 672system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 681system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 682system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 673system.cpu.iq.FU_type_0::total 8100 # Type of FU issued 674system.cpu.iq.rate 0.231972 # Inst issue rate 675system.cpu.iq.fu_busy_cnt 146 # FU busy when requested 676system.cpu.iq.fu_busy_rate 0.018025 # FU busy rate (busy events/executed inst) 677system.cpu.iq.int_inst_queue_reads 29552 # Number of integer instruction queue reads 678system.cpu.iq.int_inst_queue_writes 14921 # Number of integer instruction queue writes 679system.cpu.iq.int_inst_queue_wakeup_accesses 7399 # Number of integer instruction queue wakeup accesses | 683system.cpu.iq.FU_type_0::total 8096 # Type of FU issued 684system.cpu.iq.rate 0.219725 # Inst issue rate 685system.cpu.iq.fu_busy_cnt 147 # FU busy when requested 686system.cpu.iq.fu_busy_rate 0.018157 # FU busy rate (busy events/executed inst) 687system.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads 688system.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes 689system.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses |
| 680system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads 681system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes 682system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses | 690system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads 691system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes 692system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses |
| 683system.cpu.iq.int_alu_accesses 8203 # Number of integer alu accesses | 693system.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses |
| 684system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 685system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores 686system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 694system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 695system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores 696system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 687system.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed | 697system.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed |
| 688system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 689system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations | 698system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 699system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations |
| 690system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed | 700system.cpu.iew.lsq.thread0.squashedStores 605 # Number of stores squashed |
| 691system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 692system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 701system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 702system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 693system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled | 703system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled |
| 694system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 695system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 696system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing | 704system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 705system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 706system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing |
| 697system.cpu.iew.iewBlockCycles 684 # Number of cycles IEW is blocking | 707system.cpu.iew.iewBlockCycles 696 # Number of cycles IEW is blocking |
| 698system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking | 708system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking |
| 699system.cpu.iew.iewDispatchedInsts 10215 # Number of instructions dispatched to IQ 700system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch 701system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions 702system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions 703system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions | 709system.cpu.iew.iewDispatchedInsts 10222 # Number of instructions dispatched to IQ 710system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch 711system.cpu.iew.iewDispLoadInsts 2197 # Number of dispatched load instructions 712system.cpu.iew.iewDispStoreInsts 1543 # Number of dispatched store instructions 713system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions |
| 704system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 705system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 706system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 707system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly | 714system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 715system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 716system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 717system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly |
| 708system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly 709system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute 710system.cpu.iew.iewExecutedInsts 7807 # Number of executed instructions 711system.cpu.iew.iewExecLoadInsts 1773 # Number of load instructions executed 712system.cpu.iew.iewExecSquashedInsts 293 # Number of squashed instructions skipped in execute | 718system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly 719system.cpu.iew.branchMispredicts 356 # Number of branch mispredicts detected at execute 720system.cpu.iew.iewExecutedInsts 7806 # Number of executed instructions 721system.cpu.iew.iewExecLoadInsts 1768 # Number of load instructions executed 722system.cpu.iew.iewExecSquashedInsts 290 # Number of squashed instructions skipped in execute |
| 713system.cpu.iew.exec_swp 0 # number of swp insts executed 714system.cpu.iew.exec_nop 9 # number of nop insts executed | 723system.cpu.iew.exec_swp 0 # number of swp insts executed 724system.cpu.iew.exec_nop 9 # number of nop insts executed |
| 715system.cpu.iew.exec_refs 2920 # number of memory reference insts executed 716system.cpu.iew.exec_branches 1492 # Number of branches executed 717system.cpu.iew.exec_stores 1147 # Number of stores executed 718system.cpu.iew.exec_rate 0.223581 # Inst execution rate 719system.cpu.iew.wb_sent 7528 # cumulative count of insts sent to commit 720system.cpu.iew.wb_count 7431 # cumulative count of insts written-back 721system.cpu.iew.wb_producers 3502 # num instructions producing a value 722system.cpu.iew.wb_consumers 6830 # num instructions consuming a value 723system.cpu.iew.wb_rate 0.212813 # insts written-back per cycle 724system.cpu.iew.wb_fanout 0.512738 # average fanout of values written-back 725system.cpu.commit.commitSquashedInsts 4836 # The number of squashed insts skipped by commit | 725system.cpu.iew.exec_refs 2921 # number of memory reference insts executed 726system.cpu.iew.exec_branches 1491 # Number of branches executed 727system.cpu.iew.exec_stores 1153 # Number of stores executed 728system.cpu.iew.exec_rate 0.211855 # Inst execution rate 729system.cpu.iew.wb_sent 7533 # cumulative count of insts sent to commit 730system.cpu.iew.wb_count 7436 # cumulative count of insts written-back 731system.cpu.iew.wb_producers 3503 # num instructions producing a value 732system.cpu.iew.wb_consumers 6835 # num instructions consuming a value 733system.cpu.iew.wb_rate 0.201813 # insts written-back per cycle 734system.cpu.iew.wb_fanout 0.512509 # average fanout of values written-back 735system.cpu.commit.commitSquashedInsts 4843 # The number of squashed insts skipped by commit |
| 726system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 727system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted | 736system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 737system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted |
| 728system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle 729system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle 730system.cpu.commit.committed_per_cycle::stdev 1.278209 # Number of insts commited each cycle | 738system.cpu.commit.committed_per_cycle::samples 12682 # Number of insts commited each cycle 739system.cpu.commit.committed_per_cycle::mean 0.424066 # Number of insts commited each cycle 740system.cpu.commit.committed_per_cycle::stdev 1.266213 # Number of insts commited each cycle |
| 731system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 741system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 732system.cpu.commit.committed_per_cycle::0 10353 83.47% 83.47% # Number of insts commited each cycle 733system.cpu.commit.committed_per_cycle::1 884 7.13% 90.59% # Number of insts commited each cycle 734system.cpu.commit.committed_per_cycle::2 420 3.39% 93.98% # Number of insts commited each cycle 735system.cpu.commit.committed_per_cycle::3 217 1.75% 95.73% # Number of insts commited each cycle 736system.cpu.commit.committed_per_cycle::4 107 0.86% 96.59% # Number of insts commited each cycle 737system.cpu.commit.committed_per_cycle::5 220 1.77% 98.36% # Number of insts commited each cycle 738system.cpu.commit.committed_per_cycle::6 55 0.44% 98.81% # Number of insts commited each cycle 739system.cpu.commit.committed_per_cycle::7 39 0.31% 99.12% # Number of insts commited each cycle 740system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle | 742system.cpu.commit.committed_per_cycle::0 10636 83.87% 83.87% # Number of insts commited each cycle 743system.cpu.commit.committed_per_cycle::1 879 6.93% 90.80% # Number of insts commited each cycle 744system.cpu.commit.committed_per_cycle::2 416 3.28% 94.08% # Number of insts commited each cycle 745system.cpu.commit.committed_per_cycle::3 218 1.72% 95.80% # Number of insts commited each cycle 746system.cpu.commit.committed_per_cycle::4 111 0.88% 96.67% # Number of insts commited each cycle 747system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle 748system.cpu.commit.committed_per_cycle::6 54 0.43% 98.83% # Number of insts commited each cycle 749system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle 750system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle |
| 741system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 742system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 743system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 751system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 752system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 753system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 744system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle | 754system.cpu.commit.committed_per_cycle::total 12682 # Number of insts commited each cycle |
| 745system.cpu.commit.committedInsts 4592 # Number of instructions committed 746system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 747system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 748system.cpu.commit.refs 1965 # Number of memory references committed 749system.cpu.commit.loads 1027 # Number of loads committed 750system.cpu.commit.membars 12 # Number of memory barriers committed 751system.cpu.commit.branches 1008 # Number of branches committed 752system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 783system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 784system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 785system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 786system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 787system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 788system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 789system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 790system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached | 755system.cpu.commit.committedInsts 4592 # Number of instructions committed 756system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 757system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 758system.cpu.commit.refs 1965 # Number of memory references committed 759system.cpu.commit.loads 1027 # Number of loads committed 760system.cpu.commit.membars 12 # Number of memory barriers committed 761system.cpu.commit.branches 1008 # Number of branches committed 762system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 793system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 794system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 795system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 796system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 797system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 798system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 799system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 800system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached |
| 791system.cpu.rob.rob_reads 22352 # The number of ROB reads 792system.cpu.rob.rob_writes 21294 # The number of ROB writes | 801system.cpu.rob.rob_reads 22637 # The number of ROB reads 802system.cpu.rob.rob_writes 21308 # The number of ROB writes |
| 793system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself | 803system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 794system.cpu.idleCycles 21661 # Total number of cycles that the CPU has spent unscheduled due to idling | 804system.cpu.idleCycles 23311 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 795system.cpu.committedInsts 4592 # Number of Instructions Simulated 796system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated | 805system.cpu.committedInsts 4592 # Number of Instructions Simulated 806system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated |
| 797system.cpu.cpi 7.604094 # CPI: Cycles Per Instruction 798system.cpu.cpi_total 7.604094 # CPI: Total CPI of All Threads 799system.cpu.ipc 0.131508 # IPC: Instructions Per Cycle 800system.cpu.ipc_total 0.131508 # IPC: Total IPC of All Threads 801system.cpu.int_regfile_reads 7649 # number of integer regfile reads 802system.cpu.int_regfile_writes 4266 # number of integer regfile writes | 807system.cpu.cpi 8.023955 # CPI: Cycles Per Instruction 808system.cpu.cpi_total 8.023955 # CPI: Total CPI of All Threads 809system.cpu.ipc 0.124627 # IPC: Instructions Per Cycle 810system.cpu.ipc_total 0.124627 # IPC: Total IPC of All Threads 811system.cpu.int_regfile_reads 7656 # number of integer regfile reads 812system.cpu.int_regfile_writes 4268 # number of integer regfile writes |
| 803system.cpu.fp_regfile_reads 32 # number of floating regfile reads 804system.cpu.cc_regfile_reads 27780 # number of cc regfile reads 805system.cpu.cc_regfile_writes 3273 # number of cc regfile writes | 813system.cpu.fp_regfile_reads 32 # number of floating regfile reads 814system.cpu.cc_regfile_reads 27780 # number of cc regfile reads 815system.cpu.cc_regfile_writes 3273 # number of cc regfile writes |
| 806system.cpu.misc_regfile_reads 2976 # number of misc regfile reads | 816system.cpu.misc_regfile_reads 2974 # number of misc regfile reads |
| 807system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 817system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 808system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 818system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 809system.cpu.dcache.tags.replacements 0 # number of replacements | 819system.cpu.dcache.tags.replacements 0 # number of replacements |
| 810system.cpu.dcache.tags.tagsinuse 88.222961 # Cycle average of tags in use 811system.cpu.dcache.tags.total_refs 2096 # Total number of references to valid blocks. | 820system.cpu.dcache.tags.tagsinuse 88.014551 # Cycle average of tags in use 821system.cpu.dcache.tags.total_refs 2093 # Total number of references to valid blocks. |
| 812system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. | 822system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. |
| 813system.cpu.dcache.tags.avg_refs 14.258503 # Average number of references to valid blocks. | 823system.cpu.dcache.tags.avg_refs 14.238095 # Average number of references to valid blocks. |
| 814system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 824system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 815system.cpu.dcache.tags.occ_blocks::cpu.data 88.222961 # Average occupied blocks per requestor 816system.cpu.dcache.tags.occ_percent::cpu.data 0.021539 # Average percentage of cache occupancy 817system.cpu.dcache.tags.occ_percent::total 0.021539 # Average percentage of cache occupancy | 825system.cpu.dcache.tags.occ_blocks::cpu.data 88.014551 # Average occupied blocks per requestor 826system.cpu.dcache.tags.occ_percent::cpu.data 0.021488 # Average percentage of cache occupancy 827system.cpu.dcache.tags.occ_percent::total 0.021488 # Average percentage of cache occupancy |
| 818system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 819system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 820system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 821system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id | 828system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 829system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 830system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 831system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id |
| 822system.cpu.dcache.tags.tag_accesses 5341 # Number of tag accesses 823system.cpu.dcache.tags.data_accesses 5341 # Number of data accesses 824system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 825system.cpu.dcache.ReadReq_hits::cpu.data 1478 # number of ReadReq hits 826system.cpu.dcache.ReadReq_hits::total 1478 # number of ReadReq hits | 832system.cpu.dcache.tags.tag_accesses 5335 # Number of tag accesses 833system.cpu.dcache.tags.data_accesses 5335 # Number of data accesses 834system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 835system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits 836system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits |
| 827system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 828system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 829system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 830system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 831system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 832system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits | 837system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 838system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 839system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 840system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 841system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 842system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| 833system.cpu.dcache.demand_hits::cpu.data 2075 # number of demand (read+write) hits 834system.cpu.dcache.demand_hits::total 2075 # number of demand (read+write) hits 835system.cpu.dcache.overall_hits::cpu.data 2075 # number of overall hits 836system.cpu.dcache.overall_hits::total 2075 # number of overall hits | 843system.cpu.dcache.demand_hits::cpu.data 2072 # number of demand (read+write) hits 844system.cpu.dcache.demand_hits::total 2072 # number of demand (read+write) hits 845system.cpu.dcache.overall_hits::cpu.data 2072 # number of overall hits 846system.cpu.dcache.overall_hits::total 2072 # number of overall hits |
| 837system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses 838system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses 839system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 840system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 841system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 842system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 843system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses 844system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses 845system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses 846system.cpu.dcache.overall_misses::total 499 # number of overall misses | 847system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses 848system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses 849system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 850system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 851system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 852system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 853system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses 854system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses 855system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses 856system.cpu.dcache.overall_misses::total 499 # number of overall misses |
| 847system.cpu.dcache.ReadReq_miss_latency::cpu.data 10847000 # number of ReadReq miss cycles 848system.cpu.dcache.ReadReq_miss_latency::total 10847000 # number of ReadReq miss cycles 849system.cpu.dcache.WriteReq_miss_latency::cpu.data 22859500 # number of WriteReq miss cycles 850system.cpu.dcache.WriteReq_miss_latency::total 22859500 # number of WriteReq miss cycles 851system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144000 # number of LoadLockedReq miss cycles 852system.cpu.dcache.LoadLockedReq_miss_latency::total 144000 # number of LoadLockedReq miss cycles 853system.cpu.dcache.demand_miss_latency::cpu.data 33706500 # number of demand (read+write) miss cycles 854system.cpu.dcache.demand_miss_latency::total 33706500 # number of demand (read+write) miss cycles 855system.cpu.dcache.overall_miss_latency::cpu.data 33706500 # number of overall miss cycles 856system.cpu.dcache.overall_miss_latency::total 33706500 # number of overall miss cycles 857system.cpu.dcache.ReadReq_accesses::cpu.data 1661 # number of ReadReq accesses(hits+misses) 858system.cpu.dcache.ReadReq_accesses::total 1661 # number of ReadReq accesses(hits+misses) | 857system.cpu.dcache.ReadReq_miss_latency::cpu.data 11345000 # number of ReadReq miss cycles 858system.cpu.dcache.ReadReq_miss_latency::total 11345000 # number of ReadReq miss cycles 859system.cpu.dcache.WriteReq_miss_latency::cpu.data 24463500 # number of WriteReq miss cycles 860system.cpu.dcache.WriteReq_miss_latency::total 24463500 # number of WriteReq miss cycles 861system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles 862system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles 863system.cpu.dcache.demand_miss_latency::cpu.data 35808500 # number of demand (read+write) miss cycles 864system.cpu.dcache.demand_miss_latency::total 35808500 # number of demand (read+write) miss cycles 865system.cpu.dcache.overall_miss_latency::cpu.data 35808500 # number of overall miss cycles 866system.cpu.dcache.overall_miss_latency::total 35808500 # number of overall miss cycles 867system.cpu.dcache.ReadReq_accesses::cpu.data 1658 # number of ReadReq accesses(hits+misses) 868system.cpu.dcache.ReadReq_accesses::total 1658 # number of ReadReq accesses(hits+misses) |
| 859system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 860system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 861system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 862system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 863system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 864system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 869system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 870system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 871system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 872system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 873system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 874system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 865system.cpu.dcache.demand_accesses::cpu.data 2574 # number of demand (read+write) accesses 866system.cpu.dcache.demand_accesses::total 2574 # number of demand (read+write) accesses 867system.cpu.dcache.overall_accesses::cpu.data 2574 # number of overall (read+write) accesses 868system.cpu.dcache.overall_accesses::total 2574 # number of overall (read+write) accesses 869system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110175 # miss rate for ReadReq accesses 870system.cpu.dcache.ReadReq_miss_rate::total 0.110175 # miss rate for ReadReq accesses | 875system.cpu.dcache.demand_accesses::cpu.data 2571 # number of demand (read+write) accesses 876system.cpu.dcache.demand_accesses::total 2571 # number of demand (read+write) accesses 877system.cpu.dcache.overall_accesses::cpu.data 2571 # number of overall (read+write) accesses 878system.cpu.dcache.overall_accesses::total 2571 # number of overall (read+write) accesses 879system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110374 # miss rate for ReadReq accesses 880system.cpu.dcache.ReadReq_miss_rate::total 0.110374 # miss rate for ReadReq accesses |
| 871system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 872system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 873system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 874system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses | 881system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 882system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 883system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 884system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses |
| 875system.cpu.dcache.demand_miss_rate::cpu.data 0.193862 # miss rate for demand accesses 876system.cpu.dcache.demand_miss_rate::total 0.193862 # miss rate for demand accesses 877system.cpu.dcache.overall_miss_rate::cpu.data 0.193862 # miss rate for overall accesses 878system.cpu.dcache.overall_miss_rate::total 0.193862 # miss rate for overall accesses 879system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59273.224044 # average ReadReq miss latency 880system.cpu.dcache.ReadReq_avg_miss_latency::total 59273.224044 # average ReadReq miss latency 881system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72340.189873 # average WriteReq miss latency 882system.cpu.dcache.WriteReq_avg_miss_latency::total 72340.189873 # average WriteReq miss latency 883system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency 884system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency 885system.cpu.dcache.demand_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency 886system.cpu.dcache.demand_avg_miss_latency::total 67548.096192 # average overall miss latency 887system.cpu.dcache.overall_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency 888system.cpu.dcache.overall_avg_miss_latency::total 67548.096192 # average overall miss latency 889system.cpu.dcache.blocked_cycles::no_mshrs 147 # number of cycles access was blocked | 885system.cpu.dcache.demand_miss_rate::cpu.data 0.194088 # miss rate for demand accesses 886system.cpu.dcache.demand_miss_rate::total 0.194088 # miss rate for demand accesses 887system.cpu.dcache.overall_miss_rate::cpu.data 0.194088 # miss rate for overall accesses 888system.cpu.dcache.overall_miss_rate::total 0.194088 # miss rate for overall accesses 889system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519 # average ReadReq miss latency 890system.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519 # average ReadReq miss latency 891system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241 # average WriteReq miss latency 892system.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241 # average WriteReq miss latency 893system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency 894system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency 895system.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency 896system.cpu.dcache.demand_avg_miss_latency::total 71760.521042 # average overall miss latency 897system.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency 898system.cpu.dcache.overall_avg_miss_latency::total 71760.521042 # average overall miss latency 899system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked |
| 890system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 892system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 900system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 901system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 902system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 893system.cpu.dcache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked | 903system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked |
| 894system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 896system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 897system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 898system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 899system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 900system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 901system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 902system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits 903system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits 904system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits 905system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 906system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 907system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 908system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 909system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 910system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 911system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 912system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses | 904system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 905system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 906system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 907system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 908system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 909system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 910system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 911system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 912system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits 913system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits 914system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits 915system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 916system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 917system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 918system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 919system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 920system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 921system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 922system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses |
| 913system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7089000 # number of ReadReq MSHR miss cycles 914system.cpu.dcache.ReadReq_mshr_miss_latency::total 7089000 # number of ReadReq MSHR miss cycles 915system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3440000 # number of WriteReq MSHR miss cycles 916system.cpu.dcache.WriteReq_mshr_miss_latency::total 3440000 # number of WriteReq MSHR miss cycles 917system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10529000 # number of demand (read+write) MSHR miss cycles 918system.cpu.dcache.demand_mshr_miss_latency::total 10529000 # number of demand (read+write) MSHR miss cycles 919system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10529000 # number of overall MSHR miss cycles 920system.cpu.dcache.overall_mshr_miss_latency::total 10529000 # number of overall MSHR miss cycles 921system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063215 # mshr miss rate for ReadReq accesses 922system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063215 # mshr miss rate for ReadReq accesses | 923system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7355500 # number of ReadReq MSHR miss cycles 924system.cpu.dcache.ReadReq_mshr_miss_latency::total 7355500 # number of ReadReq MSHR miss cycles 925system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles 926system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles 927system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11023500 # number of demand (read+write) MSHR miss cycles 928system.cpu.dcache.demand_mshr_miss_latency::total 11023500 # number of demand (read+write) MSHR miss cycles 929system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11023500 # number of overall MSHR miss cycles 930system.cpu.dcache.overall_mshr_miss_latency::total 11023500 # number of overall MSHR miss cycles 931system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063329 # mshr miss rate for ReadReq accesses 932system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063329 # mshr miss rate for ReadReq accesses |
| 923system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 924system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses | 933system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 934system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses |
| 925system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for demand accesses 926system.cpu.dcache.demand_mshr_miss_rate::total 0.057110 # mshr miss rate for demand accesses 927system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for overall accesses 928system.cpu.dcache.overall_mshr_miss_rate::total 0.057110 # mshr miss rate for overall accesses 929system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67514.285714 # average ReadReq mshr miss latency 930system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67514.285714 # average ReadReq mshr miss latency 931system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81904.761905 # average WriteReq mshr miss latency 932system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81904.761905 # average WriteReq mshr miss latency 933system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency 934system.cpu.dcache.demand_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency 935system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency 936system.cpu.dcache.overall_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency 937system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 935system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for demand accesses 936system.cpu.dcache.demand_mshr_miss_rate::total 0.057176 # mshr miss rate for demand accesses 937system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for overall accesses 938system.cpu.dcache.overall_mshr_miss_rate::total 0.057176 # mshr miss rate for overall accesses 939system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952 # average ReadReq mshr miss latency 940system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952 # average ReadReq mshr miss latency 941system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency 942system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency 943system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency 944system.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency 945system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency 946system.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency 947system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 938system.cpu.icache.tags.replacements 2 # number of replacements | 948system.cpu.icache.tags.replacements 2 # number of replacements |
| 939system.cpu.icache.tags.tagsinuse 149.958367 # Cycle average of tags in use 940system.cpu.icache.tags.total_refs 1576 # Total number of references to valid blocks. | 949system.cpu.icache.tags.tagsinuse 149.507349 # Cycle average of tags in use 950system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. |
| 941system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. | 951system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. |
| 942system.cpu.icache.tags.avg_refs 5.360544 # Average number of references to valid blocks. | 952system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. |
| 943system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 953system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 944system.cpu.icache.tags.occ_blocks::cpu.inst 149.958367 # Average occupied blocks per requestor 945system.cpu.icache.tags.occ_percent::cpu.inst 0.073222 # Average percentage of cache occupancy 946system.cpu.icache.tags.occ_percent::total 0.073222 # Average percentage of cache occupancy | 954system.cpu.icache.tags.occ_blocks::cpu.inst 149.507349 # Average occupied blocks per requestor 955system.cpu.icache.tags.occ_percent::cpu.inst 0.073002 # Average percentage of cache occupancy 956system.cpu.icache.tags.occ_percent::total 0.073002 # Average percentage of cache occupancy |
| 947system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id | 957system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id |
| 948system.cpu.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id 949system.cpu.icache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id | 958system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id 959system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id |
| 950system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id | 960system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id |
| 951system.cpu.icache.tags.tag_accesses 4214 # Number of tag accesses 952system.cpu.icache.tags.data_accesses 4214 # Number of data accesses 953system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 954system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits 955system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits 956system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits 957system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits 958system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits 959system.cpu.icache.overall_hits::total 1576 # number of overall hits 960system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses 961system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses 962system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses 963system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses 964system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses 965system.cpu.icache.overall_misses::total 384 # number of overall misses 966system.cpu.icache.ReadReq_miss_latency::cpu.inst 27225000 # number of ReadReq miss cycles 967system.cpu.icache.ReadReq_miss_latency::total 27225000 # number of ReadReq miss cycles 968system.cpu.icache.demand_miss_latency::cpu.inst 27225000 # number of demand (read+write) miss cycles 969system.cpu.icache.demand_miss_latency::total 27225000 # number of demand (read+write) miss cycles 970system.cpu.icache.overall_miss_latency::cpu.inst 27225000 # number of overall miss cycles 971system.cpu.icache.overall_miss_latency::total 27225000 # number of overall miss cycles 972system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) 973system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) 974system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses 975system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses 976system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses 977system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses 978system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195918 # miss rate for ReadReq accesses 979system.cpu.icache.ReadReq_miss_rate::total 0.195918 # miss rate for ReadReq accesses 980system.cpu.icache.demand_miss_rate::cpu.inst 0.195918 # miss rate for demand accesses 981system.cpu.icache.demand_miss_rate::total 0.195918 # miss rate for demand accesses 982system.cpu.icache.overall_miss_rate::cpu.inst 0.195918 # miss rate for overall accesses 983system.cpu.icache.overall_miss_rate::total 0.195918 # miss rate for overall accesses 984system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70898.437500 # average ReadReq miss latency 985system.cpu.icache.ReadReq_avg_miss_latency::total 70898.437500 # average ReadReq miss latency 986system.cpu.icache.demand_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency 987system.cpu.icache.demand_avg_miss_latency::total 70898.437500 # average overall miss latency 988system.cpu.icache.overall_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency 989system.cpu.icache.overall_avg_miss_latency::total 70898.437500 # average overall miss latency 990system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked | 961system.cpu.icache.tags.tag_accesses 4218 # Number of tag accesses 962system.cpu.icache.tags.data_accesses 4218 # Number of data accesses 963system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 964system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits 965system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits 966system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits 967system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits 968system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits 969system.cpu.icache.overall_hits::total 1577 # number of overall hits 970system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 971system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses 972system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses 973system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses 974system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses 975system.cpu.icache.overall_misses::total 385 # number of overall misses 976system.cpu.icache.ReadReq_miss_latency::cpu.inst 28997500 # number of ReadReq miss cycles 977system.cpu.icache.ReadReq_miss_latency::total 28997500 # number of ReadReq miss cycles 978system.cpu.icache.demand_miss_latency::cpu.inst 28997500 # number of demand (read+write) miss cycles 979system.cpu.icache.demand_miss_latency::total 28997500 # number of demand (read+write) miss cycles 980system.cpu.icache.overall_miss_latency::cpu.inst 28997500 # number of overall miss cycles 981system.cpu.icache.overall_miss_latency::total 28997500 # number of overall miss cycles 982system.cpu.icache.ReadReq_accesses::cpu.inst 1962 # number of ReadReq accesses(hits+misses) 983system.cpu.icache.ReadReq_accesses::total 1962 # number of ReadReq accesses(hits+misses) 984system.cpu.icache.demand_accesses::cpu.inst 1962 # number of demand (read+write) accesses 985system.cpu.icache.demand_accesses::total 1962 # number of demand (read+write) accesses 986system.cpu.icache.overall_accesses::cpu.inst 1962 # number of overall (read+write) accesses 987system.cpu.icache.overall_accesses::total 1962 # number of overall (read+write) accesses 988system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196228 # miss rate for ReadReq accesses 989system.cpu.icache.ReadReq_miss_rate::total 0.196228 # miss rate for ReadReq accesses 990system.cpu.icache.demand_miss_rate::cpu.inst 0.196228 # miss rate for demand accesses 991system.cpu.icache.demand_miss_rate::total 0.196228 # miss rate for demand accesses 992system.cpu.icache.overall_miss_rate::cpu.inst 0.196228 # miss rate for overall accesses 993system.cpu.icache.overall_miss_rate::total 0.196228 # miss rate for overall accesses 994system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75318.181818 # average ReadReq miss latency 995system.cpu.icache.ReadReq_avg_miss_latency::total 75318.181818 # average ReadReq miss latency 996system.cpu.icache.demand_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency 997system.cpu.icache.demand_avg_miss_latency::total 75318.181818 # average overall miss latency 998system.cpu.icache.overall_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency 999system.cpu.icache.overall_avg_miss_latency::total 75318.181818 # average overall miss latency 1000system.cpu.icache.blocked_cycles::no_mshrs 493 # number of cycles access was blocked |
| 991system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 992system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 993system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 1001system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1002system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 1003system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 994system.cpu.icache.avg_blocked_cycles::no_mshrs 86.600000 # average number of cycles each access was blocked | 1004system.cpu.icache.avg_blocked_cycles::no_mshrs 98.600000 # average number of cycles each access was blocked |
| 995system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 996system.cpu.icache.writebacks::writebacks 2 # number of writebacks 997system.cpu.icache.writebacks::total 2 # number of writebacks | 1005system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1006system.cpu.icache.writebacks::writebacks 2 # number of writebacks 1007system.cpu.icache.writebacks::total 2 # number of writebacks |
| 998system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits 999system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 1000system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits 1001system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 1002system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 1003system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits | 1008system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits 1009system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits 1010system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits 1011system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits 1012system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits 1013system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits |
| 1004system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 1005system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 1006system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 1007system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 1008system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 1009system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses | 1014system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 1015system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 1016system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 1017system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 1018system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 1019system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses |
| 1010system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22193500 # number of ReadReq MSHR miss cycles 1011system.cpu.icache.ReadReq_mshr_miss_latency::total 22193500 # number of ReadReq MSHR miss cycles 1012system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22193500 # number of demand (read+write) MSHR miss cycles 1013system.cpu.icache.demand_mshr_miss_latency::total 22193500 # number of demand (read+write) MSHR miss cycles 1014system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22193500 # number of overall MSHR miss cycles 1015system.cpu.icache.overall_mshr_miss_latency::total 22193500 # number of overall MSHR miss cycles 1016system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for ReadReq accesses 1017system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150000 # mshr miss rate for ReadReq accesses 1018system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for demand accesses 1019system.cpu.icache.demand_mshr_miss_rate::total 0.150000 # mshr miss rate for demand accesses 1020system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for overall accesses 1021system.cpu.icache.overall_mshr_miss_rate::total 0.150000 # mshr miss rate for overall accesses 1022system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75488.095238 # average ReadReq mshr miss latency 1023system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75488.095238 # average ReadReq mshr miss latency 1024system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency 1025system.cpu.icache.demand_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency 1026system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency 1027system.cpu.icache.overall_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency 1028system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 1020system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23482000 # number of ReadReq MSHR miss cycles 1021system.cpu.icache.ReadReq_mshr_miss_latency::total 23482000 # number of ReadReq MSHR miss cycles 1022system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23482000 # number of demand (read+write) MSHR miss cycles 1023system.cpu.icache.demand_mshr_miss_latency::total 23482000 # number of demand (read+write) MSHR miss cycles 1024system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23482000 # number of overall MSHR miss cycles 1025system.cpu.icache.overall_mshr_miss_latency::total 23482000 # number of overall MSHR miss cycles 1026system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for ReadReq accesses 1027system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149847 # mshr miss rate for ReadReq accesses 1028system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for demand accesses 1029system.cpu.icache.demand_mshr_miss_rate::total 0.149847 # mshr miss rate for demand accesses 1030system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for overall accesses 1031system.cpu.icache.overall_mshr_miss_rate::total 0.149847 # mshr miss rate for overall accesses 1032system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79870.748299 # average ReadReq mshr miss latency 1033system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79870.748299 # average ReadReq mshr miss latency 1034system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency 1035system.cpu.icache.demand_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency 1036system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency 1037system.cpu.icache.overall_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency 1038system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 1029system.cpu.l2cache.tags.replacements 0 # number of replacements | 1039system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 1030system.cpu.l2cache.tags.tagsinuse 215.001500 # Cycle average of tags in use | 1040system.cpu.l2cache.tags.tagsinuse 214.408451 # Cycle average of tags in use |
| 1031system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 1032system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 1033system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. 1034system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1041system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 1042system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 1043system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. 1044system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1035system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.723037 # Average occupied blocks per requestor 1036system.cpu.l2cache.tags.occ_blocks::cpu.data 74.278463 # Average occupied blocks per requestor 1037system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004295 # Average percentage of cache occupancy 1038system.cpu.l2cache.tags.occ_percent::cpu.data 0.002267 # Average percentage of cache occupancy 1039system.cpu.l2cache.tags.occ_percent::total 0.006561 # Average percentage of cache occupancy | 1045system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.281348 # Average occupied blocks per requestor 1046system.cpu.l2cache.tags.occ_blocks::cpu.data 74.127103 # Average occupied blocks per requestor 1047system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004281 # Average percentage of cache occupancy 1048system.cpu.l2cache.tags.occ_percent::cpu.data 0.002262 # Average percentage of cache occupancy 1049system.cpu.l2cache.tags.occ_percent::total 0.006543 # Average percentage of cache occupancy |
| 1040system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id | 1050system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id |
| 1041system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id 1042system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id | 1051system.cpu.l2cache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id 1052system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id |
| 1043system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 1044system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses 1045system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses | 1053system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 1054system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses 1055system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses |
| 1046system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 1056system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 1047system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 1048system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 1049system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 1050system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 1051system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 1052system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 1053system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 1054system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits --- 8 unchanged lines hidden (view full) --- 1063system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses 1064system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses 1065system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 1066system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 1067system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses 1068system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 1069system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 1070system.cpu.l2cache.overall_misses::total 403 # number of overall misses | 1057system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 1058system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 1059system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 1060system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 1061system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 1062system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 1063system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 1064system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits --- 8 unchanged lines hidden (view full) --- 1073system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses 1074system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses 1075system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 1076system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 1077system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses 1078system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 1079system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 1080system.cpu.l2cache.overall_misses::total 403 # number of overall misses |
| 1071system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3375000 # number of ReadExReq miss cycles 1072system.cpu.l2cache.ReadExReq_miss_latency::total 3375000 # number of ReadExReq miss cycles 1073system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21544500 # number of ReadCleanReq miss cycles 1074system.cpu.l2cache.ReadCleanReq_miss_latency::total 21544500 # number of ReadCleanReq miss cycles 1075system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6694500 # number of ReadSharedReq miss cycles 1076system.cpu.l2cache.ReadSharedReq_miss_latency::total 6694500 # number of ReadSharedReq miss cycles 1077system.cpu.l2cache.demand_miss_latency::cpu.inst 21544500 # number of demand (read+write) miss cycles 1078system.cpu.l2cache.demand_miss_latency::cpu.data 10069500 # number of demand (read+write) miss cycles 1079system.cpu.l2cache.demand_miss_latency::total 31614000 # number of demand (read+write) miss cycles 1080system.cpu.l2cache.overall_miss_latency::cpu.inst 21544500 # number of overall miss cycles 1081system.cpu.l2cache.overall_miss_latency::cpu.data 10069500 # number of overall miss cycles 1082system.cpu.l2cache.overall_miss_latency::total 31614000 # number of overall miss cycles | 1081system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3603000 # number of ReadExReq miss cycles 1082system.cpu.l2cache.ReadExReq_miss_latency::total 3603000 # number of ReadExReq miss cycles 1083system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22833000 # number of ReadCleanReq miss cycles 1084system.cpu.l2cache.ReadCleanReq_miss_latency::total 22833000 # number of ReadCleanReq miss cycles 1085system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6961000 # number of ReadSharedReq miss cycles 1086system.cpu.l2cache.ReadSharedReq_miss_latency::total 6961000 # number of ReadSharedReq miss cycles 1087system.cpu.l2cache.demand_miss_latency::cpu.inst 22833000 # number of demand (read+write) miss cycles 1088system.cpu.l2cache.demand_miss_latency::cpu.data 10564000 # number of demand (read+write) miss cycles 1089system.cpu.l2cache.demand_miss_latency::total 33397000 # number of demand (read+write) miss cycles 1090system.cpu.l2cache.overall_miss_latency::cpu.inst 22833000 # number of overall miss cycles 1091system.cpu.l2cache.overall_miss_latency::cpu.data 10564000 # number of overall miss cycles 1092system.cpu.l2cache.overall_miss_latency::total 33397000 # number of overall miss cycles |
| 1083system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 1084system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 1085system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 1086system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 1087system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) 1088system.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) 1089system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) 1090system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 1101system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses 1102system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses 1103system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses 1104system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 1105system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses 1106system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses 1107system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 1108system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses | 1093system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 1094system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 1095system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 1096system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 1097system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) 1098system.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) 1099system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) 1100system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 1111system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses 1112system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses 1113system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses 1114system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 1115system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses 1116system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses 1117system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 1118system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses |
| 1109system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80357.142857 # average ReadExReq miss latency 1110system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80357.142857 # average ReadExReq miss latency 1111system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78059.782609 # average ReadCleanReq miss latency 1112system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78059.782609 # average ReadCleanReq miss latency 1113system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78758.823529 # average ReadSharedReq miss latency 1114system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78758.823529 # average ReadSharedReq miss latency 1115system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency 1116system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency 1117system.cpu.l2cache.demand_avg_miss_latency::total 78446.650124 # average overall miss latency 1118system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency 1119system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency 1120system.cpu.l2cache.overall_avg_miss_latency::total 78446.650124 # average overall miss latency | 1119system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency 1120system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency 1121system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870 # average ReadCleanReq miss latency 1122system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82728.260870 # average ReadCleanReq miss latency 1123system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81894.117647 # average ReadSharedReq miss latency 1124system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81894.117647 # average ReadSharedReq miss latency 1125system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency 1126system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency 1127system.cpu.l2cache.demand_avg_miss_latency::total 82870.967742 # average overall miss latency 1128system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency 1129system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency 1130system.cpu.l2cache.overall_avg_miss_latency::total 82870.967742 # average overall miss latency |
| 1121system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1122system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1123system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1124system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1125system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1126system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1127system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 1128system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits --- 8 unchanged lines hidden (view full) --- 1137system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses 1138system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses 1139system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 1140system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses 1141system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 1142system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 1143system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses 1144system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses | 1131system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1132system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1133system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1134system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1135system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1136system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1137system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 1138system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits --- 8 unchanged lines hidden (view full) --- 1147system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses 1148system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses 1149system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 1150system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses 1151system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 1152system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 1153system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses 1154system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses |
| 1145system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2955000 # number of ReadExReq MSHR miss cycles 1146system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2955000 # number of ReadExReq MSHR miss cycles 1147system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18784500 # number of ReadCleanReq MSHR miss cycles 1148system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18784500 # number of ReadCleanReq MSHR miss cycles 1149system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5499000 # number of ReadSharedReq MSHR miss cycles 1150system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5499000 # number of ReadSharedReq MSHR miss cycles 1151system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18784500 # number of demand (read+write) MSHR miss cycles 1152system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8454000 # number of demand (read+write) MSHR miss cycles 1153system.cpu.l2cache.demand_mshr_miss_latency::total 27238500 # number of demand (read+write) MSHR miss cycles 1154system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18784500 # number of overall MSHR miss cycles 1155system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8454000 # number of overall MSHR miss cycles 1156system.cpu.l2cache.overall_mshr_miss_latency::total 27238500 # number of overall MSHR miss cycles | 1155system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles 1156system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles 1157system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20073000 # number of ReadCleanReq MSHR miss cycles 1158system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20073000 # number of ReadCleanReq MSHR miss cycles 1159system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5729500 # number of ReadSharedReq MSHR miss cycles 1160system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5729500 # number of ReadSharedReq MSHR miss cycles 1161system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20073000 # number of demand (read+write) MSHR miss cycles 1162system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912500 # number of demand (read+write) MSHR miss cycles 1163system.cpu.l2cache.demand_mshr_miss_latency::total 28985500 # number of demand (read+write) MSHR miss cycles 1164system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20073000 # number of overall MSHR miss cycles 1165system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912500 # number of overall MSHR miss cycles 1166system.cpu.l2cache.overall_mshr_miss_latency::total 28985500 # number of overall MSHR miss cycles |
| 1157system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1158system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1159system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses 1160system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses 1161system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses 1162system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses 1163system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses 1164system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses 1165system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 1166system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses 1167system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses 1168system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses | 1167system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1168system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1169system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses 1170system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses 1171system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses 1172system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses 1173system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses 1174system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses 1175system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 1176system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses 1177system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses 1178system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses |
| 1169system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70357.142857 # average ReadExReq mshr miss latency 1170system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70357.142857 # average ReadExReq mshr miss latency 1171system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68059.782609 # average ReadCleanReq mshr miss latency 1172system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68059.782609 # average ReadCleanReq mshr miss latency 1173system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69607.594937 # average ReadSharedReq mshr miss latency 1174system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69607.594937 # average ReadSharedReq mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency 1177system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency | 1179system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency 1180system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency 1181system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870 # average ReadCleanReq mshr miss latency 1182system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870 # average ReadCleanReq mshr miss latency 1183system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456 # average ReadSharedReq mshr miss latency 1184system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456 # average ReadSharedReq mshr miss latency 1185system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency 1186system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency 1187system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency 1188system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency 1189system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency 1190system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency |
| 1181system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 1182system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1183system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1184system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1185system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1186system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1191system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 1192system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1193system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1194system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1195system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1196system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1187system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 1197system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 1188system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution 1194system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 1195system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) --- 10 unchanged lines hidden (view full) --- 1206system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram 1207system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1210system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 1213system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) | 1198system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 1200system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1201system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 1202system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution 1203system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution 1204system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 1205system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) --- 10 unchanged lines hidden (view full) --- 1216system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram 1217system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram 1218system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1219system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1220system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1221system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1222system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 1223system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) |
| 1214system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) | 1224system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) |
| 1215system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) | 1225system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) |
| 1216system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) | 1226system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) |
| 1217system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) | 1227system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) |
| 1218system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) | 1228system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) |
| 1219system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. 1220system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1221system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1222system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1223system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1224system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1229system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. 1230system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1231system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1232system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1233system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1234system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1225system.membus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states | 1235system.membus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states |
| 1226system.membus.trans_dist::ReadResp 355 # Transaction distribution 1227system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1228system.membus.trans_dist::ReadExResp 42 # Transaction distribution 1229system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution 1230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 1231system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 1232system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 1233system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1238system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1239system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1240system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 1241system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1242system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1243system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1244system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1245system.membus.snoop_fanout::total 397 # Request fanout histogram | 1236system.membus.trans_dist::ReadResp 355 # Transaction distribution 1237system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1238system.membus.trans_dist::ReadExResp 42 # Transaction distribution 1239system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution 1240system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 1241system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 1242system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 1243system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1248system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1249system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1250system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 1251system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1252system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1253system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1254system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1255system.membus.snoop_fanout::total 397 # Request fanout histogram |
| 1246system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) 1247system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 1248system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) 1249system.membus.respLayer1.utilization 12.0 # Layer utilization (%) | 1256system.membus.reqLayer0.occupancy 486500 # Layer occupancy (ticks) 1257system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) 1258system.membus.respLayer1.occupancy 2098750 # Layer occupancy (ticks) 1259system.membus.respLayer1.utilization 11.4 # Layer utilization (%) |
| 1250 1251---------- End Simulation Statistics ---------- | 1260 1261---------- End Simulation Statistics ---------- |