| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17232500 # Number of ticks simulated 5final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17232500 # Number of ticks simulated 5final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 74741 # Simulator instruction rate (inst/s) 8host_op_rate 87520 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 280399381 # Simulator tick rate (ticks/s) 10host_mem_usage 309668 # Number of bytes of host memory used | 7host_inst_rate 78702 # Simulator instruction rate (inst/s) 8host_op_rate 92158 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 295258113 # Simulator tick rate (ticks/s) 10host_mem_usage 310332 # Number of bytes of host memory used |
| 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 397 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) 247system.physmem_1.averagePower 808.014211 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 397 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 246system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) 248system.physmem_1.averagePower 808.014211 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states 250system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 253system.cpu.branchPred.lookups 2837 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 865 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks | 255system.cpu.branchPred.lookups 2837 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 865 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 267system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 288system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 270system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 299system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 296system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 317system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 320system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 321system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.checker.dtb.hits 0 # DTB hits 323system.cpu.checker.dtb.misses 0 # DTB misses 324system.cpu.checker.dtb.accesses 0 # DTB accesses | 300system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 324system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 325system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.checker.dtb.hits 0 # DTB hits 327system.cpu.checker.dtb.misses 0 # DTB misses 328system.cpu.checker.dtb.accesses 0 # DTB accesses |
| 329system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 325system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 346system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 330system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 359system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 354system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 355system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 376system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.checker.itb.read_accesses 0 # DTB read accesses 378system.cpu.checker.itb.write_accesses 0 # DTB write accesses 379system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.checker.itb.hits 0 # DTB hits 381system.cpu.checker.itb.misses 0 # DTB misses 382system.cpu.checker.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 13 # Number of system calls | 360system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 361system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.checker.itb.read_accesses 0 # DTB read accesses 384system.cpu.checker.itb.write_accesses 0 # DTB write accesses 385system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.checker.itb.hits 0 # DTB hits 387system.cpu.checker.itb.misses 0 # DTB misses 388system.cpu.checker.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 13 # Number of system calls |
| 390system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states |
|
| 384system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 385system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed | 391system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 392system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 394system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 387system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 388system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 391system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 394system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 408system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 409system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 411system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 412system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 413system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 414system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 415system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 395system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 396system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 397system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 399system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 400system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 402system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 416system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 417system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 418system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 419system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 420system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 421system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 422system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 423system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 424system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 416system.cpu.dtb.walker.walks 0 # Table walker walks requested 417system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 421system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 437system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 438system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 439system.cpu.dtb.read_accesses 0 # DTB read accesses 440system.cpu.dtb.write_accesses 0 # DTB write accesses 441system.cpu.dtb.inst_accesses 0 # ITB inst accesses 442system.cpu.dtb.hits 0 # DTB hits 443system.cpu.dtb.misses 0 # DTB misses 444system.cpu.dtb.accesses 0 # DTB accesses | 425system.cpu.dtb.walker.walks 0 # Table walker walks requested 426system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 430system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 432system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 446system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 448system.cpu.dtb.read_accesses 0 # DTB read accesses 449system.cpu.dtb.write_accesses 0 # DTB write accesses 450system.cpu.dtb.inst_accesses 0 # ITB inst accesses 451system.cpu.dtb.hits 0 # DTB hits 452system.cpu.dtb.misses 0 # DTB misses 453system.cpu.dtb.accesses 0 # DTB accesses |
| 454system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 445system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 466system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 468system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 469system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 470system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 471system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 472system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 473system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 455system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 462system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 476system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 478system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 479system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 480system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 481system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 482system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 483system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 484system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 474system.cpu.itb.walker.walks 0 # Table walker walks requested 475system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 478system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 479system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 480system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 481system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 495system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 496system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 497system.cpu.itb.read_accesses 0 # DTB read accesses 498system.cpu.itb.write_accesses 0 # DTB write accesses 499system.cpu.itb.inst_accesses 0 # ITB inst accesses 500system.cpu.itb.hits 0 # DTB hits 501system.cpu.itb.misses 0 # DTB misses 502system.cpu.itb.accesses 0 # DTB accesses | 485system.cpu.itb.walker.walks 0 # Table walker walks requested 486system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 487system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 488system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 489system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 490system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 491system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 492system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 506system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 507system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 508system.cpu.itb.read_accesses 0 # DTB read accesses 509system.cpu.itb.write_accesses 0 # DTB write accesses 510system.cpu.itb.inst_accesses 0 # ITB inst accesses 511system.cpu.itb.hits 0 # DTB hits 512system.cpu.itb.misses 0 # DTB misses 513system.cpu.itb.accesses 0 # DTB accesses |
| 514system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states |
|
| 503system.cpu.numCycles 34466 # number of cpu cycles simulated 504system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 505system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 506system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss 507system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed 508system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered 509system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken 510system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked --- 277 unchanged lines hidden (view full) --- 788system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads 789system.cpu.int_regfile_reads 7659 # number of integer regfile reads 790system.cpu.int_regfile_writes 4270 # number of integer regfile writes 791system.cpu.fp_regfile_reads 32 # number of floating regfile reads 792system.cpu.cc_regfile_reads 27801 # number of cc regfile reads 793system.cpu.cc_regfile_writes 3276 # number of cc regfile writes 794system.cpu.misc_regfile_reads 2978 # number of misc regfile reads 795system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 515system.cpu.numCycles 34466 # number of cpu cycles simulated 516system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 517system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 518system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss 519system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed 520system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered 521system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken 522system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked --- 277 unchanged lines hidden (view full) --- 800system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads 801system.cpu.int_regfile_reads 7659 # number of integer regfile reads 802system.cpu.int_regfile_writes 4270 # number of integer regfile writes 803system.cpu.fp_regfile_reads 32 # number of floating regfile reads 804system.cpu.cc_regfile_reads 27801 # number of cc regfile reads 805system.cpu.cc_regfile_writes 3276 # number of cc regfile writes 806system.cpu.misc_regfile_reads 2978 # number of misc regfile reads 807system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 808system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 796system.cpu.dcache.tags.replacements 0 # number of replacements 797system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use 798system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. 799system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 800system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks. 801system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 802system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor 803system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy 804system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy 805system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 806system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 807system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 808system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 809system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses 810system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses | 809system.cpu.dcache.tags.replacements 0 # number of replacements 810system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use 811system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. 812system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 813system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks. 814system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 815system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor 816system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy 817system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy 818system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 819system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 820system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 821system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 822system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses 823system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses |
| 824system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 811system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 812system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits 813system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 814system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 815system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 816system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 817system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 818system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 96 unchanged lines hidden (view full) --- 915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency 916system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency 917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency 918system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency 919system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 920system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency 921system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 922system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency | 825system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 826system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits 827system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 828system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 829system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 830system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 831system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 832system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 96 unchanged lines hidden (view full) --- 929system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency 930system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency 931system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency 932system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency 933system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 934system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency 935system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 936system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency |
| 937system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 923system.cpu.icache.tags.replacements 2 # number of replacements 924system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use 925system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. 926system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 927system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. 928system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 929system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor 930system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy 931system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy 932system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 933system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 934system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 935system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 936system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses 937system.cpu.icache.tags.data_accesses 4216 # Number of data accesses | 938system.cpu.icache.tags.replacements 2 # number of replacements 939system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use 940system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. 941system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 942system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. 943system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 944system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor 945system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy 946system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy 947system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 948system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 949system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 950system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 951system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses 952system.cpu.icache.tags.data_accesses 4216 # Number of data accesses |
| 953system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 938system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits 939system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits 940system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits 941system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits 942system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits 943system.cpu.icache.overall_hits::total 1577 # number of overall hits 944system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses 945system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 1004system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses 1005system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses 1006system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency 1007system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency 1008system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1009system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency 1010system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1011system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency | 954system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits 955system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits 956system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits 957system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits 958system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits 959system.cpu.icache.overall_hits::total 1577 # number of overall hits 960system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses 961system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 1020system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses 1021system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses 1022system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency 1023system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency 1024system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1025system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency 1026system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1027system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency |
| 1028system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
|
| 1012system.cpu.l2cache.tags.replacements 0 # number of replacements 1013system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use 1014system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 1015system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 1016system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 1017system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1018system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor 1019system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor 1020system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy 1021system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy 1022system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy 1023system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 1024system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 1025system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 1026system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id 1027system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses 1028system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses | 1029system.cpu.l2cache.tags.replacements 0 # number of replacements 1030system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use 1031system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 1032system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 1033system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 1034system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1035system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor 1036system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor 1037system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy 1038system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy 1039system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy 1040system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 1041system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 1042system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 1043system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id 1044system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses 1045system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses |
| 1046system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
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| 1029system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 1030system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 1031system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 1032system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 1033system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 1034system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 1035system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 1036system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits --- 124 unchanged lines hidden (view full) --- 1161system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency 1163system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 1164system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1165system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1166system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1167system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1168system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1047system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 1048system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 1049system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 1050system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 1051system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 1052system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 1053system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 1054system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits --- 124 unchanged lines hidden (view full) --- 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency 1181system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 1182system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1183system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1184system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1185system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1186system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1187system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
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| 1169system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1172system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution 1175system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 1176system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 1191system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1192system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 1193system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 1194system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 1195system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) 1196system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 1197system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) 1198system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) | 1188system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution 1194system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 1195system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 1210system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 1212system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 1213system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 1214system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) 1215system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 1216system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) 1217system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) |
| 1218system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states |
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| 1199system.membus.trans_dist::ReadResp 355 # Transaction distribution 1200system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1201system.membus.trans_dist::ReadExResp 42 # Transaction distribution 1202system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution 1203system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 1204system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 1205system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 1206system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 1219system.membus.trans_dist::ReadResp 355 # Transaction distribution 1220system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1221system.membus.trans_dist::ReadExResp 42 # Transaction distribution 1222system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution 1223system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 1224system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 1225system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 1226system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |