| stats.txt (11440:76b5639162af) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17232500 # Number of ticks simulated 5final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17232500 # Number of ticks simulated 5final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 9367 # Simulator instruction rate (inst/s) 8host_op_rate 10970 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 35022410 # Simulator tick rate (ticks/s) 10host_mem_usage 245324 # Number of bytes of host memory used 11host_seconds 0.49 # Real time elapsed on the host | 7host_inst_rate 43939 # Simulator instruction rate (inst/s) 8host_op_rate 51450 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 164826819 # Simulator tick rate (ticks/s) 10host_mem_usage 269540 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host |
| 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory --- 853 unchanged lines hidden (view full) --- 873system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency 874system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency 875system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked 876system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 877system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 878system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 879system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked 880system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory --- 853 unchanged lines hidden (view full) --- 873system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency 874system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency 875system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked 876system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 877system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 878system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 879system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked 880system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 881system.cpu.dcache.fast_writes 0 # number of fast writes performed 882system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 883system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 884system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 885system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 886system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 887system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 888system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 889system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 890system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits --- 26 unchanged lines hidden (view full) --- 917system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency 918system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency 919system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency 920system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency 921system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 922system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency 923system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 924system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency | 881system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 882system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 883system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 884system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 885system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 886system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 887system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 888system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits --- 26 unchanged lines hidden (view full) --- 915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency 916system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency 917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency 918system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency 919system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 920system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency 921system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 922system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency |
| 925system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 926system.cpu.icache.tags.replacements 2 # number of replacements 927system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use 928system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. 929system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 930system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. 931system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 932system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor 933system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 975system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency 976system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency 977system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked 978system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 979system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 980system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 981system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked 982system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 923system.cpu.icache.tags.replacements 2 # number of replacements 924system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use 925system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. 926system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 927system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. 928system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 929system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor 930system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 972system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency 973system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency 974system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked 975system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 976system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 977system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 978system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked 979system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 983system.cpu.icache.fast_writes 0 # number of fast writes performed 984system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 985system.cpu.icache.writebacks::writebacks 2 # number of writebacks 986system.cpu.icache.writebacks::total 2 # number of writebacks 987system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits 988system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 989system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits 990system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 991system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 992system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 1009system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses 1010system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses 1011system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency 1012system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency 1013system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1014system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency 1015system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1016system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency | 980system.cpu.icache.writebacks::writebacks 2 # number of writebacks 981system.cpu.icache.writebacks::total 2 # number of writebacks 982system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits 983system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 984system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits 985system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 986system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 987system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 1004system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses 1005system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses 1006system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency 1007system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency 1008system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1009system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency 1010system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1011system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency |
| 1017system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1018system.cpu.l2cache.tags.replacements 0 # number of replacements 1019system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use 1020system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 1021system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 1022system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 1023system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1024system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor 1025system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor --- 81 unchanged lines hidden (view full) --- 1107system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency 1108system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency 1109system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1110system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1111system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1112system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1113system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1114system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1012system.cpu.l2cache.tags.replacements 0 # number of replacements 1013system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use 1014system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 1015system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 1016system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 1017system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1018system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor 1019system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor --- 81 unchanged lines hidden (view full) --- 1101system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency 1102system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency 1103system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1104system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1105system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1106system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1107system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1108system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1115system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1116system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1117system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 1118system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 1119system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 1120system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1121system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 1122system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 1123system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 1124system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses --- 38 unchanged lines hidden (view full) --- 1163system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency 1164system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency 1165system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency 1166system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 1167system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency 1168system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency 1169system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 1170system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency | 1109system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 1110system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 1111system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 1112system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1113system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 1114system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 1115system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 1116system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses --- 38 unchanged lines hidden (view full) --- 1155system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency 1156system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency 1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency 1160system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency 1161system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency |
| 1171system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1172system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 1173system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1174system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1175system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1176system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1177system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1178system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution --- 53 unchanged lines hidden --- | 1163system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 1164system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1165system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1166system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1167system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1168system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1169system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution --- 53 unchanged lines hidden --- |