Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000017 # Number of seconds simulated

4sim_ticks 17163000 # Number of ticks simulated
5final_tick 17163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 17170000 # Number of ticks simulated
5final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 25428 # Simulator instruction rate (inst/s)
8host_op_rate 29777 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 95019968 # Simulator tick rate (ticks/s)
10host_mem_usage 305352 # Number of bytes of host memory used
11host_seconds 0.18 # Real time elapsed on the host

7host_inst_rate 50361 # Simulator instruction rate (inst/s)
8host_op_rate 58973 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 188251031 # Simulator tick rate (ticks/s)
10host_mem_usage 313812 # Number of bytes of host memory used
11host_seconds 0.09 # Real time elapsed on the host

12sim_insts 4592 # Number of instructions simulated
13sim_ops 5378 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory
18system.physmem.bytes_read::total 25344 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 396 # Number of read requests responded to by this memory

24system.physmem.bw_read::cpu.inst 1025461749 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 451203170 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1476664919 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 1025461749 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 1025461749 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 1025461749 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 451203170 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1476664919 # Total bandwidth to/from this memory (bytes/s)

24system.physmem.bw_read::cpu.inst 1025043681 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 451019220 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1476062900 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 1025043681 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 1025043681 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 1025043681 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 451019220 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1476062900 # Total bandwidth to/from this memory (bytes/s)

32system.physmem.readReqs 396 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side

--- 30 unchanged lines hidden (view full) ---

70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

78system.physmem.totGap 17090000 # Total gap between requests

78system.physmem.totGap 17097000 # Total gap between requests

79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 396 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)

--- 108 unchanged lines hidden (view full) ---

195system.physmem.bytesPerActivate::256-383 6 9.52% 58.73% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 8 12.70% 71.43% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation

203system.physmem.totQLat 3055250 # Total ticks spent queuing
204system.physmem.totMemAccLat 10480250 # Total ticks spent from burst creation until serviced by the DRAM

203system.physmem.totQLat 3045250 # Total ticks spent queuing
204system.physmem.totMemAccLat 10470250 # Total ticks spent from burst creation until serviced by the DRAM

205system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers

206system.physmem.avgQLat 7715.28 # Average queueing delay per DRAM burst

206system.physmem.avgQLat 7690.03 # Average queueing delay per DRAM burst

207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

208system.physmem.avgMemAccLat 26465.28 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 1476.66 # Average DRAM read bandwidth in MiByte/s

208system.physmem.avgMemAccLat 26440.03 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 1476.06 # Average DRAM read bandwidth in MiByte/s

210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s

211system.physmem.avgRdBWSys 1476.66 # Average system read bandwidth in MiByte/s

211system.physmem.avgRdBWSys 1476.06 # Average system read bandwidth in MiByte/s

212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s

214system.physmem.busUtil 11.54 # Data bus utilization in percentage
215system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads

214system.physmem.busUtil 11.53 # Data bus utilization in percentage
215system.physmem.busUtilRead 11.53 # Data bus utilization in percentage for reads

216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 330 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

223system.physmem.avgGap 43156.57 # Average gap between requests

223system.physmem.avgGap 43174.24 # Average gap between requests

224system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)

230system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ)

230system.physmem_0.actBackEnergy 10798650 # Energy for active background per rank (pJ)

231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)

232system.physmem_0.totalEnergy 14428830 # Total energy per rank (pJ)
233system.physmem_0.averagePower 911.198611 # Core power per rank (mW)

232system.physmem_0.totalEnergy 14433105 # Total energy per rank (pJ)
233system.physmem_0.averagePower 911.108972 # Core power per rank (mW)

234system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states
235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states

237system.physmem_0.memoryStateTime::ACT 16176750 # Time in different power states

237system.physmem_0.memoryStateTime::ACT 16183750 # Time in different power states

238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ)
247system.physmem_1.averagePower 807.028896 # Core power per rank (mW)

248system.physmem_1.memoryStateTime::IDLE 665250 # Time in different power states

248system.physmem_1.memoryStateTime::IDLE 672250 # Time in different power states

249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

253system.cpu.branchPred.lookups 2533 # Number of BP lookups
254system.cpu.branchPred.condPredicted 1576 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 452 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 2102 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 812 # Number of BTB hits

253system.cpu.branchPred.lookups 2537 # Number of BP lookups
254system.cpu.branchPred.condPredicted 1577 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 453 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 2106 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 814 # Number of BTB hits

258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

259system.cpu.branchPred.BTBHitPct 38.629876 # BTB Hit Percentage

259system.cpu.branchPred.BTBHitPct 38.651472 # BTB Hit Percentage

260system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
262system.cpu_clk_domain.clock 500 # Clock period in ticks
263system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
264system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
265system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
266system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
267system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst

--- 223 unchanged lines hidden (view full) ---

491system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
492system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
493system.cpu.itb.read_accesses 0 # DTB read accesses
494system.cpu.itb.write_accesses 0 # DTB write accesses
495system.cpu.itb.inst_accesses 0 # ITB inst accesses
496system.cpu.itb.hits 0 # DTB hits
497system.cpu.itb.misses 0 # DTB misses
498system.cpu.itb.accesses 0 # DTB accesses

499system.cpu.numCycles 34327 # number of cpu cycles simulated

499system.cpu.numCycles 34341 # number of cpu cycles simulated

500system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
501system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

502system.cpu.fetch.icacheStallCycles 7647 # Number of cycles fetch is stalled on an Icache miss
503system.cpu.fetch.Insts 11725 # Number of instructions fetch has processed
504system.cpu.fetch.Branches 2533 # Number of branches that fetch encountered
505system.cpu.fetch.predictedBranches 1133 # Number of branches that fetch has predicted taken
506system.cpu.fetch.Cycles 4667 # Number of cycles fetch has run and was not squashing or blocked
507system.cpu.fetch.SquashCycles 953 # Number of cycles fetch has spent squashing

502system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss
503system.cpu.fetch.Insts 11733 # Number of instructions fetch has processed
504system.cpu.fetch.Branches 2537 # Number of branches that fetch encountered
505system.cpu.fetch.predictedBranches 1135 # Number of branches that fetch has predicted taken
506system.cpu.fetch.Cycles 4671 # Number of cycles fetch has run and was not squashing or blocked
507system.cpu.fetch.SquashCycles 955 # Number of cycles fetch has spent squashing

508system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
509system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps
510system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR

511system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched
512system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed
513system.cpu.fetch.rateDist::samples 13059 # Number of instructions fetched each cycle (Total)
514system.cpu.fetch.rateDist::mean 1.059729 # Number of instructions fetched each cycle (Total)
515system.cpu.fetch.rateDist::stdev 2.422792 # Number of instructions fetched each cycle (Total)

511system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched
512system.cpu.fetch.IcacheSquashes 292 # Number of outstanding Icache misses that were squashed
513system.cpu.fetch.rateDist::samples 13078 # Number of instructions fetched each cycle (Total)
514system.cpu.fetch.rateDist::mean 1.059336 # Number of instructions fetched each cycle (Total)
515system.cpu.fetch.rateDist::stdev 2.422082 # Number of instructions fetched each cycle (Total)

516system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

517system.cpu.fetch.rateDist::0 10498 80.39% 80.39% # Number of instructions fetched each cycle (Total)
518system.cpu.fetch.rateDist::1 262 2.01% 82.40% # Number of instructions fetched each cycle (Total)
519system.cpu.fetch.rateDist::2 215 1.65% 84.04% # Number of instructions fetched each cycle (Total)
520system.cpu.fetch.rateDist::3 219 1.68% 85.72% # Number of instructions fetched each cycle (Total)
521system.cpu.fetch.rateDist::4 263 2.01% 87.73% # Number of instructions fetched each cycle (Total)
522system.cpu.fetch.rateDist::5 312 2.39% 90.12% # Number of instructions fetched each cycle (Total)
523system.cpu.fetch.rateDist::6 142 1.09% 91.21% # Number of instructions fetched each cycle (Total)
524system.cpu.fetch.rateDist::7 158 1.21% 92.42% # Number of instructions fetched each cycle (Total)
525system.cpu.fetch.rateDist::8 990 7.58% 100.00% # Number of instructions fetched each cycle (Total)

517system.cpu.fetch.rateDist::0 10515 80.40% 80.40% # Number of instructions fetched each cycle (Total)
518system.cpu.fetch.rateDist::1 260 1.99% 82.39% # Number of instructions fetched each cycle (Total)
519system.cpu.fetch.rateDist::2 215 1.64% 84.03% # Number of instructions fetched each cycle (Total)
520system.cpu.fetch.rateDist::3 219 1.67% 85.71% # Number of instructions fetched each cycle (Total)
521system.cpu.fetch.rateDist::4 267 2.04% 87.75% # Number of instructions fetched each cycle (Total)
522system.cpu.fetch.rateDist::5 312 2.39% 90.14% # Number of instructions fetched each cycle (Total)
523system.cpu.fetch.rateDist::6 142 1.09% 91.22% # Number of instructions fetched each cycle (Total)
524system.cpu.fetch.rateDist::7 157 1.20% 92.42% # Number of instructions fetched each cycle (Total)
525system.cpu.fetch.rateDist::8 991 7.58% 100.00% # Number of instructions fetched each cycle (Total)

526system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
527system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
528system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

529system.cpu.fetch.rateDist::total 13059 # Number of instructions fetched each cycle (Total)
530system.cpu.fetch.branchRate 0.073790 # Number of branch fetches per cycle
531system.cpu.fetch.rate 0.341568 # Number of inst fetches per cycle
532system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle
533system.cpu.decode.BlockedCycles 4216 # Number of cycles decode is blocked

529system.cpu.fetch.rateDist::total 13078 # Number of instructions fetched each cycle (Total)
530system.cpu.fetch.branchRate 0.073877 # Number of branch fetches per cycle
531system.cpu.fetch.rate 0.341662 # Number of inst fetches per cycle
532system.cpu.decode.IdleCycles 6351 # Number of cycles decode is idle
533system.cpu.decode.BlockedCycles 4223 # Number of cycles decode is blocked

534system.cpu.decode.RunCycles 2063 # Number of cycles decode is running

535system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking
536system.cpu.decode.SquashCycles 321 # Number of cycles decode is squashing
537system.cpu.decode.BranchResolved 380 # Number of times decode resolved a branch

535system.cpu.decode.UnblockCycles 119 # Number of cycles decode is unblocking
536system.cpu.decode.SquashCycles 322 # Number of cycles decode is squashing
537system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch

538system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction

539system.cpu.decode.DecodedInsts 11316 # Number of instructions handled by decode

539system.cpu.decode.DecodedInsts 11299 # Number of instructions handled by decode

540system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode

541system.cpu.rename.SquashCycles 321 # Number of cycles rename is squashing
542system.cpu.rename.IdleCycles 6551 # Number of cycles rename is idle
543system.cpu.rename.BlockCycles 647 # Number of cycles rename is blocking
544system.cpu.rename.serializeStallCycles 2328 # count of cycles rename stalled for serializing inst
545system.cpu.rename.RunCycles 1964 # Number of cycles rename is running

541system.cpu.rename.SquashCycles 322 # Number of cycles rename is squashing
542system.cpu.rename.IdleCycles 6564 # Number of cycles rename is idle
543system.cpu.rename.BlockCycles 644 # Number of cycles rename is blocking
544system.cpu.rename.serializeStallCycles 2338 # count of cycles rename stalled for serializing inst
545system.cpu.rename.RunCycles 1962 # Number of cycles rename is running

546system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking

547system.cpu.rename.RenamedInsts 10673 # Number of instructions processed by rename

547system.cpu.rename.RenamedInsts 10655 # Number of instructions processed by rename

548system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full
549system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full
550system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full

551system.cpu.rename.RenamedOperands 10857 # Number of destination operands rename has renamed
552system.cpu.rename.RenameLookups 48954 # Number of register rename lookups that rename has made
553system.cpu.rename.int_rename_lookups 11788 # Number of integer rename lookups

551system.cpu.rename.RenamedOperands 10847 # Number of destination operands rename has renamed
552system.cpu.rename.RenameLookups 48852 # Number of register rename lookups that rename has made
553system.cpu.rename.int_rename_lookups 11762 # Number of integer rename lookups

554system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups
555system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed

556system.cpu.rename.UndoneMaps 5363 # Number of HB maps that are undone due to squashing

556system.cpu.rename.UndoneMaps 5353 # Number of HB maps that are undone due to squashing

557system.cpu.rename.serializingInsts 42 # count of serializing insts renamed
558system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
559system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer

560system.cpu.memDep0.insertedLoads 2126 # Number of loads inserted to the mem dependence unit.
561system.cpu.memDep0.insertedStores 1537 # Number of stores inserted to the mem dependence unit.

560system.cpu.memDep0.insertedLoads 2118 # Number of loads inserted to the mem dependence unit.
561system.cpu.memDep0.insertedStores 1531 # Number of stores inserted to the mem dependence unit.

562system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads.
563system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores.

564system.cpu.iq.iqInstsAdded 9711 # Number of instructions added to the IQ (excludes non-spec)

564system.cpu.iq.iqInstsAdded 9695 # Number of instructions added to the IQ (excludes non-spec)

565system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ

566system.cpu.iq.iqInstsIssued 7972 # Number of instructions issued

566system.cpu.iq.iqInstsIssued 7975 # Number of instructions issued

567system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued

568system.cpu.iq.iqSquashedInstsExamined 4379 # Number of squashed instructions iterated over during squash; mainly for profiling
569system.cpu.iq.iqSquashedOperandsExamined 10941 # Number of squashed operands that are examined and possibly removed from graph

568system.cpu.iq.iqSquashedInstsExamined 4363 # Number of squashed instructions iterated over during squash; mainly for profiling
569system.cpu.iq.iqSquashedOperandsExamined 10837 # Number of squashed operands that are examined and possibly removed from graph

570system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed

571system.cpu.iq.issued_per_cycle::samples 13059 # Number of insts issued each cycle
572system.cpu.iq.issued_per_cycle::mean 0.610460 # Number of insts issued each cycle
573system.cpu.iq.issued_per_cycle::stdev 1.342240 # Number of insts issued each cycle

571system.cpu.iq.issued_per_cycle::samples 13078 # Number of insts issued each cycle
572system.cpu.iq.issued_per_cycle::mean 0.609803 # Number of insts issued each cycle
573system.cpu.iq.issued_per_cycle::stdev 1.341106 # Number of insts issued each cycle

574system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

575system.cpu.iq.issued_per_cycle::0 9876 75.63% 75.63% # Number of insts issued each cycle
576system.cpu.iq.issued_per_cycle::1 1174 8.99% 84.62% # Number of insts issued each cycle
577system.cpu.iq.issued_per_cycle::2 762 5.84% 90.45% # Number of insts issued each cycle
578system.cpu.iq.issued_per_cycle::3 454 3.48% 93.93% # Number of insts issued each cycle
579system.cpu.iq.issued_per_cycle::4 326 2.50% 96.42% # Number of insts issued each cycle
580system.cpu.iq.issued_per_cycle::5 278 2.13% 98.55% # Number of insts issued each cycle
581system.cpu.iq.issued_per_cycle::6 116 0.89% 99.44% # Number of insts issued each cycle

575system.cpu.iq.issued_per_cycle::0 9890 75.62% 75.62% # Number of insts issued each cycle
576system.cpu.iq.issued_per_cycle::1 1180 9.02% 84.65% # Number of insts issued each cycle
577system.cpu.iq.issued_per_cycle::2 762 5.83% 90.47% # Number of insts issued each cycle
578system.cpu.iq.issued_per_cycle::3 451 3.45% 93.92% # Number of insts issued each cycle
579system.cpu.iq.issued_per_cycle::4 329 2.52% 96.44% # Number of insts issued each cycle
580system.cpu.iq.issued_per_cycle::5 278 2.13% 98.56% # Number of insts issued each cycle
581system.cpu.iq.issued_per_cycle::6 115 0.88% 99.44% # Number of insts issued each cycle

582system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle
583system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle
584system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
585system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
586system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

587system.cpu.iq.issued_per_cycle::total 13059 # Number of insts issued each cycle

587system.cpu.iq.issued_per_cycle::total 13078 # Number of insts issued each cycle

588system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
589system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available
590system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available
591system.cpu.iq.fu_full::IntDiv 0 0.00% 5.92% # attempts to use FU when none available
592system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.92% # attempts to use FU when none available
593system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.92% # attempts to use FU when none available
594system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.92% # attempts to use FU when none available
595system.cpu.iq.fu_full::FloatMult 0 0.00% 5.92% # attempts to use FU when none available

--- 19 unchanged lines hidden (view full) ---

615system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.92% # attempts to use FU when none available
616system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.92% # attempts to use FU when none available
617system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.92% # attempts to use FU when none available
618system.cpu.iq.fu_full::MemRead 67 44.08% 50.00% # attempts to use FU when none available
619system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # attempts to use FU when none available
620system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
621system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
622system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

623system.cpu.iq.FU_type_0::IntAlu 4885 61.28% 61.28% # Type of FU issued
624system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.36% # Type of FU issued
625system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.36% # Type of FU issued
626system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.36% # Type of FU issued
627system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.36% # Type of FU issued
628system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.36% # Type of FU issued
629system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.36% # Type of FU issued
630system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.36% # Type of FU issued
631system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.36% # Type of FU issued
632system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.36% # Type of FU issued
633system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.36% # Type of FU issued
634system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.36% # Type of FU issued
635system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.36% # Type of FU issued
636system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.36% # Type of FU issued
637system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.36% # Type of FU issued
638system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.36% # Type of FU issued
639system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.36% # Type of FU issued
640system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.36% # Type of FU issued
641system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.36% # Type of FU issued
642system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.36% # Type of FU issued
643system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.36% # Type of FU issued
644system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.36% # Type of FU issued
645system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.36% # Type of FU issued
646system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.36% # Type of FU issued
647system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.36% # Type of FU issued
648system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.40% # Type of FU issued
649system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.40% # Type of FU issued
650system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.40% # Type of FU issued
651system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.40% # Type of FU issued
652system.cpu.iq.FU_type_0::MemRead 1831 22.97% 84.37% # Type of FU issued
653system.cpu.iq.FU_type_0::MemWrite 1246 15.63% 100.00% # Type of FU issued

623system.cpu.iq.FU_type_0::IntAlu 4886 61.27% 61.27% # Type of FU issued
624system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.35% # Type of FU issued
625system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.35% # Type of FU issued
626system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.35% # Type of FU issued
627system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.35% # Type of FU issued
628system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.35% # Type of FU issued
629system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.35% # Type of FU issued
630system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.35% # Type of FU issued
631system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.35% # Type of FU issued
632system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued
633system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued
634system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued
635system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued
636system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued
637system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued
638system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued
639system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued
640system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued
641system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued
642system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued
643system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued
644system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued
645system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued
646system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued
647system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued
648system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.39% # Type of FU issued
649system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued
650system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued
651system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued
652system.cpu.iq.FU_type_0::MemRead 1833 22.98% 84.38% # Type of FU issued
653system.cpu.iq.FU_type_0::MemWrite 1246 15.62% 100.00% # Type of FU issued

654system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
655system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

656system.cpu.iq.FU_type_0::total 7972 # Type of FU issued
657system.cpu.iq.rate 0.232237 # Inst issue rate

656system.cpu.iq.FU_type_0::total 7975 # Type of FU issued
657system.cpu.iq.rate 0.232230 # Inst issue rate

658system.cpu.iq.fu_busy_cnt 152 # FU busy when requested

659system.cpu.iq.fu_busy_rate 0.019067 # FU busy rate (busy events/executed inst)
660system.cpu.iq.int_inst_queue_reads 29107 # Number of integer instruction queue reads
661system.cpu.iq.int_inst_queue_writes 14039 # Number of integer instruction queue writes
662system.cpu.iq.int_inst_queue_wakeup_accesses 7309 # Number of integer instruction queue wakeup accesses

659system.cpu.iq.fu_busy_rate 0.019060 # FU busy rate (busy events/executed inst)
660system.cpu.iq.int_inst_queue_reads 29132 # Number of integer instruction queue reads
661system.cpu.iq.int_inst_queue_writes 14007 # Number of integer instruction queue writes
662system.cpu.iq.int_inst_queue_wakeup_accesses 7313 # Number of integer instruction queue wakeup accesses

663system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads
664system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes
665system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses

666system.cpu.iq.int_alu_accesses 8081 # Number of integer alu accesses

666system.cpu.iq.int_alu_accesses 8084 # Number of integer alu accesses

667system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses
668system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores
669system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

670system.cpu.iew.lsq.thread0.squashedLoads 1099 # Number of loads squashed

670system.cpu.iew.lsq.thread0.squashedLoads 1091 # Number of loads squashed

671system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
672system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations

673system.cpu.iew.lsq.thread0.squashedStores 599 # Number of stores squashed

673system.cpu.iew.lsq.thread0.squashedStores 593 # Number of stores squashed

674system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
675system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
676system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled
677system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked
678system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

679system.cpu.iew.iewSquashCycles 321 # Number of cycles IEW is squashing
680system.cpu.iew.iewBlockCycles 613 # Number of cycles IEW is blocking

679system.cpu.iew.iewSquashCycles 322 # Number of cycles IEW is squashing
680system.cpu.iew.iewBlockCycles 611 # Number of cycles IEW is blocking

681system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking

682system.cpu.iew.iewDispatchedInsts 9766 # Number of instructions dispatched to IQ

682system.cpu.iew.iewDispatchedInsts 9750 # Number of instructions dispatched to IQ

683system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch

684system.cpu.iew.iewDispLoadInsts 2126 # Number of dispatched load instructions
685system.cpu.iew.iewDispStoreInsts 1537 # Number of dispatched store instructions

684system.cpu.iew.iewDispLoadInsts 2118 # Number of dispatched load instructions
685system.cpu.iew.iewDispStoreInsts 1531 # Number of dispatched store instructions

686system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
687system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
688system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
689system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
690system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly
691system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly
692system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute

693system.cpu.iew.iewExecutedInsts 7697 # Number of executed instructions

693system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions

694system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed

695system.cpu.iew.iewExecSquashedInsts 275 # Number of squashed instructions skipped in execute

695system.cpu.iew.iewExecSquashedInsts 274 # Number of squashed instructions skipped in execute

696system.cpu.iew.exec_swp 0 # number of swp insts executed
697system.cpu.iew.exec_nop 9 # number of nop insts executed

698system.cpu.iew.exec_refs 2930 # number of memory reference insts executed
699system.cpu.iew.exec_branches 1433 # Number of branches executed
700system.cpu.iew.exec_stores 1194 # Number of stores executed
701system.cpu.iew.exec_rate 0.224226 # Inst execution rate
702system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit
703system.cpu.iew.wb_count 7341 # cumulative count of insts written-back
704system.cpu.iew.wb_producers 3456 # num instructions producing a value
705system.cpu.iew.wb_consumers 6757 # num instructions consuming a value

698system.cpu.iew.exec_refs 2933 # number of memory reference insts executed
699system.cpu.iew.exec_branches 1435 # Number of branches executed
700system.cpu.iew.exec_stores 1197 # Number of stores executed
701system.cpu.iew.exec_rate 0.224251 # Inst execution rate
702system.cpu.iew.wb_sent 7436 # cumulative count of insts sent to commit
703system.cpu.iew.wb_count 7345 # cumulative count of insts written-back
704system.cpu.iew.wb_producers 3459 # num instructions producing a value
705system.cpu.iew.wb_consumers 6763 # num instructions consuming a value

706system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

707system.cpu.iew.wb_rate 0.213855 # insts written-back per cycle
708system.cpu.iew.wb_fanout 0.511470 # average fanout of values written-back

707system.cpu.iew.wb_rate 0.213884 # insts written-back per cycle
708system.cpu.iew.wb_fanout 0.511459 # average fanout of values written-back

709system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

710system.cpu.commit.commitSquashedInsts 4387 # The number of squashed insts skipped by commit

710system.cpu.commit.commitSquashedInsts 4371 # The number of squashed insts skipped by commit

711system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards

712system.cpu.commit.branchMispredicts 297 # The number of times a branch was mispredicted
713system.cpu.commit.committed_per_cycle::samples 12286 # Number of insts commited each cycle
714system.cpu.commit.committed_per_cycle::mean 0.437734 # Number of insts commited each cycle
715system.cpu.commit.committed_per_cycle::stdev 1.284067 # Number of insts commited each cycle

712system.cpu.commit.branchMispredicts 298 # The number of times a branch was mispredicted
713system.cpu.commit.committed_per_cycle::samples 12306 # Number of insts commited each cycle
714system.cpu.commit.committed_per_cycle::mean 0.437023 # Number of insts commited each cycle
715system.cpu.commit.committed_per_cycle::stdev 1.282384 # Number of insts commited each cycle

716system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

717system.cpu.commit.committed_per_cycle::0 10235 83.31% 83.31% # Number of insts commited each cycle
718system.cpu.commit.committed_per_cycle::1 882 7.18% 90.49% # Number of insts commited each cycle
719system.cpu.commit.committed_per_cycle::2 420 3.42% 93.90% # Number of insts commited each cycle
720system.cpu.commit.committed_per_cycle::3 222 1.81% 95.71% # Number of insts commited each cycle
721system.cpu.commit.committed_per_cycle::4 111 0.90% 96.61% # Number of insts commited each cycle
722system.cpu.commit.committed_per_cycle::5 213 1.73% 98.35% # Number of insts commited each cycle
723system.cpu.commit.committed_per_cycle::6 51 0.42% 98.76% # Number of insts commited each cycle
724system.cpu.commit.committed_per_cycle::7 41 0.33% 99.10% # Number of insts commited each cycle

717system.cpu.commit.committed_per_cycle::0 10254 83.33% 83.33% # Number of insts commited each cycle
718system.cpu.commit.committed_per_cycle::1 882 7.17% 90.49% # Number of insts commited each cycle
719system.cpu.commit.committed_per_cycle::2 420 3.41% 93.91% # Number of insts commited each cycle
720system.cpu.commit.committed_per_cycle::3 223 1.81% 95.72% # Number of insts commited each cycle
721system.cpu.commit.committed_per_cycle::4 112 0.91% 96.63% # Number of insts commited each cycle
722system.cpu.commit.committed_per_cycle::5 213 1.73% 98.36% # Number of insts commited each cycle
723system.cpu.commit.committed_per_cycle::6 51 0.41% 98.77% # Number of insts commited each cycle
724system.cpu.commit.committed_per_cycle::7 40 0.33% 99.10% # Number of insts commited each cycle

725system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle
726system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
727system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
728system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

729system.cpu.commit.committed_per_cycle::total 12286 # Number of insts commited each cycle

729system.cpu.commit.committed_per_cycle::total 12306 # Number of insts commited each cycle

730system.cpu.commit.committedInsts 4592 # Number of instructions committed
731system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
732system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
733system.cpu.commit.refs 1965 # Number of memory references committed
734system.cpu.commit.loads 1027 # Number of loads committed
735system.cpu.commit.membars 12 # Number of memory barriers committed
736system.cpu.commit.branches 1008 # Number of branches committed
737system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.

--- 30 unchanged lines hidden (view full) ---

768system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
769system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
770system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction
771system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction
772system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
773system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
774system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
775system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached

776system.cpu.rob.rob_reads 21783 # The number of ROB reads
777system.cpu.rob.rob_writes 20313 # The number of ROB writes
778system.cpu.timesIdled 192 # Number of times that the entire CPU went into an idle state and unscheduled itself
779system.cpu.idleCycles 21268 # Total number of cycles that the CPU has spent unscheduled due to idling

776system.cpu.rob.rob_reads 21787 # The number of ROB reads
777system.cpu.rob.rob_writes 20281 # The number of ROB writes
778system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself
779system.cpu.idleCycles 21263 # Total number of cycles that the CPU has spent unscheduled due to idling

780system.cpu.committedInsts 4592 # Number of Instructions Simulated
781system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated

782system.cpu.cpi 7.475392 # CPI: Cycles Per Instruction
783system.cpu.cpi_total 7.475392 # CPI: Total CPI of All Threads
784system.cpu.ipc 0.133772 # IPC: Instructions Per Cycle
785system.cpu.ipc_total 0.133772 # IPC: Total IPC of All Threads
786system.cpu.int_regfile_reads 7631 # number of integer regfile reads

782system.cpu.cpi 7.478441 # CPI: Cycles Per Instruction
783system.cpu.cpi_total 7.478441 # CPI: Total CPI of All Threads
784system.cpu.ipc 0.133718 # IPC: Instructions Per Cycle
785system.cpu.ipc_total 0.133718 # IPC: Total IPC of All Threads
786system.cpu.int_regfile_reads 7636 # number of integer regfile reads

787system.cpu.int_regfile_writes 4176 # number of integer regfile writes
788system.cpu.fp_regfile_reads 32 # number of floating regfile reads

789system.cpu.cc_regfile_reads 27375 # number of cc regfile reads
790system.cpu.cc_regfile_writes 3204 # number of cc regfile writes
791system.cpu.misc_regfile_reads 3054 # number of misc regfile reads

789system.cpu.cc_regfile_reads 27387 # number of cc regfile reads
790system.cpu.cc_regfile_writes 3201 # number of cc regfile writes
791system.cpu.misc_regfile_reads 3057 # number of misc regfile reads

792system.cpu.misc_regfile_writes 24 # number of misc regfile writes
793system.cpu.dcache.tags.replacements 0 # number of replacements

794system.cpu.dcache.tags.tagsinuse 87.851603 # Cycle average of tags in use

794system.cpu.dcache.tags.tagsinuse 87.846363 # Cycle average of tags in use

795system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks.
796system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
797system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks.
798system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

799system.cpu.dcache.tags.occ_blocks::cpu.data 87.851603 # Average occupied blocks per requestor
800system.cpu.dcache.tags.occ_percent::cpu.data 0.021448 # Average percentage of cache occupancy
801system.cpu.dcache.tags.occ_percent::total 0.021448 # Average percentage of cache occupancy

799system.cpu.dcache.tags.occ_blocks::cpu.data 87.846363 # Average occupied blocks per requestor
800system.cpu.dcache.tags.occ_percent::cpu.data 0.021447 # Average percentage of cache occupancy
801system.cpu.dcache.tags.occ_percent::total 0.021447 # Average percentage of cache occupancy

802system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
803system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
804system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
805system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id
806system.cpu.dcache.tags.tag_accesses 5255 # Number of tag accesses
807system.cpu.dcache.tags.data_accesses 5255 # Number of data accesses
808system.cpu.dcache.ReadReq_hits::cpu.data 1436 # number of ReadReq hits
809system.cpu.dcache.ReadReq_hits::total 1436 # number of ReadReq hits

--- 12 unchanged lines hidden (view full) ---

822system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses
823system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses
824system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
825system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
826system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
827system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
828system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
829system.cpu.dcache.overall_misses::total 498 # number of overall misses

830system.cpu.dcache.ReadReq_miss_latency::cpu.data 10572000 # number of ReadReq miss cycles
831system.cpu.dcache.ReadReq_miss_latency::total 10572000 # number of ReadReq miss cycles
832system.cpu.dcache.WriteReq_miss_latency::cpu.data 22577500 # number of WriteReq miss cycles
833system.cpu.dcache.WriteReq_miss_latency::total 22577500 # number of WriteReq miss cycles

830system.cpu.dcache.ReadReq_miss_latency::cpu.data 10593000 # number of ReadReq miss cycles
831system.cpu.dcache.ReadReq_miss_latency::total 10593000 # number of ReadReq miss cycles
832system.cpu.dcache.WriteReq_miss_latency::cpu.data 22578500 # number of WriteReq miss cycles
833system.cpu.dcache.WriteReq_miss_latency::total 22578500 # number of WriteReq miss cycles

834system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles
835system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles

836system.cpu.dcache.demand_miss_latency::cpu.data 33149500 # number of demand (read+write) miss cycles
837system.cpu.dcache.demand_miss_latency::total 33149500 # number of demand (read+write) miss cycles
838system.cpu.dcache.overall_miss_latency::cpu.data 33149500 # number of overall miss cycles
839system.cpu.dcache.overall_miss_latency::total 33149500 # number of overall miss cycles

836system.cpu.dcache.demand_miss_latency::cpu.data 33171500 # number of demand (read+write) miss cycles
837system.cpu.dcache.demand_miss_latency::total 33171500 # number of demand (read+write) miss cycles
838system.cpu.dcache.overall_miss_latency::cpu.data 33171500 # number of overall miss cycles
839system.cpu.dcache.overall_miss_latency::total 33171500 # number of overall miss cycles

840system.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses)
841system.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses)
842system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
843system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
844system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
845system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
846system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
847system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)

--- 6 unchanged lines hidden (view full) ---

854system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses
855system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses
856system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
857system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
858system.cpu.dcache.demand_miss_rate::cpu.data 0.196838 # miss rate for demand accesses
859system.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses
860system.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses
861system.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses

862system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58408.839779 # average ReadReq miss latency
863system.cpu.dcache.ReadReq_avg_miss_latency::total 58408.839779 # average ReadReq miss latency
864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71222.397476 # average WriteReq miss latency
865system.cpu.dcache.WriteReq_avg_miss_latency::total 71222.397476 # average WriteReq miss latency

862system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58524.861878 # average ReadReq miss latency
863system.cpu.dcache.ReadReq_avg_miss_latency::total 58524.861878 # average ReadReq miss latency
864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71225.552050 # average WriteReq miss latency
865system.cpu.dcache.WriteReq_avg_miss_latency::total 71225.552050 # average WriteReq miss latency

866system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency
867system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency

868system.cpu.dcache.demand_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency
869system.cpu.dcache.demand_avg_miss_latency::total 66565.261044 # average overall miss latency
870system.cpu.dcache.overall_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency
871system.cpu.dcache.overall_avg_miss_latency::total 66565.261044 # average overall miss latency

868system.cpu.dcache.demand_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency
869system.cpu.dcache.demand_avg_miss_latency::total 66609.437751 # average overall miss latency
870system.cpu.dcache.overall_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency
871system.cpu.dcache.overall_avg_miss_latency::total 66609.437751 # average overall miss latency

872system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked
873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
874system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
876system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked
877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
878system.cpu.dcache.fast_writes 0 # number of fast writes performed
879system.cpu.dcache.cache_copies 0 # number of cache copies performed

--- 10 unchanged lines hidden (view full) ---

890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses
891system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
893system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
894system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
895system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
896system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
897system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses

898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6969000 # number of ReadReq MSHR miss cycles
899system.cpu.dcache.ReadReq_mshr_miss_latency::total 6969000 # number of ReadReq MSHR miss cycles
900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3397000 # number of WriteReq MSHR miss cycles
901system.cpu.dcache.WriteReq_mshr_miss_latency::total 3397000 # number of WriteReq MSHR miss cycles
902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10366000 # number of demand (read+write) MSHR miss cycles
903system.cpu.dcache.demand_mshr_miss_latency::total 10366000 # number of demand (read+write) MSHR miss cycles
904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10366000 # number of overall MSHR miss cycles
905system.cpu.dcache.overall_mshr_miss_latency::total 10366000 # number of overall MSHR miss cycles

898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6985000 # number of ReadReq MSHR miss cycles
899system.cpu.dcache.ReadReq_mshr_miss_latency::total 6985000 # number of ReadReq MSHR miss cycles
900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles
901system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles
902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10383000 # number of demand (read+write) MSHR miss cycles
903system.cpu.dcache.demand_mshr_miss_latency::total 10383000 # number of demand (read+write) MSHR miss cycles
904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10383000 # number of overall MSHR miss cycles
905system.cpu.dcache.overall_mshr_miss_latency::total 10383000 # number of overall MSHR miss cycles

906system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses
907system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses
908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
909system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for demand accesses
911system.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses
912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses
913system.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses

914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66371.428571 # average ReadReq mshr miss latency
915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66371.428571 # average ReadReq mshr miss latency
916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80880.952381 # average WriteReq mshr miss latency
917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80880.952381 # average WriteReq mshr miss latency
918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency
919system.cpu.dcache.demand_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency
920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency
921system.cpu.dcache.overall_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency

914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66523.809524 # average ReadReq mshr miss latency
915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66523.809524 # average ReadReq mshr miss latency
916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency
917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency
918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency
919system.cpu.dcache.demand_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency
920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency
921system.cpu.dcache.overall_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency

922system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
923system.cpu.icache.tags.replacements 1 # number of replacements

924system.cpu.icache.tags.tagsinuse 149.741808 # Cycle average of tags in use
925system.cpu.icache.tags.total_refs 1582 # Total number of references to valid blocks.

924system.cpu.icache.tags.tagsinuse 149.742670 # Cycle average of tags in use
925system.cpu.icache.tags.total_refs 1585 # Total number of references to valid blocks.

926system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks.

927system.cpu.icache.tags.avg_refs 5.399317 # Average number of references to valid blocks.

927system.cpu.icache.tags.avg_refs 5.409556 # Average number of references to valid blocks.

928system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

929system.cpu.icache.tags.occ_blocks::cpu.inst 149.741808 # Average occupied blocks per requestor
930system.cpu.icache.tags.occ_percent::cpu.inst 0.073116 # Average percentage of cache occupancy
931system.cpu.icache.tags.occ_percent::total 0.073116 # Average percentage of cache occupancy

929system.cpu.icache.tags.occ_blocks::cpu.inst 149.742670 # Average occupied blocks per requestor
930system.cpu.icache.tags.occ_percent::cpu.inst 0.073117 # Average percentage of cache occupancy
931system.cpu.icache.tags.occ_percent::total 0.073117 # Average percentage of cache occupancy

932system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
933system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
934system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
935system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id

936system.cpu.icache.tags.tag_accesses 4229 # Number of tag accesses
937system.cpu.icache.tags.data_accesses 4229 # Number of data accesses
938system.cpu.icache.ReadReq_hits::cpu.inst 1582 # number of ReadReq hits
939system.cpu.icache.ReadReq_hits::total 1582 # number of ReadReq hits
940system.cpu.icache.demand_hits::cpu.inst 1582 # number of demand (read+write) hits
941system.cpu.icache.demand_hits::total 1582 # number of demand (read+write) hits
942system.cpu.icache.overall_hits::cpu.inst 1582 # number of overall hits
943system.cpu.icache.overall_hits::total 1582 # number of overall hits

936system.cpu.icache.tags.tag_accesses 4235 # Number of tag accesses
937system.cpu.icache.tags.data_accesses 4235 # Number of data accesses
938system.cpu.icache.ReadReq_hits::cpu.inst 1585 # number of ReadReq hits
939system.cpu.icache.ReadReq_hits::total 1585 # number of ReadReq hits
940system.cpu.icache.demand_hits::cpu.inst 1585 # number of demand (read+write) hits
941system.cpu.icache.demand_hits::total 1585 # number of demand (read+write) hits
942system.cpu.icache.overall_hits::cpu.inst 1585 # number of overall hits
943system.cpu.icache.overall_hits::total 1585 # number of overall hits

944system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses
945system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses
946system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses
947system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses
948system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses
949system.cpu.icache.overall_misses::total 386 # number of overall misses

950system.cpu.icache.ReadReq_miss_latency::cpu.inst 26869500 # number of ReadReq miss cycles
951system.cpu.icache.ReadReq_miss_latency::total 26869500 # number of ReadReq miss cycles
952system.cpu.icache.demand_miss_latency::cpu.inst 26869500 # number of demand (read+write) miss cycles
953system.cpu.icache.demand_miss_latency::total 26869500 # number of demand (read+write) miss cycles
954system.cpu.icache.overall_miss_latency::cpu.inst 26869500 # number of overall miss cycles
955system.cpu.icache.overall_miss_latency::total 26869500 # number of overall miss cycles
956system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses)
957system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses)
958system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses
959system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses
960system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses
961system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses
962system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196138 # miss rate for ReadReq accesses
963system.cpu.icache.ReadReq_miss_rate::total 0.196138 # miss rate for ReadReq accesses
964system.cpu.icache.demand_miss_rate::cpu.inst 0.196138 # miss rate for demand accesses
965system.cpu.icache.demand_miss_rate::total 0.196138 # miss rate for demand accesses
966system.cpu.icache.overall_miss_rate::cpu.inst 0.196138 # miss rate for overall accesses
967system.cpu.icache.overall_miss_rate::total 0.196138 # miss rate for overall accesses
968system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69610.103627 # average ReadReq miss latency
969system.cpu.icache.ReadReq_avg_miss_latency::total 69610.103627 # average ReadReq miss latency
970system.cpu.icache.demand_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency
971system.cpu.icache.demand_avg_miss_latency::total 69610.103627 # average overall miss latency
972system.cpu.icache.overall_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency
973system.cpu.icache.overall_avg_miss_latency::total 69610.103627 # average overall miss latency

950system.cpu.icache.ReadReq_miss_latency::cpu.inst 26879500 # number of ReadReq miss cycles
951system.cpu.icache.ReadReq_miss_latency::total 26879500 # number of ReadReq miss cycles
952system.cpu.icache.demand_miss_latency::cpu.inst 26879500 # number of demand (read+write) miss cycles
953system.cpu.icache.demand_miss_latency::total 26879500 # number of demand (read+write) miss cycles
954system.cpu.icache.overall_miss_latency::cpu.inst 26879500 # number of overall miss cycles
955system.cpu.icache.overall_miss_latency::total 26879500 # number of overall miss cycles
956system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses)
957system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses)
958system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses
959system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses
960system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses
961system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses
962system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195840 # miss rate for ReadReq accesses
963system.cpu.icache.ReadReq_miss_rate::total 0.195840 # miss rate for ReadReq accesses
964system.cpu.icache.demand_miss_rate::cpu.inst 0.195840 # miss rate for demand accesses
965system.cpu.icache.demand_miss_rate::total 0.195840 # miss rate for demand accesses
966system.cpu.icache.overall_miss_rate::cpu.inst 0.195840 # miss rate for overall accesses
967system.cpu.icache.overall_miss_rate::total 0.195840 # miss rate for overall accesses
968system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69636.010363 # average ReadReq miss latency
969system.cpu.icache.ReadReq_avg_miss_latency::total 69636.010363 # average ReadReq miss latency
970system.cpu.icache.demand_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency
971system.cpu.icache.demand_avg_miss_latency::total 69636.010363 # average overall miss latency
972system.cpu.icache.overall_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency
973system.cpu.icache.overall_avg_miss_latency::total 69636.010363 # average overall miss latency

974system.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked
975system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
976system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
977system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
978system.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000 # average number of cycles each access was blocked
979system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
980system.cpu.icache.fast_writes 0 # number of fast writes performed
981system.cpu.icache.cache_copies 0 # number of cache copies performed

--- 4 unchanged lines hidden (view full) ---

986system.cpu.icache.overall_mshr_hits::cpu.inst 93 # number of overall MSHR hits
987system.cpu.icache.overall_mshr_hits::total 93 # number of overall MSHR hits
988system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses
989system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses
990system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
991system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses
992system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
993system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses

994system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21385500 # number of ReadReq MSHR miss cycles
995system.cpu.icache.ReadReq_mshr_miss_latency::total 21385500 # number of ReadReq MSHR miss cycles
996system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21385500 # number of demand (read+write) MSHR miss cycles
997system.cpu.icache.demand_mshr_miss_latency::total 21385500 # number of demand (read+write) MSHR miss cycles
998system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21385500 # number of overall MSHR miss cycles
999system.cpu.icache.overall_mshr_miss_latency::total 21385500 # number of overall MSHR miss cycles
1000system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for ReadReq accesses
1001system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148882 # mshr miss rate for ReadReq accesses
1002system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for demand accesses
1003system.cpu.icache.demand_mshr_miss_rate::total 0.148882 # mshr miss rate for demand accesses
1004system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for overall accesses
1005system.cpu.icache.overall_mshr_miss_rate::total 0.148882 # mshr miss rate for overall accesses
1006system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72988.054608 # average ReadReq mshr miss latency
1007system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72988.054608 # average ReadReq mshr miss latency
1008system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency
1009system.cpu.icache.demand_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency
1010system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency
1011system.cpu.icache.overall_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency

994system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21398500 # number of ReadReq MSHR miss cycles
995system.cpu.icache.ReadReq_mshr_miss_latency::total 21398500 # number of ReadReq MSHR miss cycles
996system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21398500 # number of demand (read+write) MSHR miss cycles
997system.cpu.icache.demand_mshr_miss_latency::total 21398500 # number of demand (read+write) MSHR miss cycles
998system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21398500 # number of overall MSHR miss cycles
999system.cpu.icache.overall_mshr_miss_latency::total 21398500 # number of overall MSHR miss cycles
1000system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for ReadReq accesses
1001system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148656 # mshr miss rate for ReadReq accesses
1002system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for demand accesses
1003system.cpu.icache.demand_mshr_miss_rate::total 0.148656 # mshr miss rate for demand accesses
1004system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for overall accesses
1005system.cpu.icache.overall_mshr_miss_rate::total 0.148656 # mshr miss rate for overall accesses
1006system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73032.423208 # average ReadReq mshr miss latency
1007system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73032.423208 # average ReadReq mshr miss latency
1008system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency
1009system.cpu.icache.demand_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency
1010system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency
1011system.cpu.icache.overall_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency

1012system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1013system.cpu.l2cache.tags.replacements 0 # number of replacements

1014system.cpu.l2cache.tags.tagsinuse 187.228350 # Cycle average of tags in use

1014system.cpu.l2cache.tags.tagsinuse 187.228140 # Cycle average of tags in use

1015system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
1016system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks.
1017system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks.
1018system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1019system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.551776 # Average occupied blocks per requestor
1020system.cpu.l2cache.tags.occ_blocks::cpu.data 46.676574 # Average occupied blocks per requestor

1019system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.553706 # Average occupied blocks per requestor
1020system.cpu.l2cache.tags.occ_blocks::cpu.data 46.674434 # Average occupied blocks per requestor

1021system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy
1022system.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy
1023system.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy
1024system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
1025system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
1026system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
1027system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id
1028system.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses

--- 17 unchanged lines hidden (view full) ---

1046system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses
1047system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses
1048system.cpu.l2cache.demand_misses::total 401 # number of demand (read+write) misses
1049system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses
1050system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses
1051system.cpu.l2cache.overall_misses::total 401 # number of overall misses
1052system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles
1053system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles

1054system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20756000 # number of ReadCleanReq miss cycles
1055system.cpu.l2cache.ReadCleanReq_miss_latency::total 20756000 # number of ReadCleanReq miss cycles
1056system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6584500 # number of ReadSharedReq miss cycles
1057system.cpu.l2cache.ReadSharedReq_miss_latency::total 6584500 # number of ReadSharedReq miss cycles
1058system.cpu.l2cache.demand_miss_latency::cpu.inst 20756000 # number of demand (read+write) miss cycles
1059system.cpu.l2cache.demand_miss_latency::cpu.data 9917500 # number of demand (read+write) miss cycles
1060system.cpu.l2cache.demand_miss_latency::total 30673500 # number of demand (read+write) miss cycles
1061system.cpu.l2cache.overall_miss_latency::cpu.inst 20756000 # number of overall miss cycles
1062system.cpu.l2cache.overall_miss_latency::cpu.data 9917500 # number of overall miss cycles
1063system.cpu.l2cache.overall_miss_latency::total 30673500 # number of overall miss cycles

1054system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20751000 # number of ReadCleanReq miss cycles
1055system.cpu.l2cache.ReadCleanReq_miss_latency::total 20751000 # number of ReadCleanReq miss cycles
1056system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6579500 # number of ReadSharedReq miss cycles
1057system.cpu.l2cache.ReadSharedReq_miss_latency::total 6579500 # number of ReadSharedReq miss cycles
1058system.cpu.l2cache.demand_miss_latency::cpu.inst 20751000 # number of demand (read+write) miss cycles
1059system.cpu.l2cache.demand_miss_latency::cpu.data 9912500 # number of demand (read+write) miss cycles
1060system.cpu.l2cache.demand_miss_latency::total 30663500 # number of demand (read+write) miss cycles
1061system.cpu.l2cache.overall_miss_latency::cpu.inst 20751000 # number of overall miss cycles
1062system.cpu.l2cache.overall_miss_latency::cpu.data 9912500 # number of overall miss cycles
1063system.cpu.l2cache.overall_miss_latency::total 30663500 # number of overall miss cycles

1064system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
1065system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
1066system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses)
1067system.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses)
1068system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses)
1069system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses)
1070system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses
1071system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses

--- 10 unchanged lines hidden (view full) ---

1082system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses
1083system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses
1084system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses
1085system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses
1086system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses
1087system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses
1088system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency
1089system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency

1090system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75476.363636 # average ReadCleanReq miss latency
1091system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75476.363636 # average ReadCleanReq miss latency
1092system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78386.904762 # average ReadSharedReq miss latency
1093system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78386.904762 # average ReadSharedReq miss latency
1094system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency
1095system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency
1096system.cpu.l2cache.demand_avg_miss_latency::total 76492.518703 # average overall miss latency
1097system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency
1098system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency
1099system.cpu.l2cache.overall_avg_miss_latency::total 76492.518703 # average overall miss latency

1090system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75458.181818 # average ReadCleanReq miss latency
1091system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75458.181818 # average ReadCleanReq miss latency
1092system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78327.380952 # average ReadSharedReq miss latency
1093system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78327.380952 # average ReadSharedReq miss latency
1094system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency
1095system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency
1096system.cpu.l2cache.demand_avg_miss_latency::total 76467.581047 # average overall miss latency
1097system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency
1098system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency
1099system.cpu.l2cache.overall_avg_miss_latency::total 76467.581047 # average overall miss latency

1100system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1101system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1102system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1103system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1104system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1105system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1106system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1107system.cpu.l2cache.cache_copies 0 # number of cache copies performed

--- 12 unchanged lines hidden (view full) ---

1120system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
1121system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses
1122system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses
1123system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
1124system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses
1125system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses
1126system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles
1127system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles

1128system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18006000 # number of ReadCleanReq MSHR miss cycles
1129system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18006000 # number of ReadCleanReq MSHR miss cycles
1130system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5464000 # number of ReadSharedReq MSHR miss cycles
1131system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5464000 # number of ReadSharedReq MSHR miss cycles
1132system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18006000 # number of demand (read+write) MSHR miss cycles
1133system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8377000 # number of demand (read+write) MSHR miss cycles
1134system.cpu.l2cache.demand_mshr_miss_latency::total 26383000 # number of demand (read+write) MSHR miss cycles
1135system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18006000 # number of overall MSHR miss cycles
1136system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8377000 # number of overall MSHR miss cycles
1137system.cpu.l2cache.overall_mshr_miss_latency::total 26383000 # number of overall MSHR miss cycles

1128system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18001000 # number of ReadCleanReq MSHR miss cycles
1129system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18001000 # number of ReadCleanReq MSHR miss cycles
1130system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5459000 # number of ReadSharedReq MSHR miss cycles
1131system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5459000 # number of ReadSharedReq MSHR miss cycles
1132system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18001000 # number of demand (read+write) MSHR miss cycles
1133system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8372000 # number of demand (read+write) MSHR miss cycles
1134system.cpu.l2cache.demand_mshr_miss_latency::total 26373000 # number of demand (read+write) MSHR miss cycles
1135system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18001000 # number of overall MSHR miss cycles
1136system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8372000 # number of overall MSHR miss cycles
1137system.cpu.l2cache.overall_mshr_miss_latency::total 26373000 # number of overall MSHR miss cycles

1138system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
1139system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
1140system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses
1141system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses
1142system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses
1143system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses
1144system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses
1145system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses
1146system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses
1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses
1148system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses
1149system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses
1150system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency
1151system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency

1152system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65476.363636 # average ReadCleanReq mshr miss latency
1153system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65476.363636 # average ReadCleanReq mshr miss latency
1154system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69164.556962 # average ReadSharedReq mshr miss latency
1155system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962 # average ReadSharedReq mshr miss latency
1156system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency
1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency
1158system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency
1159system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency
1160system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency
1161system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency

1152system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65458.181818 # average ReadCleanReq mshr miss latency
1153system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65458.181818 # average ReadCleanReq mshr miss latency
1154system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69101.265823 # average ReadSharedReq mshr miss latency
1155system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69101.265823 # average ReadSharedReq mshr miss latency
1156system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency
1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency
1158system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency
1159system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency
1160system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency
1161system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency

1162system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

1163system.cpu.toL2Bus.snoop_filter.tot_requests 441 # Total number of requests made to the snoop filter.
1164system.cpu.toL2Bus.snoop_filter.hit_single_requests 44 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1165system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1166system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1167system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1168system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1163system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
1164system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
1165system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
1166system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution
1167system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution
1168system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes)
1169system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
1170system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes)
1171system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
1172system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
1173system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
1174system.cpu.toL2Bus.snoops 0 # Total snoops (count)
1175system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram

1169system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
1170system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
1171system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
1172system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution
1173system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution
1174system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes)
1175system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
1176system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes)
1177system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
1178system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
1179system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
1180system.cpu.toL2Bus.snoops 0 # Total snoops (count)
1181system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram

1176system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
1177system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram

1182system.cpu.toL2Bus.snoop_fanout::mean 0.102041 # Request fanout histogram
1183system.cpu.toL2Bus.snoop_fanout::stdev 0.303046 # Request fanout histogram

1178system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1184system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1179system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1180system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram

1185system.cpu.toL2Bus.snoop_fanout::0 396 89.80% 89.80% # Request fanout histogram
1186system.cpu.toL2Bus.snoop_fanout::1 45 10.20% 100.00% # Request fanout histogram

1181system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1182system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1187system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1188system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1183system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram

1189system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram