| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17307500 # Number of ticks simulated 5final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 56147 # Simulator instruction rate (inst/s) 8host_op_rate 65749 # Simulator op (including micro ops) rate (op/s) --- 759 unchanged lines hidden (view full) --- 768system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 769system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 770system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 771system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 772system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 773system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 774system.cpu.commit.op_class_0::total 5377 # Class of committed instruction 775system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17307500 # Number of ticks simulated 5final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 56147 # Simulator instruction rate (inst/s) 8host_op_rate 65749 # Simulator op (including micro ops) rate (op/s) --- 759 unchanged lines hidden (view full) --- 768system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 769system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 770system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 771system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 772system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 773system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 774system.cpu.commit.op_class_0::total 5377 # Class of committed instruction 775system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached |
| 776system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 777system.cpu.rob.rob_reads 22770 # The number of ROB reads 778system.cpu.rob.rob_writes 21679 # The number of ROB writes 779system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself 780system.cpu.idleCycles 21096 # Total number of cycles that the CPU has spent unscheduled due to idling 781system.cpu.committedInsts 4591 # Number of Instructions Simulated 782system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated 783system.cpu.cpi 7.539970 # CPI: Cycles Per Instruction 784system.cpu.cpi_total 7.539970 # CPI: Total CPI of All Threads --- 426 unchanged lines hidden --- | 776system.cpu.rob.rob_reads 22770 # The number of ROB reads 777system.cpu.rob.rob_writes 21679 # The number of ROB writes 778system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself 779system.cpu.idleCycles 21096 # Total number of cycles that the CPU has spent unscheduled due to idling 780system.cpu.committedInsts 4591 # Number of Instructions Simulated 781system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated 782system.cpu.cpi 7.539970 # CPI: Cycles Per Instruction 783system.cpu.cpi_total 7.539970 # CPI: Total CPI of All Threads --- 426 unchanged lines hidden --- |