| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16223000 # Number of ticks simulated 5final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16223000 # Number of ticks simulated 5final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 26356 # Simulator instruction rate (inst/s) 8host_op_rate 30865 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 93111675 # Simulator tick rate (ticks/s) 10host_mem_usage 251576 # Number of bytes of host memory used 11host_seconds 0.17 # Real time elapsed on the host | 7host_inst_rate 54860 # Simulator instruction rate (inst/s) 8host_op_rate 64243 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 193800024 # Simulator tick rate (ticks/s) 10host_mem_usage 308908 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host |
| 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory --- 196 unchanged lines hidden (view full) --- 216system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 331 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes 220system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 40695.21 # Average gap between requests 223system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined | 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory --- 196 unchanged lines hidden (view full) --- 216system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 331 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes 220system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 40695.21 # Average gap between requests 223system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined |
| 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 225system.physmem.memoryStateTime::REF 520000 # Time in different power states 226system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 227system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 228system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 229system.physmem.actEnergy::0 317520 # Energy for activate commands per rank (pJ) 230system.physmem.actEnergy::1 151200 # Energy for activate commands per rank (pJ) 231system.physmem.preEnergy::0 173250 # Energy for precharge commands per rank (pJ) 232system.physmem.preEnergy::1 82500 # Energy for precharge commands per rank (pJ) 233system.physmem.readEnergy::0 2238600 # Energy for read commands per rank (pJ) 234system.physmem.readEnergy::1 795600 # Energy for read commands per rank (pJ) 235system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 236system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 237system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) 238system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) 239system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) 240system.physmem.actBackEnergy::1 10477170 # Energy for active background per rank (pJ) 241system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) 242system.physmem.preBackEnergy::1 309000 # Energy for precharge background per rank (pJ) 243system.physmem.totalEnergy::0 14571510 # Total energy per rank (pJ) 244system.physmem.totalEnergy::1 12832590 # Total energy per rank (pJ) 245system.physmem.averagePower::0 920.354334 # Core power per rank (mW) 246system.physmem.averagePower::1 810.522027 # Core power per rank (mW) 247system.membus.trans_dist::ReadReq 355 # Transaction distribution 248system.membus.trans_dist::ReadResp 355 # Transaction distribution 249system.membus.trans_dist::ReadExReq 42 # Transaction distribution 250system.membus.trans_dist::ReadExResp 42 # Transaction distribution 251system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 252system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 253system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 254system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 255system.membus.snoops 0 # Total snoops (count) 256system.membus.snoop_fanout::samples 397 # Request fanout histogram 257system.membus.snoop_fanout::mean 0 # Request fanout histogram 258system.membus.snoop_fanout::stdev 0 # Request fanout histogram 259system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 260system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 261system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 262system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 263system.membus.snoop_fanout::min_value 0 # Request fanout histogram 264system.membus.snoop_fanout::max_value 0 # Request fanout histogram 265system.membus.snoop_fanout::total 397 # Request fanout histogram 266system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) 267system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 268system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) 269system.membus.respLayer1.utilization 22.8 # Layer utilization (%) 270system.cpu_clk_domain.clock 500 # Clock period in ticks | 224system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) 225system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) 226system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) 227system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 229system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) 230system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) 231system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) 232system.physmem_0.averagePower 920.354334 # Core power per rank (mW) 233system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states 234system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 235system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 236system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states 237system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 239system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 240system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) 241system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 243system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) 244system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) 246system.physmem_1.averagePower 810.522027 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states 248system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 271system.cpu.branchPred.lookups 2638 # Number of BP lookups 272system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted 273system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect 274system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups 275system.cpu.branchPred.BTBHits 783 # Number of BTB hits 276system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 277system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage 278system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. 279system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. | 252system.cpu.branchPred.lookups 2638 # Number of BP lookups 253system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups 256system.cpu.branchPred.BTBHits 783 # Number of BTB hits 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 258system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. 260system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. |
| 261system.cpu_clk_domain.clock 500 # Clock period in ticks 262system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 263system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 264system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 265system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 266system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 267system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 268system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 280system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 281system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 282system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 283system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 284system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 285system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 286system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 287system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 293system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 294system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 295system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 296system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 297system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 298system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 299system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 300system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 270system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 271system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 272system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 273system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 274system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 275system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 276system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 277system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 283system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 284system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 285system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 286system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 287system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 288system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 289system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 290system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 291system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 292system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 293system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 294system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 295system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 296system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 297system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 298system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 301system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 302system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 303system.cpu.checker.dtb.read_hits 0 # DTB read hits 304system.cpu.checker.dtb.read_misses 0 # DTB read misses 305system.cpu.checker.dtb.write_hits 0 # DTB write hits 306system.cpu.checker.dtb.write_misses 0 # DTB write misses 307system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 308system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 314system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 315system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 316system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 317system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 318system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 319system.cpu.checker.dtb.hits 0 # DTB hits 320system.cpu.checker.dtb.misses 0 # DTB misses 321system.cpu.checker.dtb.accesses 0 # DTB accesses | 299system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 300system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 301system.cpu.checker.dtb.read_hits 0 # DTB read hits 302system.cpu.checker.dtb.read_misses 0 # DTB read misses 303system.cpu.checker.dtb.write_hits 0 # DTB write hits 304system.cpu.checker.dtb.write_misses 0 # DTB write misses 305system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 306system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 312system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 313system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 314system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 315system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 316system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 317system.cpu.checker.dtb.hits 0 # DTB hits 318system.cpu.checker.dtb.misses 0 # DTB misses 319system.cpu.checker.dtb.accesses 0 # DTB accesses |
| 320system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 321system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 322system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 323system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 324system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 325system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 326system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 327system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 322system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 323system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 324system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 325system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 326system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 327system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 328system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 329system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 335system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 336system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 338system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 339system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 340system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 341system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 342system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 328system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 329system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 330system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 331system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 332system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 333system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 334system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 335system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 341system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 342system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 343system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 344system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 345system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 346system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 347system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 348system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 349system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 350system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 353system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 356system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 343system.cpu.checker.itb.inst_hits 0 # ITB inst hits 344system.cpu.checker.itb.inst_misses 0 # ITB inst misses 345system.cpu.checker.itb.read_hits 0 # DTB read hits 346system.cpu.checker.itb.read_misses 0 # DTB read misses 347system.cpu.checker.itb.write_hits 0 # DTB write hits 348system.cpu.checker.itb.write_misses 0 # DTB write misses 349system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 350system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 9 unchanged lines hidden (view full) --- 360system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 361system.cpu.checker.itb.hits 0 # DTB hits 362system.cpu.checker.itb.misses 0 # DTB misses 363system.cpu.checker.itb.accesses 0 # DTB accesses 364system.cpu.workload.num_syscalls 13 # Number of system calls 365system.cpu.checker.numCycles 5390 # number of cpu cycles simulated 366system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 367system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed | 357system.cpu.checker.itb.inst_hits 0 # ITB inst hits 358system.cpu.checker.itb.inst_misses 0 # ITB inst misses 359system.cpu.checker.itb.read_hits 0 # DTB read hits 360system.cpu.checker.itb.read_misses 0 # DTB read misses 361system.cpu.checker.itb.write_hits 0 # DTB write hits 362system.cpu.checker.itb.write_misses 0 # DTB write misses 363system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 364system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 9 unchanged lines hidden (view full) --- 374system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 375system.cpu.checker.itb.hits 0 # DTB hits 376system.cpu.checker.itb.misses 0 # DTB misses 377system.cpu.checker.itb.accesses 0 # DTB accesses 378system.cpu.workload.num_syscalls 13 # Number of system calls 379system.cpu.checker.numCycles 5390 # number of cpu cycles simulated 380system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 381system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 382system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 383system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 384system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 386system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 387system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 389system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 368system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 369system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 370system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 371system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 372system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 373system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 374system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 375system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 381system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 382system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 384system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 385system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 386system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 387system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 388system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 390system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 391system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 392system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 393system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 394system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 395system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 396system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 397system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 403system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 404system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 405system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 406system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 407system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 408system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 409system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 410system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 411system.cpu.dtb.walker.walks 0 # Table walker walks requested 412system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 413system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 389system.cpu.dtb.inst_hits 0 # ITB inst hits 390system.cpu.dtb.inst_misses 0 # ITB inst misses 391system.cpu.dtb.read_hits 0 # DTB read hits 392system.cpu.dtb.read_misses 0 # DTB read misses 393system.cpu.dtb.write_hits 0 # DTB write hits 394system.cpu.dtb.write_misses 0 # DTB write misses 395system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 396system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 402system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 403system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 404system.cpu.dtb.read_accesses 0 # DTB read accesses 405system.cpu.dtb.write_accesses 0 # DTB write accesses 406system.cpu.dtb.inst_accesses 0 # ITB inst accesses 407system.cpu.dtb.hits 0 # DTB hits 408system.cpu.dtb.misses 0 # DTB misses 409system.cpu.dtb.accesses 0 # DTB accesses | 419system.cpu.dtb.inst_hits 0 # ITB inst hits 420system.cpu.dtb.inst_misses 0 # ITB inst misses 421system.cpu.dtb.read_hits 0 # DTB read hits 422system.cpu.dtb.read_misses 0 # DTB read misses 423system.cpu.dtb.write_hits 0 # DTB write hits 424system.cpu.dtb.write_misses 0 # DTB write misses 425system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 426system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 432system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 433system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 434system.cpu.dtb.read_accesses 0 # DTB read accesses 435system.cpu.dtb.write_accesses 0 # DTB write accesses 436system.cpu.dtb.inst_accesses 0 # ITB inst accesses 437system.cpu.dtb.hits 0 # DTB hits 438system.cpu.dtb.misses 0 # DTB misses 439system.cpu.dtb.accesses 0 # DTB accesses |
| 440system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 410system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 411system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 412system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 413system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 414system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 415system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 416system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 417system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 423system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 424system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 425system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 426system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 427system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 428system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 429system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 430system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 448system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 449system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 450system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 451system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 452system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 453system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 454system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 455system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 461system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 462system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 463system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 464system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 465system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 466system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 467system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 468system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 469system.cpu.itb.walker.walks 0 # Table walker walks requested 470system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 471system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 472system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 473system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 474system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 475system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 431system.cpu.itb.inst_hits 0 # ITB inst hits 432system.cpu.itb.inst_misses 0 # ITB inst misses 433system.cpu.itb.read_hits 0 # DTB read hits 434system.cpu.itb.read_misses 0 # DTB read misses 435system.cpu.itb.write_hits 0 # DTB write hits 436system.cpu.itb.write_misses 0 # DTB write misses 437system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 438system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 300 unchanged lines hidden (view full) --- 739system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads 740system.cpu.int_regfile_reads 7945 # number of integer regfile reads 741system.cpu.int_regfile_writes 4420 # number of integer regfile writes 742system.cpu.fp_regfile_reads 31 # number of floating regfile reads 743system.cpu.cc_regfile_reads 28734 # number of cc regfile reads 744system.cpu.cc_regfile_writes 3302 # number of cc regfile writes 745system.cpu.misc_regfile_reads 3189 # number of misc regfile reads 746system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 477system.cpu.itb.inst_hits 0 # ITB inst hits 478system.cpu.itb.inst_misses 0 # ITB inst misses 479system.cpu.itb.read_hits 0 # DTB read hits 480system.cpu.itb.read_misses 0 # DTB read misses 481system.cpu.itb.write_hits 0 # DTB write hits 482system.cpu.itb.write_misses 0 # DTB write misses 483system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 484system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 300 unchanged lines hidden (view full) --- 785system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads 786system.cpu.int_regfile_reads 7945 # number of integer regfile reads 787system.cpu.int_regfile_writes 4420 # number of integer regfile writes 788system.cpu.fp_regfile_reads 31 # number of floating regfile reads 789system.cpu.cc_regfile_reads 28734 # number of cc regfile reads 790system.cpu.cc_regfile_writes 3302 # number of cc regfile writes 791system.cpu.misc_regfile_reads 3189 # number of misc regfile reads 792system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 747system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 748system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 749system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 750system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 751system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) 752system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 753system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) 754system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) 755system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 756system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 757system.cpu.toL2Bus.snoops 0 # Total snoops (count) 758system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 759system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram 760system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 761system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 762system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 763system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 764system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 765system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 766system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 767system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 768system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 769system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram 770system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram 771system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram 772system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram 773system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 774system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram 775system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram 776system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 777system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 778system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) 779system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) 780system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 781system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) 782system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) | 793system.cpu.dcache.tags.replacements 0 # number of replacements 794system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use 795system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. 796system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 797system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. 798system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 799system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor 800system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy 801system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy 802system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 803system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 804system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 805system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 806system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 807system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 808system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits 809system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits 810system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits 811system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits 812system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 813system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 814system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 815system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 816system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits 817system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits 818system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits 819system.cpu.dcache.overall_hits::total 2146 # number of overall hits 820system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses 821system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses 822system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses 823system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses 824system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 825system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 826system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses 827system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses 828system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses 829system.cpu.dcache.overall_misses::total 521 # number of overall misses 830system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles 831system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles 832system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles 833system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles 834system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles 835system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles 836system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles 837system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles 838system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles 839system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles 840system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) 841system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) 842system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 843system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 844system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 845system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 846system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 847system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 848system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses 849system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses 850system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses 851system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses 852system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses 856system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 857system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 858system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses 859system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses 860system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses 861system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses 862system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency 863system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency 865system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency 866system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency 867system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 874system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed 880system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits 881system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits 882system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits 883system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits 884system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 885system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses 907system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses 908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 909system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses 911system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses 912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses 913system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses 914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency 915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency 916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency 917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency 918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency 919system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency 920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency 921system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency 922system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 783system.cpu.icache.tags.replacements 1 # number of replacements 784system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use 785system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. 786system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 787system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. 788system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 789system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor 790system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy --- 214 unchanged lines hidden (view full) --- 1005system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency 1006system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency 1007system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency 1008system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 1009system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency 1010system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency 1011system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 1012system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 923system.cpu.icache.tags.replacements 1 # number of replacements 924system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use 925system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. 926system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 927system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. 928system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 929system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor 930system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy --- 214 unchanged lines hidden (view full) --- 1145system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency 1147system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency 1148system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 1152system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1013system.cpu.dcache.tags.replacements 0 # number of replacements 1014system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use 1015system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. 1016system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 1017system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. 1018system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1019system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor 1020system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy 1021system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy 1022system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 1023system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 1024system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 1025system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 1026system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 1027system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 1028system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits 1029system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits 1030system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits 1031system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits 1032system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 1033system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 1034system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 1035system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 1036system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits 1037system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits 1038system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits 1039system.cpu.dcache.overall_hits::total 2146 # number of overall hits 1040system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses 1041system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses 1042system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses 1043system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses 1044system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 1045system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 1046system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses 1047system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses 1048system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses 1049system.cpu.dcache.overall_misses::total 521 # number of overall misses 1050system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles 1051system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles 1052system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles 1053system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles 1054system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles 1055system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles 1056system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles 1057system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles 1058system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles 1059system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles 1060system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) 1061system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) 1062system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 1063system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 1064system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 1065system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 1066system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 1067system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 1068system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses 1069system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses 1070system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses 1071system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses 1072system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses 1073system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses 1074system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses 1075system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses 1076system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 1077system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 1078system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses 1079system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses 1080system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses 1081system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses 1082system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency 1083system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency 1084system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency 1085system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency 1086system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency 1087system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency 1088system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency 1089system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency 1090system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency 1091system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency 1092system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked 1093system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1094system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 1095system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1096system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked 1097system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1098system.cpu.dcache.fast_writes 0 # number of fast writes performed 1099system.cpu.dcache.cache_copies 0 # number of cache copies performed 1100system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits 1101system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits 1102system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits 1103system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits 1104system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1105system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 1106system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits 1107system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits 1108system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits 1109system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits 1110system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 1111system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 1112system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 1113system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 1114system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 1115system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 1116system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 1117system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 1118system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles 1119system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles 1120system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles 1121system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles 1122system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles 1123system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles 1124system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles 1125system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles 1126system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses 1127system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses 1128system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 1129system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 1130system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses 1131system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses 1132system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses 1133system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses 1134system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency 1135system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency 1136system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency 1137system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency 1138system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency 1139system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency 1140system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency 1141system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency 1142system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1153system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 1157system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1164system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 1183system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 1184system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) 1185system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) 1186system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 1187system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) 1188system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 1189system.membus.trans_dist::ReadReq 355 # Transaction distribution 1190system.membus.trans_dist::ReadResp 355 # Transaction distribution 1191system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1192system.membus.trans_dist::ReadExResp 42 # Transaction distribution 1193system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 1194system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 1195system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 1196system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 1197system.membus.snoops 0 # Total snoops (count) 1198system.membus.snoop_fanout::samples 397 # Request fanout histogram 1199system.membus.snoop_fanout::mean 0 # Request fanout histogram 1200system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1201system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1202system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 1203system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1204system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1205system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1206system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1207system.membus.snoop_fanout::total 397 # Request fanout histogram 1208system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) 1209system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 1210system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) 1211system.membus.respLayer1.utilization 22.8 # Layer utilization (%) |
| 1143 1144---------- End Simulation Statistics ---------- | 1212 1213---------- End Simulation Statistics ---------- |