| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16223000 # Number of ticks simulated 5final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16223000 # Number of ticks simulated 5final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 32617 # Simulator instruction rate (inst/s) 8host_op_rate 38195 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 115221437 # Simulator tick rate (ticks/s) 10host_mem_usage 253076 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host | 7host_inst_rate 55920 # Simulator instruction rate (inst/s) 8host_op_rate 65484 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 197542740 # Simulator tick rate (ticks/s) 10host_mem_usage 304472 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host |
| 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory --- 65 unchanged lines hidden (view full) --- 85system.physmem.readPktSize::6 397 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory --- 65 unchanged lines hidden (view full) --- 85system.physmem.readPktSize::6 397 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 91 unchanged lines hidden (view full) --- 194system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation | 95system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 91 unchanged lines hidden (view full) --- 194system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation |
| 202system.physmem.totQLat 2970000 # Total ticks spent queuing 203system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM | 202system.physmem.totQLat 3126000 # Total ticks spent queuing 203system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM |
| 204system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers | 204system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers |
| 205system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst | 205system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst |
| 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 207system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst | 207system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst |
| 208system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 12.24 # Data bus utilization in percentage 214system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 40695.21 # Average gap between requests 223system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 225system.physmem.memoryStateTime::REF 520000 # Time in different power states 226system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 227system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 228system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 208system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 12.24 # Data bus utilization in percentage 214system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 40695.21 # Average gap between requests 223system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 225system.physmem.memoryStateTime::REF 520000 # Time in different power states 226system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 227system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 228system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 229system.membus.throughput 1566171485 # Throughput (bytes/s) | |
| 230system.membus.trans_dist::ReadReq 355 # Transaction distribution 231system.membus.trans_dist::ReadResp 355 # Transaction distribution 232system.membus.trans_dist::ReadExReq 42 # Transaction distribution 233system.membus.trans_dist::ReadExResp 42 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) | 229system.membus.trans_dist::ReadReq 355 # Transaction distribution 230system.membus.trans_dist::ReadResp 355 # Transaction distribution 231system.membus.trans_dist::ReadExReq 42 # Transaction distribution 232system.membus.trans_dist::ReadExResp 42 # Transaction distribution 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) |
| 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 238system.membus.data_through_bus 25408 # Total data (bytes) 239system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 235system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 236system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 237system.membus.snoops 0 # Total snoops (count) 238system.membus.snoop_fanout::samples 397 # Request fanout histogram 239system.membus.snoop_fanout::mean 0 # Request fanout histogram 240system.membus.snoop_fanout::stdev 0 # Request fanout histogram 241system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 242system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 243system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 244system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 245system.membus.snoop_fanout::min_value 0 # Request fanout histogram 246system.membus.snoop_fanout::max_value 0 # Request fanout histogram 247system.membus.snoop_fanout::total 397 # Request fanout histogram |
| 240system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) 241system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 242system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) 243system.membus.respLayer1.utilization 22.8 # Layer utilization (%) 244system.cpu_clk_domain.clock 500 # Clock period in ticks 245system.cpu.branchPred.lookups 2638 # Number of BP lookups 246system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted 247system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect --- 465 unchanged lines hidden (view full) --- 713system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads 714system.cpu.int_regfile_reads 7944 # number of integer regfile reads 715system.cpu.int_regfile_writes 4420 # number of integer regfile writes 716system.cpu.fp_regfile_reads 31 # number of floating regfile reads 717system.cpu.cc_regfile_reads 28734 # number of cc regfile reads 718system.cpu.cc_regfile_writes 3302 # number of cc regfile writes 719system.cpu.misc_regfile_reads 3189 # number of misc regfile reads 720system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 248system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) 249system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 250system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) 251system.membus.respLayer1.utilization 22.8 # Layer utilization (%) 252system.cpu_clk_domain.clock 500 # Clock period in ticks 253system.cpu.branchPred.lookups 2638 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect --- 465 unchanged lines hidden (view full) --- 721system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads 722system.cpu.int_regfile_reads 7944 # number of integer regfile reads 723system.cpu.int_regfile_writes 4420 # number of integer regfile writes 724system.cpu.fp_regfile_reads 31 # number of floating regfile reads 725system.cpu.cc_regfile_reads 28734 # number of cc regfile reads 726system.cpu.cc_regfile_writes 3302 # number of cc regfile writes 727system.cpu.misc_regfile_reads 3189 # number of misc regfile reads 728system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 721system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) | |
| 722system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 723system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 724system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 725system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 726system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) 727system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 728system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) | 729system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 730system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 731system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 732system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 733system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) 734system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 735system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) |
| 729system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) 730system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 731system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 732system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) 733system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 736system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) 737system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 738system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 739system.cpu.toL2Bus.snoops 0 # Total snoops (count) 740system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 741system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram 742system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 743system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 744system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 745system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 746system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 747system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 748system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 749system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 750system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 751system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram 752system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram 753system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram 754system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram 755system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 756system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram 757system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram 758system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram |
| 734system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 735system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) 736system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) 737system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 738system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) 739system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 740system.cpu.icache.tags.replacements 1 # number of replacements | 759system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 760system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) 761system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) 762system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 763system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) 764system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 765system.cpu.icache.tags.replacements 1 # number of replacements |
| 741system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use | 766system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use |
| 742system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. 743system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 744system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. 745system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 767system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. 768system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 769system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. 770system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 746system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor 747system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy 748system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy | 771system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor 772system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy 773system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy |
| 749system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id 750system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 751system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 752system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id 753system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses 754system.cpu.icache.tags.data_accesses 4430 # Number of data accesses 755system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits 756system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits 757system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits 758system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits 759system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits 760system.cpu.icache.overall_hits::total 1666 # number of overall hits 761system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses 762system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses 763system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses 764system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses 765system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses 766system.cpu.icache.overall_misses::total 402 # number of overall misses | 774system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id 775system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 776system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 777system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id 778system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses 779system.cpu.icache.tags.data_accesses 4430 # Number of data accesses 780system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits 781system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits 782system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits 783system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits 784system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits 785system.cpu.icache.overall_hits::total 1666 # number of overall hits 786system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses 787system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses 788system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses 789system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses 790system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses 791system.cpu.icache.overall_misses::total 402 # number of overall misses |
| 767system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles 768system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles 769system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles 770system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles 771system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles 772system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles | 792system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles 793system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles 794system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles 795system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles 796system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles 797system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles |
| 773system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) 774system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) 775system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses 776system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses 777system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses 778system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses 779system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses 780system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses 781system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses 782system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses 783system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses 784system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses | 798system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) 799system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) 800system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses 801system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses 802system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses 803system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses 804system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses 805system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses 806system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses 807system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses 808system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses 809system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses |
| 785system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency 786system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency 787system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency 788system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency 789system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency 790system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency | 810system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency 811system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency 812system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency 813system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency 814system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency 815system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency |
| 791system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked 792system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 793system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 794system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 795system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked 796system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 797system.cpu.icache.fast_writes 0 # number of fast writes performed 798system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 803system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits 804system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits 805system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 806system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 807system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 808system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 809system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 810system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses | 816system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked 817system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 818system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 819system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 820system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked 821system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 822system.cpu.icache.fast_writes 0 # number of fast writes performed 823system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 828system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits 829system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits 830system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 831system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 832system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 833system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 834system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 835system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses |
| 811system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles 812system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles 813system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles 814system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles 815system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles 816system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles | 836system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles 837system.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles 838system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles 839system.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles 840system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles 841system.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles |
| 817system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses 818system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses 819system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses 820system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses 821system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses 822system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses | 842system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses 843system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses 844system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses 845system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses 846system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses 847system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses |
| 823system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency 824system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency 825system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency 826system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency 827system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency 828system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency | 848system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency 849system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency 850system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency 851system.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency 852system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency 853system.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency |
| 829system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 830system.cpu.l2cache.tags.replacements 0 # number of replacements | 854system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 855system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 831system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use | 856system.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use |
| 832system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 833system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 834system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 835system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 857system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 858system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 859system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 860system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 836system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor 837system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor 838system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy | 861system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor 862system.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor 863system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy |
| 839system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy | 864system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy |
| 840system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy | 865system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy |
| 841system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 842system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id 843system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 844system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id 845system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses 846system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses 847system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 848system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 859system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 860system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 861system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 862system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 863system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses 864system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 865system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 866system.cpu.l2cache.overall_misses::total 402 # number of overall misses | 866system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 867system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id 868system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 869system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id 870system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses 871system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses 872system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 873system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 884system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 885system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 886system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 887system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 888system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses 889system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 890system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 891system.cpu.l2cache.overall_misses::total 402 # number of overall misses |
| 867system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19251250 # number of ReadReq miss cycles 868system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6010750 # number of ReadReq miss cycles | 892system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles 893system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles |
| 869system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles 870system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles 871system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles | 894system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles 895system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles 896system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles |
| 872system.cpu.l2cache.demand_miss_latency::cpu.inst 19251250 # number of demand (read+write) miss cycles 873system.cpu.l2cache.demand_miss_latency::cpu.data 9112500 # number of demand (read+write) miss cycles | 897system.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles 898system.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles |
| 874system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles | 899system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles |
| 875system.cpu.l2cache.overall_miss_latency::cpu.inst 19251250 # number of overall miss cycles 876system.cpu.l2cache.overall_miss_latency::cpu.data 9112500 # number of overall miss cycles | 900system.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles 901system.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles |
| 877system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles 878system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) 879system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 880system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) 881system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 882system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 883system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses 884system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses --- 7 unchanged lines hidden (view full) --- 892system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 893system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 894system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses 895system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 896system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses 897system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses 898system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 899system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses | 902system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles 903system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) 904system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 905system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) 906system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 907system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 908system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses 909system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses --- 7 unchanged lines hidden (view full) --- 917system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 918system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 919system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses 920system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 921system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses 922system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses 923system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 924system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses |
| 900system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency 901system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency | 925system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency 926system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency |
| 902system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency 903system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency 904system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency | 927system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency 928system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency 929system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency |
| 905system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency 906system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency | 930system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency 931system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency |
| 907system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency | 932system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency |
| 908system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency 909system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency | 933system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency 934system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency |
| 910system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency 911system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 912system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 913system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 914system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 915system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 916system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 917system.cpu.l2cache.fast_writes 0 # number of fast writes performed --- 10 unchanged lines hidden (view full) --- 928system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 929system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 930system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 931system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 932system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 933system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 934system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 935system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses | 935system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency 936system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 937system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 938system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 939system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 940system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 941system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 942system.cpu.l2cache.fast_writes 0 # number of fast writes performed --- 10 unchanged lines hidden (view full) --- 953system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 954system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 955system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 956system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 957system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 958system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 959system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 960system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses |
| 936system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles 937system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles | 961system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles 962system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles |
| 938system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles 939system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles 940system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles | 963system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles 964system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles 965system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles |
| 941system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles 942system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles | 966system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles 967system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles |
| 943system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles | 968system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles |
| 944system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles 945system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles | 969system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles 970system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles |
| 946system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles 947system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses 948system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses 949system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses 950system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 951system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 952system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses 953system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 954system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 955system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses 956system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 957system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses | 971system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles 972system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses 973system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses 974system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses 975system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 976system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 977system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses 978system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 979system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 980system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses 981system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 982system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses |
| 958system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency 959system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency | 983system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency 984system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency |
| 960system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency 961system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency 962system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency | 985system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency 986system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency 987system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency |
| 963system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency 964system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency | 988system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency 989system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency |
| 965system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency | 990system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency |
| 966system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency 967system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency | 991system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency 992system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency |
| 968system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 969system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 970system.cpu.dcache.tags.replacements 0 # number of replacements | 993system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 994system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 995system.cpu.dcache.tags.replacements 0 # number of replacements |
| 971system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use | 996system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use |
| 972system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. 973system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 974system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. 975system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 997system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. 998system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 999system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. 1000system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 976system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor 977system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy 978system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy | 1001system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor 1002system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy 1003system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy |
| 979system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 980system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 981system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 982system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 983system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 984system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 985system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits 986system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits --- 12 unchanged lines hidden (view full) --- 999system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses 1000system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses 1001system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 1002system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 1003system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses 1004system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses 1005system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses 1006system.cpu.dcache.overall_misses::total 521 # number of overall misses | 1004system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 1005system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 1006system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 1007system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 1008system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 1009system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 1010system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits 1011system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits --- 12 unchanged lines hidden (view full) --- 1024system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses 1025system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses 1026system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 1027system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 1028system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses 1029system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses 1030system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses 1031system.cpu.dcache.overall_misses::total 521 # number of overall misses |
| 1007system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles 1008system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles | 1032system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles 1033system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles |
| 1009system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles 1010system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles 1011system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles 1012system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles | 1034system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles 1035system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles 1036system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles 1037system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles |
| 1013system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles 1014system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles 1015system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles 1016system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles | 1038system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles 1039system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles 1040system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles 1041system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles |
| 1017system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) 1018system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) 1019system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 1020system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 1021system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 1022system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 1023system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 1024system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1031system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses 1032system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses 1033system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 1034system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 1035system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses 1036system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses 1037system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses 1038system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses | 1042system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) 1043system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) 1044system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 1045system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 1046system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 1047system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 1048system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 1049system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1056system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses 1057system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses 1058system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 1059system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 1060system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses 1061system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses 1062system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses 1063system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses |
| 1039system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency 1040system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency | 1064system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency 1065system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency |
| 1041system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency 1042system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency 1043system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency 1044system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency | 1066system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency 1067system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency 1068system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency 1069system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency |
| 1045system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency 1046system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency 1047system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency 1048system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency | 1070system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency 1071system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency 1072system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency 1073system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency |
| 1049system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked 1050system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1051system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 1052system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1053system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked 1054system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1055system.cpu.dcache.fast_writes 0 # number of fast writes performed 1056system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 1067system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 1068system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 1069system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 1070system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 1071system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 1072system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 1073system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 1074system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses | 1074system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked 1075system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1076system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 1077system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1078system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked 1079system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1080system.cpu.dcache.fast_writes 0 # number of fast writes performed 1081system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 1092system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 1093system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 1094system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 1095system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 1096system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 1097system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 1098system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 1099system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses |
| 1075system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles 1076system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles | 1100system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles 1101system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles |
| 1077system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles 1078system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles | 1102system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles 1103system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles |
| 1079system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles 1080system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles 1081system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles 1082system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles | 1104system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles 1105system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles 1106system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles 1107system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles |
| 1083system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses 1084system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses 1085system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 1086system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 1087system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses 1088system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses 1089system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses 1090system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses | 1108system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses 1109system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses 1110system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 1111system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 1112system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses 1113system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses 1114system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses 1115system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses |
| 1091system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency 1092system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency | 1116system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency 1117system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency |
| 1093system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency 1094system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency | 1118system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency 1119system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency |
| 1095system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency 1096system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency 1097system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency 1098system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency | 1120system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency 1121system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency 1122system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency 1123system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency |
| 1099system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1100 1101---------- End Simulation Statistics ---------- | 1124system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1125 1126---------- End Simulation Statistics ---------- |