| stats.txt (10036:80e84beef3bb) | stats.txt (10038:7eccd14e2610) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16981000 # Number of ticks simulated 5final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16981000 # Number of ticks simulated 5final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 35724 # Simulator instruction rate (inst/s) 8host_op_rate 44574 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 132106037 # Simulator tick rate (ticks/s) 10host_mem_usage 247896 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host | 7host_inst_rate 39940 # Simulator instruction rate (inst/s) 8host_op_rate 49834 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 147693403 # Simulator tick rate (ticks/s) 10host_mem_usage 267784 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host |
| 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory --- 202 unchanged lines hidden (view full) --- 222system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 223system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 224system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 225system.cpu.branchPred.BTBHits 697 # Number of BTB hits 226system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 227system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 228system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 229system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. | 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory --- 202 unchanged lines hidden (view full) --- 222system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 223system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 224system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 225system.cpu.branchPred.BTBHits 697 # Number of BTB hits 226system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 227system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 228system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 229system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. |
| 230system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 231system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 232system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 233system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 234system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 235system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 236system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 237system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 238system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 239system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 240system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 241system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 242system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 243system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 244system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 245system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 246system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 247system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 248system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 249system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 250system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
|
| 230system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 231system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 232system.cpu.checker.dtb.read_hits 0 # DTB read hits 233system.cpu.checker.dtb.read_misses 0 # DTB read misses 234system.cpu.checker.dtb.write_hits 0 # DTB write hits 235system.cpu.checker.dtb.write_misses 0 # DTB write misses 236system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 237system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 243system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 244system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 245system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 246system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 247system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 248system.cpu.checker.dtb.hits 0 # DTB hits 249system.cpu.checker.dtb.misses 0 # DTB misses 250system.cpu.checker.dtb.accesses 0 # DTB accesses | 251system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 252system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 253system.cpu.checker.dtb.read_hits 0 # DTB read hits 254system.cpu.checker.dtb.read_misses 0 # DTB read misses 255system.cpu.checker.dtb.write_hits 0 # DTB write hits 256system.cpu.checker.dtb.write_misses 0 # DTB write misses 257system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 258system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 264system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 265system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 266system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 267system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 268system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 269system.cpu.checker.dtb.hits 0 # DTB hits 270system.cpu.checker.dtb.misses 0 # DTB misses 271system.cpu.checker.dtb.accesses 0 # DTB accesses |
| 272system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 273system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 274system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 275system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 276system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 277system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 278system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 279system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 280system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 281system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 282system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 283system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 284system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 285system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 286system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 287system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 288system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 289system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 290system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 291system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 292system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
|
| 251system.cpu.checker.itb.inst_hits 0 # ITB inst hits 252system.cpu.checker.itb.inst_misses 0 # ITB inst misses 253system.cpu.checker.itb.read_hits 0 # DTB read hits 254system.cpu.checker.itb.read_misses 0 # DTB read misses 255system.cpu.checker.itb.write_hits 0 # DTB write hits 256system.cpu.checker.itb.write_misses 0 # DTB write misses 257system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 258system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 9 unchanged lines hidden (view full) --- 268system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 269system.cpu.checker.itb.hits 0 # DTB hits 270system.cpu.checker.itb.misses 0 # DTB misses 271system.cpu.checker.itb.accesses 0 # DTB accesses 272system.cpu.workload.num_syscalls 13 # Number of system calls 273system.cpu.checker.numCycles 5742 # number of cpu cycles simulated 274system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 275system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed | 293system.cpu.checker.itb.inst_hits 0 # ITB inst hits 294system.cpu.checker.itb.inst_misses 0 # ITB inst misses 295system.cpu.checker.itb.read_hits 0 # DTB read hits 296system.cpu.checker.itb.read_misses 0 # DTB read misses 297system.cpu.checker.itb.write_hits 0 # DTB write hits 298system.cpu.checker.itb.write_misses 0 # DTB write misses 299system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 300system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 9 unchanged lines hidden (view full) --- 310system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 311system.cpu.checker.itb.hits 0 # DTB hits 312system.cpu.checker.itb.misses 0 # DTB misses 313system.cpu.checker.itb.accesses 0 # DTB accesses 314system.cpu.workload.num_syscalls 13 # Number of system calls 315system.cpu.checker.numCycles 5742 # number of cpu cycles simulated 316system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 317system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 318system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 319system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 320system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 321system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 322system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 323system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 324system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 325system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 327system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 328system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 329system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 330system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 331system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 334system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 335system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 336system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 337system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 338system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
|
| 276system.cpu.dtb.inst_hits 0 # ITB inst hits 277system.cpu.dtb.inst_misses 0 # ITB inst misses 278system.cpu.dtb.read_hits 0 # DTB read hits 279system.cpu.dtb.read_misses 0 # DTB read misses 280system.cpu.dtb.write_hits 0 # DTB write hits 281system.cpu.dtb.write_misses 0 # DTB write misses 282system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 283system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 289system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 290system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 291system.cpu.dtb.read_accesses 0 # DTB read accesses 292system.cpu.dtb.write_accesses 0 # DTB write accesses 293system.cpu.dtb.inst_accesses 0 # ITB inst accesses 294system.cpu.dtb.hits 0 # DTB hits 295system.cpu.dtb.misses 0 # DTB misses 296system.cpu.dtb.accesses 0 # DTB accesses | 339system.cpu.dtb.inst_hits 0 # ITB inst hits 340system.cpu.dtb.inst_misses 0 # ITB inst misses 341system.cpu.dtb.read_hits 0 # DTB read hits 342system.cpu.dtb.read_misses 0 # DTB read misses 343system.cpu.dtb.write_hits 0 # DTB write hits 344system.cpu.dtb.write_misses 0 # DTB write misses 345system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 346system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 352system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 353system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 354system.cpu.dtb.read_accesses 0 # DTB read accesses 355system.cpu.dtb.write_accesses 0 # DTB write accesses 356system.cpu.dtb.inst_accesses 0 # ITB inst accesses 357system.cpu.dtb.hits 0 # DTB hits 358system.cpu.dtb.misses 0 # DTB misses 359system.cpu.dtb.accesses 0 # DTB accesses |
| 360system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 361system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 362system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 363system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 364system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 365system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 366system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 367system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 368system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 370system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 371system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 372system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 373system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 376system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 377system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 378system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 379system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 380system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
|
| 297system.cpu.itb.inst_hits 0 # ITB inst hits 298system.cpu.itb.inst_misses 0 # ITB inst misses 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.write_hits 0 # DTB write hits 302system.cpu.itb.write_misses 0 # DTB write misses 303system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 304system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 56 unchanged lines hidden (view full) --- 361system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst 362system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 363system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 364system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 365system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 366system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 367system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 368system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed | 381system.cpu.itb.inst_hits 0 # ITB inst hits 382system.cpu.itb.inst_misses 0 # ITB inst misses 383system.cpu.itb.read_hits 0 # DTB read hits 384system.cpu.itb.read_misses 0 # DTB read misses 385system.cpu.itb.write_hits 0 # DTB write hits 386system.cpu.itb.write_misses 0 # DTB write misses 387system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 388system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 56 unchanged lines hidden (view full) --- 445system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst 446system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 447system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 448system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 449system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 450system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 451system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 452system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed |
| 369system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made | 453system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made |
| 370system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 371system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 372system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 373system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 374system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 375system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 376system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer 377system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 378system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 379system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 380system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 381system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 382system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 383system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 384system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 385system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling | 454system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 455system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 456system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 457system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 458system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 459system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 460system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer 461system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 462system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 463system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 464system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 465system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 466system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 467system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 468system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 469system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 386system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph | 470system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph |
| 387system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 388system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle --- 170 unchanged lines hidden (view full) --- 565system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 566system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction 567system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads 568system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle 569system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads 570system.cpu.int_regfile_reads 39210 # number of integer regfile reads 571system.cpu.int_regfile_writes 7985 # number of integer regfile writes 572system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 471system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 472system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle --- 170 unchanged lines hidden (view full) --- 649system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 650system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction 651system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads 652system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle 653system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads 654system.cpu.int_regfile_reads 39210 # number of integer regfile reads 655system.cpu.int_regfile_writes 7985 # number of integer regfile writes 656system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 573system.cpu.misc_regfile_reads 2977 # number of misc regfile reads | 657system.cpu.misc_regfile_reads 3239 # number of misc regfile reads |
| 574system.cpu.misc_regfile_writes 24 # number of misc regfile writes 575system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) 576system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 580system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) --- 374 unchanged lines hidden --- | 658system.cpu.misc_regfile_writes 24 # number of misc regfile writes 659system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) 660system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 661system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 662system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 663system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 664system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 665system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) --- 374 unchanged lines hidden --- |