| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10303500 # Number of ticks simulated 5final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 43907 # Simulator instruction rate (inst/s) 8host_op_rate 54769 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 98312554 # Simulator tick rate (ticks/s) 10host_mem_usage 230064 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host |
| 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25664 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 401 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 31system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 32system.cpu.checker.dtb.read_hits 0 # DTB read hits 33system.cpu.checker.dtb.read_misses 0 # DTB read misses 34system.cpu.checker.dtb.write_hits 0 # DTB write hits 35system.cpu.checker.dtb.write_misses 0 # DTB write misses 36system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 374 unchanged lines hidden (view full) --- 412system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles 413system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) 414system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) 415system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses 416system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses 417system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses 418system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses 419system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses |
| 420system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses |
| 421system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses |
| 422system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses |
| 423system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses |
| 424system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses |
| 425system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency |
| 426system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency |
| 427system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency |
| 428system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency |
| 429system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency |
| 430system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency |
| 431system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 432system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 433system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 434system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 435system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 436system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 437system.cpu.icache.fast_writes 0 # number of fast writes performed 438system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 450system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 451system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles 452system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles 453system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles 454system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles 455system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles 456system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles 457system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses |
| 458system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses |
| 459system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses |
| 460system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses |
| 461system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses |
| 462system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses |
| 463system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency |
| 464system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency |
| 465system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency |
| 466system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency |
| 467system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency |
| 468system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency |
| 469system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 470system.cpu.dcache.replacements 0 # number of replacements 471system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use 472system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. 473system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. 474system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. 475system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 476system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 516system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 517system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 518system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 519system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses 520system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses 521system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses 522system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses 523system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses |
| 524system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses |
| 525system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses |
| 526system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses |
| 527system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses |
| 528system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses |
| 529system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses |
| 530system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses |
| 531system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses |
| 532system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses |
| 533system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency |
| 534system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency |
| 535system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency |
| 536system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency |
| 537system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency |
| 538system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency |
| 539system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency |
| 540system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency |
| 541system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency |
| 542system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency |
| 543system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 544system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 545system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 546system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 547system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 548system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 549system.cpu.dcache.fast_writes 0 # number of fast writes performed 550system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 19 unchanged lines hidden (view full) --- 570system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles 571system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles 572system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles 573system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles 574system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles 575system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles 576system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles 577system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses |
| 578system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses |
| 579system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses |
| 580system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses |
| 581system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses |
| 582system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses |
| 583system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses |
| 584system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses |
| 585system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency |
| 586system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency |
| 587system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency |
| 588system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency |
| 589system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency |
| 590system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency |
| 591system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency |
| 592system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency |
| 593system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 594system.cpu.l2cache.replacements 0 # number of replacements 595system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use 596system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. 597system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. 598system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. 599system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 600system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor --- 40 unchanged lines hidden (view full) --- 641system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 642system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses 643system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses 644system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses 645system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses 646system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses 647system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses 648system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses |
| 649system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses |
| 650system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| 651system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 652system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses 653system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses |
| 654system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses |
| 655system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses 656system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses |
| 657system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses |
| 658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency 659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency |
| 660system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency |
| 661system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency |
| 662system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency |
| 663system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 664system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency |
| 665system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency |
| 666system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 667system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency |
| 668system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency |
| 669system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 670system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 671system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 672system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 673system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 674system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 675system.cpu.l2cache.fast_writes 0 # number of fast writes performed 676system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 22 unchanged lines hidden (view full) --- 699system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles 700system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles 701system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles 702system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles 703system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles 704system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles 705system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses 706system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses |
| 707system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses |
| 708system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| 709system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 710system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses 711system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses |
| 712system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses |
| 713system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses 714system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses |
| 715system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses |
| 716system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency 717system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency |
| 718system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency |
| 719system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency |
| 720system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency |
| 721system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency 722system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency |
| 723system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency |
| 724system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency 725system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency |
| 726system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency |
| 727system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 728 729---------- End Simulation Statistics ---------- |