4,5c4,5
< sim_ticks 13371000 # Number of ticks simulated
< final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 13372000 # Number of ticks simulated
> final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 32987 # Simulator instruction rate (inst/s)
< host_op_rate 41149 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 95942804 # Simulator tick rate (ticks/s)
< host_mem_usage 272856 # Number of bytes of host memory used
< host_seconds 0.14 # Real time elapsed on the host
---
> host_inst_rate 16216 # Simulator instruction rate (inst/s)
> host_op_rate 20228 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 47166036 # Simulator tick rate (ticks/s)
> host_mem_usage 230800 # Number of bytes of host memory used
> host_seconds 0.28 # Real time elapsed on the host
22,29c22,29
< system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s)
73c73
< system.physmem.totGap 13312500 # Total gap between requests
---
> system.physmem.totGap 13314500 # Total gap between requests
175c175
< system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s
---
> system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s
177c177
< system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s
---
> system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s
187c187
< system.physmem.avgGap 33788.07 # Average gap between requests
---
> system.physmem.avgGap 33793.15 # Average gap between requests
276c276
< system.cpu.numCycles 26743 # number of cpu cycles simulated
---
> system.cpu.numCycles 26745 # number of cpu cycles simulated
287c287
< system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss
293,299c293,298
< system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked
> system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total)
301,302c300,301
< system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total)
313,315c312,314
< system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle
---
> system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle
317c316
< system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked
330,331c329,330
< system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename
---
> system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename
335,337c334,336
< system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups
340c339
< system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing
355,357c354,356
< system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle
359c358
< system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle
361c360
< system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle
371c370
< system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle
441c440
< system.cpu.iq.rate 0.336088 # Inst issue rate
---
> system.cpu.iq.rate 0.336063 # Inst issue rate
444c443
< system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads
467c466
< system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
485c484
< system.cpu.iew.exec_rate 0.320233 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.320209 # Inst execution rate
491c490
< system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle
529c528
< system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
533,536c532,535
< system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads
543c542
< system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use
548,550c547,549
< system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy
---
> system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy
557,586c556,585
< system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
< system.cpu.icache.overall_misses::total 359 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency
---
> system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
> system.cpu.icache.overall_misses::total 360 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency
595,600c594,599
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
607,624c606,623
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
625a625,758
> system.cpu.l2cache.replacements 0 # number of replacements
> system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
> system.cpu.l2cache.overall_hits::total 40 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
> system.cpu.l2cache.overall_misses::total 399 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
> system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
627c760
< system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
---
> system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use
632,634c765,767
< system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
---
> system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy
657,658c790,791
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles
663,666c796,799
< system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
689,690c822,823
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
695,698c828,831
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency
725,726c858,859
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles
729,732c862,865
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
741,742c874,875
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
745,748c878,881
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
750,883d882
< system.cpu.l2cache.replacements 0 # number of replacements
< system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
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< system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
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< system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
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< system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
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< system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
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< system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
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< system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
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< system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
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< system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
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< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
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< system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
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< system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
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< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
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< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
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< system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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< system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
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< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
< sim_ticks 13371000 # Number of ticks simulated
< final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 13372000 # Number of ticks simulated
> final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 32987 # Simulator instruction rate (inst/s)
< host_op_rate 41149 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 95942804 # Simulator tick rate (ticks/s)
< host_mem_usage 272856 # Number of bytes of host memory used
< host_seconds 0.14 # Real time elapsed on the host
---
> host_inst_rate 16216 # Simulator instruction rate (inst/s)
> host_op_rate 20228 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 47166036 # Simulator tick rate (ticks/s)
> host_mem_usage 230800 # Number of bytes of host memory used
> host_seconds 0.28 # Real time elapsed on the host
22,29c22,29
< system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s)
73c73
< system.physmem.totGap 13312500 # Total gap between requests
---
> system.physmem.totGap 13314500 # Total gap between requests
175c175
< system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s
---
> system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s
177c177
< system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s
---
> system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s
187c187
< system.physmem.avgGap 33788.07 # Average gap between requests
---
> system.physmem.avgGap 33793.15 # Average gap between requests
276c276
< system.cpu.numCycles 26743 # number of cpu cycles simulated
---
> system.cpu.numCycles 26745 # number of cpu cycles simulated
287c287
< system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss
293,299c293,298
< system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked
> system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total)
301,302c300,301
< system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total)
313,315c312,314
< system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle
---
> system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle
317c316
< system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked
330,331c329,330
< system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename
---
> system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename
335,337c334,336
< system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups
340c339
< system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing
355,357c354,356
< system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle
359c358
< system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle
361c360
< system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle
371c370
< system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle
441c440
< system.cpu.iq.rate 0.336088 # Inst issue rate
---
> system.cpu.iq.rate 0.336063 # Inst issue rate
444c443
< system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads
467c466
< system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
485c484
< system.cpu.iew.exec_rate 0.320233 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.320209 # Inst execution rate
491c490
< system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle
529c528
< system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
533,536c532,535
< system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads
543c542
< system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use
548,550c547,549
< system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy
---
> system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy
557,586c556,585
< system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
< system.cpu.icache.overall_misses::total 359 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency
---
> system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
> system.cpu.icache.overall_misses::total 360 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency
595,600c594,599
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
607,624c606,623
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
625a625,758
> system.cpu.l2cache.replacements 0 # number of replacements
> system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
> system.cpu.l2cache.overall_hits::total 40 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
> system.cpu.l2cache.overall_misses::total 399 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
> system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
627c760
< system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
---
> system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use
632,634c765,767
< system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
---
> system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy
657,658c790,791
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles
663,666c796,799
< system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
689,690c822,823
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
695,698c828,831
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency
725,726c858,859
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles
729,732c862,865
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
741,742c874,875
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
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< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
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< system.cpu.l2cache.replacements 0 # number of replacements
< system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
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< system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
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< system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
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< system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
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< system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
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< system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
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< system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
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< system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
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< system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
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< system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
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< system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate