3,5c3,5
< sim_seconds 0.000010 # Number of seconds simulated
< sim_ticks 10062000 # Number of ticks simulated
< final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000013 # Number of seconds simulated
> sim_ticks 13414500 # Number of ticks simulated
> final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 57856 # Simulator instruction rate (inst/s)
< host_op_rate 72170 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 126623534 # Simulator tick rate (ticks/s)
< host_mem_usage 231188 # Number of bytes of host memory used
---
> host_inst_rate 59216 # Simulator instruction rate (inst/s)
> host_op_rate 73866 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 172781643 # Simulator tick rate (ticks/s)
> host_mem_usage 231444 # Number of bytes of host memory used
14c14
< system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
16,19c16,19
< system.physmem.bytes_read::total 25472 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25600 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
21,30c21,30
< system.physmem.num_reads::total 398 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 398 # Total number of read requests seen
---
> system.physmem.num_reads::total 400 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 401 # Total number of read requests seen
32,33c32,33
< system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 25472 # Total number of bytes read from memory
---
> system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 25600 # Total number of bytes read from memory
35c35
< system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize()
---
> system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize()
40,44c40,44
< system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
53c53
< system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
73c73
< system.physmem.totGap 10004500 # Total gap between requests
---
> system.physmem.totGap 13356500 # Total gap between requests
80c80
< system.physmem.readPktSize::6 398 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 401 # Categorize read packet sizes
101,104c101,104
< system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
167,172c167,172
< system.physmem.totQLat 2567898 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests
< system.physmem.totBusLat 1592000 # Total cycles spent in databus access
< system.physmem.totBankLat 6552000 # Total cycles spent in bank access
< system.physmem.avgQLat 6452.01 # Average queueing delay per request
< system.physmem.avgBankLat 16462.31 # Average bank access latency per request
---
> system.physmem.totQLat 2497399 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests
> system.physmem.totBusLat 1604000 # Total cycles spent in databus access
> system.physmem.totBankLat 6636000 # Total cycles spent in bank access
> system.physmem.avgQLat 6227.93 # Average queueing delay per request
> system.physmem.avgBankLat 16548.63 # Average bank access latency per request
174,175c174,175
< system.physmem.avgMemAccLat 26914.32 # Average memory access latency
< system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s
---
> system.physmem.avgMemAccLat 26776.56 # Average memory access latency
> system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s
177c177
< system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s
---
> system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s
180,181c180,181
< system.physmem.busUtil 15.82 # Data bus utilization in percentage
< system.physmem.avgRdQLen 1.06 # Average read queue length over time
---
> system.physmem.busUtil 11.93 # Data bus utilization in percentage
> system.physmem.avgRdQLen 0.80 # Average read queue length over time
183c183
< system.physmem.readRowHits 323 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 326 # Number of row buffer hits during reads
185c185
< system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
187c187
< system.physmem.avgGap 25136.93 # Average gap between requests
---
> system.physmem.avgGap 33307.98 # Average gap between requests
276c276
< system.cpu.numCycles 20125 # number of cpu cycles simulated
---
> system.cpu.numCycles 26830 # number of cpu cycles simulated
279,283c279,283
< system.cpu.BPredUnit.lookups 2519 # Number of BP lookups
< system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted
< system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect
< system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups
< system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits
---
> system.cpu.BPredUnit.lookups 2508 # Number of BP lookups
> system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted
> system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect
> system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups
> system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits
286,293c286,293
< system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
< system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked
---
> system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
> system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked
295,299c295,300
< system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps
> system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total)
301,309c302,310
< system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total)
313,337c314,339
< system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2441 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2242 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename
< system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2440 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups
339,342c341,344
< system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 46 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer
---
> system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer
344,356c346,358
< system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle
---
> system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle
358,366c360,368
< system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle
370c372
< system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle
372,402c374,404
< system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available
406,436c408,438
< system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued
439,445c441,447
< system.cpu.iq.FU_type_0::total 8888 # Type of FU issued
< system.cpu.iq.rate 0.441640 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 8896 # Type of FU issued
> system.cpu.iq.rate 0.331569 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses
447c449
< system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
---
> system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
451c453
< system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores
455,456c457,458
< system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed
462,466c464,468
< system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch
468,470c470,472
< system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
---
> system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall
472,478c474,480
< system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute
480,488c482,490
< system.cpu.iew.exec_nop 0 # number of nop insts executed
< system.cpu.iew.exec_refs 3261 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1428 # Number of branches executed
< system.cpu.iew.exec_stores 1173 # Number of stores executed
< system.cpu.iew.exec_rate 0.421615 # Inst execution rate
< system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 8062 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 3862 # num instructions producing a value
< system.cpu.iew.wb_consumers 7771 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 1 # number of nop insts executed
> system.cpu.iew.exec_refs 3284 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1437 # Number of branches executed
> system.cpu.iew.exec_stores 1174 # Number of stores executed
> system.cpu.iew.exec_rate 0.316996 # Inst execution rate
> system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 8071 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 3897 # num instructions producing a value
> system.cpu.iew.wb_consumers 7827 # num instructions consuming a value
490,491c492,493
< system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back
493c495
< system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit
495,498c497,500
< system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle
500,508c502,510
< system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle
512c514
< system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle
523c525
< system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached
525,528c527,530
< system.cpu.rob.rob_reads 22426 # The number of ROB reads
< system.cpu.rob.rob_writes 23541 # The number of ROB writes
< system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 23385 # The number of ROB reads
> system.cpu.rob.rob_writes 23680 # The number of ROB writes
> system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling
532,537c534,539
< system.cpu.cpi 4.378808 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 4.378808 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.228373 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.228373 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 39006 # number of integer regfile reads
< system.cpu.int_regfile_writes 7962 # number of integer regfile writes
---
> system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 39120 # number of integer regfile reads
> system.cpu.int_regfile_writes 7969 # number of integer regfile writes
539c541
< system.cpu.misc_regfile_reads 15230 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 15172 # number of misc regfile reads
542,545c544,547
< system.cpu.icache.tagsinuse 152.520984 # Cycle average of tags in use
< system.cpu.icache.total_refs 1592 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 5.396610 # Average number of references to valid blocks.
---
> system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use
> system.cpu.icache.total_refs 1570 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks.
547,586c549,588
< system.cpu.icache.occ_blocks::cpu.inst 152.520984 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.074473 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.074473 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits
< system.cpu.icache.overall_hits::total 1592 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 358 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 358 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 358 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 358 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 358 # number of overall misses
< system.cpu.icache.overall_misses::total 358 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11241000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11241000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11241000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11241000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11241000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11241000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183590 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.183590 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.183590 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.183590 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.183590 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.183590 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31399.441341 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 31399.441341 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 31399.441341 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 31399.441341 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits
> system.cpu.icache.overall_hits::total 1570 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses
> system.cpu.icache.overall_misses::total 373 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
588c590
< system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
590c592
< system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked
594,623c596,625
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9141000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9141000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9141000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9141000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9141000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9141000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.151282 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.151282 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.151282 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30986.440678 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30986.440678 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14464500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14464500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14464500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14464500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14464500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14464500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153371 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.153371 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.153371 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48538.590604 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48538.590604 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency
626,629c628,631
< system.cpu.dcache.tagsinuse 87.982117 # Cycle average of tags in use
< system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 15.986301 # Average number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 86.306986 # Cycle average of tags in use
> system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks.
631,637c633,639
< system.cpu.dcache.occ_blocks::cpu.data 87.982117 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.021480 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.021480 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 1717 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1717 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
---
> system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits
642,649c644,651
< system.cpu.dcache.demand_hits::cpu.data 2309 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2309 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2309 # number of overall hits
< system.cpu.dcache.overall_hits::total 2309 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 185 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 185 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 321 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 321 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 2324 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2324 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2324 # number of overall hits
> system.cpu.dcache.overall_hits::total 2324 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses
652,667c654,669
< system.cpu.dcache.demand_misses::cpu.data 506 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 506 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 506 # number of overall misses
< system.cpu.dcache.overall_misses::total 506 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5690000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5690000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10922000 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 53000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 53000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 16612000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16612000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16612000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16612000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1902 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1902 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses
> system.cpu.dcache.overall_misses::total 518 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses)
674,681c676,683
< system.cpu.dcache.demand_accesses::cpu.data 2815 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2815 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2815 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2815 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097266 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.097266 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.351588 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.351588 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses
684,698c686,700
< system.cpu.dcache.demand_miss_rate::cpu.data 0.179751 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.179751 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.179751 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.179751 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30756.756757 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 30756.756757 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34024.922118 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34024.922118 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26500 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26500 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 32830.039526 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 32830.039526 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
700c702
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
702c704
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
706,709c708,711
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits
712,717c714,719
< system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
720,733c722,735
< system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3250000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 3250000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1919000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1919000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5169000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 5169000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5169000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 5169000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054679 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054679 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4906000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4906000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2418500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2418500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7324500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7324500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7324500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7324500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054951 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054951 # mshr miss rate for ReadReq accesses
736,747c738,749
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051865 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.051865 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051865 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.051865 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31250 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31250 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45690.476190 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45690.476190 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35404.109589 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 35404.109589 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35404.109589 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 35404.109589 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.052076 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.052076 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46283.018868 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46283.018868 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57583.333333 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57583.333333 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency
750,753c752,755
< system.cpu.l2cache.tagsinuse 191.265427 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 37 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 0.103933 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tagsinuse 186.094427 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks.
755,768c757,770
< system.cpu.l2cache.occ_blocks::cpu.inst 144.274623 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 46.990804 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::cpu.inst 0.004403 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.001434 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.005837 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
< system.cpu.l2cache.overall_hits::total 37 # number of overall hits
---
> system.cpu.l2cache.occ_blocks::cpu.inst 140.048248 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 46.046179 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::cpu.inst 0.004274 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.001405 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits
> system.cpu.l2cache.overall_hits::total 41 # number of overall hits
770,771c772,773
< system.cpu.l2cache.ReadReq_misses::cpu.data 84 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
775,776c777,778
< system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses
778,793c780,795
< system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses
< system.cpu.l2cache.overall_misses::total 404 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8824000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3115500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 11939500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1876000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 8824000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 4991500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 13815500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 8824000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 4991500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 13815500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
> system.cpu.l2cache.overall_misses::total 405 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13965500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4578500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18544000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2375500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2375500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13965500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 6954000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 20919500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13965500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 6954000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 20919500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 404 # number of ReadReq accesses(hits+misses)
796,804c798,806
< system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942373 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.807692 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.907268 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 446 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 446 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932886 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.801887 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses
807,823c809,825
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942373 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.863014 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.916100 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942373 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.863014 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.916100 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31741.007194 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37089.285714 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 32982.044199 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 44666.666667 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 44666.666667 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31741.007194 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 34196.782178 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31741.007194 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 34196.782178 # average overall miss latency
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency
832d833
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
834,835c835
< system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
837,838c837
< system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
840,843c839,842
< system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
846,865c845,864
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7843874 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2768060 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10611934 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1736536 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1736536 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7843874 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4504596 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 12348470 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7843874 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4504596 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 12348470 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.769231 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892231 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses
868,884c867,883
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency