4,5c4,5
< sim_ticks 10303500 # Number of ticks simulated
< final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 10305000 # Number of ticks simulated
> final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 43907 # Simulator instruction rate (inst/s)
< host_op_rate 54769 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 98312554 # Simulator tick rate (ticks/s)
< host_mem_usage 230064 # Number of bytes of host memory used
< host_seconds 0.10 # Real time elapsed on the host
< sim_insts 4600 # Number of instructions simulated
< sim_ops 5739 # Number of ops (including micro ops) simulated
---
> host_inst_rate 40668 # Simulator instruction rate (inst/s)
> host_op_rate 50741 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 91257316 # Simulator tick rate (ticks/s)
> host_mem_usage 232684 # Number of bytes of host memory used
> host_seconds 0.11 # Real time elapsed on the host
> sim_insts 4591 # Number of instructions simulated
> sim_ops 5729 # Number of ops (including micro ops) simulated
15,16c15,16
< system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
< system.physmem.bytes_read::total 25664 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory
> system.physmem.bytes_read::total 25536 # Number of bytes read from this memory
20,29c20,29
< system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 401 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 399 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s)
73c73
< system.cpu.checker.numCycles 5752 # number of cpu cycles simulated
---
> system.cpu.checker.numCycles 5742 # number of cpu cycles simulated
118c118
< system.cpu.numCycles 20608 # number of cpu cycles simulated
---
> system.cpu.numCycles 20611 # number of cpu cycles simulated
121,125c121,125
< system.cpu.BPredUnit.lookups 2552 # Number of BP lookups
< system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted
< system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect
< system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups
< system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits
---
> system.cpu.BPredUnit.lookups 2522 # Number of BP lookups
> system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted
> system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect
> system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups
> system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits
127,142c127,141
< system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target.
< system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions.
< system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps
< system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total)
---
> system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target.
> system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
> system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total)
144,152c143,151
< system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total)
156,172c155,171
< system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2624 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2398 # Number of cycles rename is running
---
> system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2573 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2368 # Number of cycles rename is running
174,183c173,182
< system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename
< system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
---
> system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename
> system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 45 # count of serializing insts renamed
185,199c184,198
< system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle
---
> system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle
201,209c200,208
< system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle
213c212
< system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle
215,245c214,244
< system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available
249,279c248,278
< system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued
282,288c281,287
< system.cpu.iq.FU_type_0::total 9165 # Type of FU issued
< system.cpu.iq.rate 0.444730 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 9186 # Type of FU issued
> system.cpu.iq.rate 0.445684 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 217 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses
290c289
< system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
---
> system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes
292c291
< system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses
294c293
< system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores
296c295
< system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed
299c298
< system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed
305,306c304,305
< system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking
308,312c307,311
< system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
---
> system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions
316,321c315,320
< system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute
323,331c322,330
< system.cpu.iew.exec_nop 1 # number of nop insts executed
< system.cpu.iew.exec_refs 3351 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1406 # Number of branches executed
< system.cpu.iew.exec_stores 1199 # Number of stores executed
< system.cpu.iew.exec_rate 0.420565 # Inst execution rate
< system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 8167 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 3874 # num instructions producing a value
< system.cpu.iew.wb_consumers 7832 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 0 # number of nop insts executed
> system.cpu.iew.exec_refs 3377 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1400 # Number of branches executed
> system.cpu.iew.exec_stores 1208 # Number of stores executed
> system.cpu.iew.exec_rate 0.423027 # Inst execution rate
> system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 8236 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 3901 # num instructions producing a value
> system.cpu.iew.wb_consumers 7899 # num instructions consuming a value
333,334c332,333
< system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back
336,338c335,337
< system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions
< system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions
< system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions
> system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions
> system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit
340,343c339,342
< system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle
345,353c344,352
< system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle
357,359c356,358
< system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 4600 # Number of instructions committed
< system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 4591 # Number of instructions committed
> system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
361,362c360,361
< system.cpu.commit.refs 2139 # Number of memory references committed
< system.cpu.commit.loads 1201 # Number of loads committed
---
> system.cpu.commit.refs 2138 # Number of memory references committed
> system.cpu.commit.loads 1200 # Number of loads committed
364c363
< system.cpu.commit.branches 945 # Number of branches committed
---
> system.cpu.commit.branches 944 # Number of branches committed
366c365
< system.cpu.commit.int_insts 4985 # Number of committed integer instructions.
---
> system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
368c367
< system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached
370,382c369,381
< system.cpu.rob.rob_reads 22629 # The number of ROB reads
< system.cpu.rob.rob_writes 24771 # The number of ROB writes
< system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.committedInsts 4600 # Number of Instructions Simulated
< system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 4600 # Number of Instructions Simulated
< system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 39716 # number of integer regfile reads
< system.cpu.int_regfile_writes 8038 # number of integer regfile writes
---
> system.cpu.rob.rob_reads 22509 # The number of ROB reads
> system.cpu.rob.rob_writes 24591 # The number of ROB writes
> system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.committedInsts 4591 # Number of Instructions Simulated
> system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
> system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 40006 # number of integer regfile reads
> system.cpu.int_regfile_writes 8113 # number of integer regfile writes
384c383
< system.cpu.misc_regfile_reads 16043 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 15846 # number of misc regfile reads
386,388c385,387
< system.cpu.icache.replacements 2 # number of replacements
< system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use
< system.cpu.icache.total_refs 1665 # Total number of references to valid blocks.
---
> system.cpu.icache.replacements 5 # number of replacements
> system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use
> system.cpu.icache.total_refs 1637 # Total number of references to valid blocks.
390c389
< system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks.
392,430c391,429
< system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits
< system.cpu.icache.overall_hits::total 1665 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
< system.cpu.icache.overall_misses::total 366 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency
---
> system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits
> system.cpu.icache.overall_hits::total 1637 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
> system.cpu.icache.overall_misses::total 359 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency
439,444c438,443
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits
451,468c450,467
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency
471,472c470,471
< system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use
< system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use
> system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks.
474c473
< system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks.
---
> system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks.
476,480c475,479
< system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits
---
> system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits
487,492c486,491
< system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits
< system.cpu.dcache.overall_hits::total 2405 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits
> system.cpu.dcache.overall_hits::total 2425 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses
497,504c496,503
< system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
< system.cpu.dcache.overall_misses::total 474 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses
> system.cpu.dcache.overall_misses::total 477 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles
507,512c506,511
< system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses)
519,524c518,523
< system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses
529,536c528,535
< system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency
539,542c538,541
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency
551,552c550,551
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
557,560c556,559
< system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits
569,578c568,577
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses
581,592c580,591
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency
595,598c594,597
< system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks.
600,603c599,602
< system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy
606,607c605,606
< system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits
609,610c608,609
< system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits
612,613c611,612
< system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
< system.cpu.l2cache.overall_hits::total 40 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits
> system.cpu.l2cache.overall_hits::total 42 # number of overall hits
615,616c614,615
< system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 361 # number of ReadReq misses
620,621c619,620
< system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses
623,635c622,634
< system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses
< system.cpu.l2cache.overall_misses::total 405 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
> system.cpu.l2cache.overall_misses::total 403 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9473000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2933000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles
648,649c647,648
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses
653,654c652,653
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses
656,668c655,667
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency
684,685c683,684
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses
689,690c688,689
< system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses
692,704c691,703
< system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles
706,707c705,706
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses
711,712c710,711
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses
714,726c713,725
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency