7,11c7,11
< host_inst_rate 20985 # Simulator instruction rate (inst/s)
< host_op_rate 26178 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 46991642 # Simulator tick rate (ticks/s)
< host_mem_usage 229632 # Number of bytes of host memory used
< host_seconds 0.22 # Real time elapsed on the host
---
> host_inst_rate 43907 # Simulator instruction rate (inst/s)
> host_op_rate 54769 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 98312554 # Simulator tick rate (ticks/s)
> host_mem_usage 230064 # Number of bytes of host memory used
> host_seconds 0.10 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 25664 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 401 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
> system.physmem.bytes_read::total 25664 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 401 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s)
412a420
> system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses
413a422
> system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses
414a424
> system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses
415a426
> system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency
416a428
> system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency
417a430
> system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency
444a458
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses
445a460
> system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses
446a462
> system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses
447a464
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency
448a466
> system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
449a468
> system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
504a524
> system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses
505a526
> system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses
506a528
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
507a530
> system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses
508a532
> system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses
509a534
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency
510a536
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency
511a538
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency
512a540
> system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency
513a542
> system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency
548a578
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses
549a580
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
550a582
> system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses
551a584
> system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses
552a586
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency
553a588
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency
554a590
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
555a592
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
611a649
> system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses
612a651
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
614a654
> system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses
616a657
> system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses
618a660
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency
619a662
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency
621a665
> system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency
623a668
> system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency
661a707
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses
662a709
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
664a712
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses
666a715
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses
668a718
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency
669a720
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency
671a723
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
673a726
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
< host_inst_rate 20985 # Simulator instruction rate (inst/s)
< host_op_rate 26178 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 46991642 # Simulator tick rate (ticks/s)
< host_mem_usage 229632 # Number of bytes of host memory used
< host_seconds 0.22 # Real time elapsed on the host
---
> host_inst_rate 43907 # Simulator instruction rate (inst/s)
> host_op_rate 54769 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 98312554 # Simulator tick rate (ticks/s)
> host_mem_usage 230064 # Number of bytes of host memory used
> host_seconds 0.10 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 25664 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 401 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
> system.physmem.bytes_read::total 25664 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 401 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s)
412a420
> system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses
413a422
> system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses
414a424
> system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses
415a426
> system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency
416a428
> system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency
417a430
> system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency
444a458
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses
445a460
> system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses
446a462
> system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses
447a464
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency
448a466
> system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
449a468
> system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
504a524
> system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses
505a526
> system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses
506a528
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
507a530
> system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses
508a532
> system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses
509a534
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency
510a536
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency
511a538
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency
512a540
> system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency
513a542
> system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency
548a578
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses
549a580
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
550a582
> system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses
551a584
> system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses
552a586
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency
553a588
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency
554a590
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
555a592
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
611a649
> system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses
612a651
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
614a654
> system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses
616a657
> system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses
618a660
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency
619a662
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency
621a665
> system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency
623a668
> system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency
661a707
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses
662a709
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
664a712
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses
666a715
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses
668a718
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency
669a720
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency
671a723
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
673a726
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency