3,5c3,5
< sim_seconds 0.000018 # Number of seconds simulated
< sim_ticks 18422500 # Number of ticks simulated
< final_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000019 # Number of seconds simulated
> sim_ticks 18517500 # Number of ticks simulated
> final_tick 18517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 76941 # Simulator instruction rate (inst/s)
< host_op_rate 90095 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 308579581 # Simulator tick rate (ticks/s)
< host_mem_usage 270584 # Number of bytes of host memory used
---
> host_inst_rate 74881 # Simulator instruction rate (inst/s)
> host_op_rate 87684 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 301872470 # Simulator tick rate (ticks/s)
> host_mem_usage 270416 # Number of bytes of host memory used
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
19,22c19,22
< system.physmem.bytes_read::total 25408 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25344 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
24,33c24,33
< system.physmem.num_reads::total 397 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 958827521 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 420355543 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1379183064 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 958827521 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 958827521 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 958827521 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 420355543 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1379183064 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 397 # Number of read requests accepted
---
> system.physmem.num_reads::total 396 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 950452275 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 418199001 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1368651276 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 950452275 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 950452275 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 950452275 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 418199001 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1368651276 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 396 # Number of read requests accepted
35c35
< system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue
37c37
< system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM
40c40
< system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side
54c54
< system.physmem.perBankRdBursts::9 9 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 8 # Per bank write bursts
79c79
< system.physmem.totGap 18337000 # Total gap between requests
---
> system.physmem.totGap 18432000 # Total gap between requests
86c86
< system.physmem.readPktSize::6 397 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 396 # Read request sizes (log2)
94c94
< system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 204 # What read queue length does an incoming req see
96,97c96,97
< system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
191,197c191,197
< system.physmem.bytesPerActivate::mean 407.864407 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 273.934367 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 344.219630 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 10 16.95% 16.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17 28.81% 45.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8 13.56% 59.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7 11.86% 71.19% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 406.779661 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 269.610222 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 346.645206 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% # Bytes accessed per row activation
199,202c199,202
< system.physmem.bytesPerActivate::640-767 2 3.39% 76.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 5.08% 81.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 3 5.08% 86.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8 13.56% 100.00% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation
204,207c204,207
< system.physmem.totQLat 5196750 # Total ticks spent queuing
< system.physmem.totMemAccLat 12640500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 13090.05 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 5212000 # Total ticks spent queuing
> system.physmem.totMemAccLat 12637000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 13161.62 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 31840.05 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1379.18 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 31911.62 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1368.65 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 1379.18 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1368.65 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 10.77 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.77 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.69 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.69 # Data bus utilization in percentage for reads
218c218
< system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.87 # Average read queue length when enqueuing
220c220
< system.physmem.readRowHits 330 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 329 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads
224,225c224,225
< system.physmem.avgGap 46188.92 # Average gap between requests
< system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 46545.45 # Average gap between requests
> system.physmem.pageHitRate 83.08 # Row buffer hit rate, read and write combined
231,234c231,234
< system.physmem_0.actBackEnergy 3077430 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 36000 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 5255970 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actBackEnergy 3085980 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 37920 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 5290170 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 19200 # Energy for precharge power-down per rank (pJ)
236,239c236,239
< system.physmem_0.totalEnergy 12170160 # Total energy per rank (pJ)
< system.physmem_0.averagePower 660.613923 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 11420000 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states
---
> system.physmem_0.totalEnergy 12213390 # Total energy per rank (pJ)
> system.physmem_0.averagePower 659.559336 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 11496500 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 29500 # Time in different power states
242,244c242,244
< system.physmem_0.memoryStateTime::PRE_PDN 53500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 6303750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 11521750 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 49250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 6316250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 11602500 # Time in different power states
247c247
< system.physmem_1.readEnergy 749700 # Energy for read commands per rank (pJ)
---
> system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ)
250,253c250,253
< system.physmem_1.actBackEnergy 1466040 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 65760 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 6124080 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 616800 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 1457490 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 66240 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 6092730 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 686400 # Energy for precharge power-down per rank (pJ)
255,257c255,257
< system.physmem_1.totalEnergy 10487985 # Total energy per rank (pJ)
< system.physmem_1.averagePower 569.303026 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 14986000 # Total Idle time Per DRAM Rank
---
> system.physmem_1.totalEnergy 10511025 # Total energy per rank (pJ)
> system.physmem_1.averagePower 567.626569 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 15098500 # Total Idle time Per DRAM Rank
261,269c261,269
< system.physmem_1.memoryStateTime::PRE_PDN 1605250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 2751250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 13430000 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 2844 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1749 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 2408 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 867 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::PRE_PDN 1787250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 2733750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 13360500 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 2820 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1728 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 468 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 2384 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 844 # Number of BTB hits
271,272c271,272
< system.cpu.branchPred.BTBHitPct 36.004983 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 35.402685 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 322 # Number of times the RAS was used to get a target.
274c274
< system.cpu.branchPred.indirectLookups 266 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.indirectLookups 260 # Number of indirect predictor lookups.
276,277c276,277
< system.cpu.branchPred.indirectMisses 253 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectMisses 247 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches.
279c279
< system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
309c309
< system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
339c339
< system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
369c369
< system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
400c400
< system.cpu.checker.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states
404c404
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
434c434
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
464c464
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
494c494
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
524,525c524,525
< system.cpu.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 36846 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 37036 # number of cpu cycles simulated
528,533c528,533
< system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 12314 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2844 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 1194 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 5108 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing
---
> system.cpu.fetch.icacheStallCycles 7733 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 12373 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2820 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 985 # Number of cycles fetch has spent squashing
537,541c537,541
< system.cpu.fetch.CacheLines 1962 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 13535 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.094422 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.458272 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 13616 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.093052 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.461769 # Number of instructions fetched each cycle (Total)
543,551c543,551
< system.cpu.fetch.rateDist::0 10839 80.08% 80.08% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 264 1.95% 82.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 185 1.37% 83.40% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 204 1.51% 84.91% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 283 2.09% 87.00% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 398 2.94% 89.94% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 139 1.03% 90.96% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 173 1.28% 92.24% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1050 7.76% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10916 80.17% 80.17% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 271 1.99% 82.16% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 182 1.34% 83.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 206 1.51% 85.01% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 259 1.90% 86.91% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 398 2.92% 89.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 138 1.01% 90.85% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 192 1.41% 92.26% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1054 7.74% 100.00% # Number of instructions fetched each cycle (Total)
555,563c555,563
< system.cpu.fetch.rateDist::total 13535 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.077186 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.334202 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 6279 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 4644 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2146 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch
---
> system.cpu.fetch.rateDist::total 13616 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.076142 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.334080 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 6341 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 4657 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2138 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 909 # Number of times decode resolved a branch
565c565
< system.cpu.decode.DecodedInsts 12150 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 12250 # Number of instructions handled by decode
567,569c567,569
< system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 6511 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 826 # Number of cycles rename is blocking
---
> system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 6573 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 835 # Number of cycles rename is blocking
571,573c571,573
< system.cpu.rename.RunCycles 2033 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1361 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename
---
> system.cpu.rename.RunCycles 2036 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1364 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 11552 # Number of instructions processed by rename
575c575
< system.cpu.rename.IQFullEvents 178 # Number of times rename has blocked due to IQ full
---
> system.cpu.rename.IQFullEvents 181 # Number of times rename has blocked due to IQ full
577,580c577,580
< system.cpu.rename.SQFullEvents 1169 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 11641 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 52345 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 12355 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 1170 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 11673 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 53030 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 12530 # Number of integer rename lookups
583c583
< system.cpu.rename.UndoneMaps 6147 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 6179 # Number of HB maps that are undone due to squashing
586,588c586,588
< system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2197 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1543 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 442 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit.
591c591
< system.cpu.iq.iqInstsAdded 10169 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 10296 # Number of instructions added to the IQ (excludes non-spec)
593,596c593,596
< system.cpu.iq.iqInstsIssued 8096 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 4835 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 12334 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 8207 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 4962 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 12830 # Number of squashed operands that are examined and possibly removed from graph
598,600c598,600
< system.cpu.iq.issued_per_cycle::samples 13535 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.598153 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.329974 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 13616 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.602747 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.340306 # Number of insts issued each cycle
602,609c602,609
< system.cpu.iq.issued_per_cycle::0 10320 76.25% 76.25% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1163 8.59% 84.84% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 763 5.64% 90.48% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 482 3.56% 94.04% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 344 2.54% 96.58% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 273 2.02% 98.60% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 120 0.89% 99.48% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 60 0.44% 99.93% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% # Number of insts issued each cycle
614c614
< system.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 13616 # Number of insts issued each cycle
616,650c616,650
< system.cpu.iq.fu_full::IntAlu 9 6.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 66 44.00% 50.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 62 41.33% 91.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 0 0.00% 91.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemWrite 13 8.67% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% # attempts to use FU when none available
654,688c654,688
< system.cpu.iq.FU_type_0::IntAlu 5023 62.04% 62.04% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1154 14.25% 99.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.59% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemWrite 33 0.41% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% # Type of FU issued
691,697c691,697
< system.cpu.iq.FU_type_0::total 8096 # Type of FU issued
< system.cpu.iq.rate 0.219725 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 150 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.018528 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 8207 # Type of FU issued
> system.cpu.iq.rate 0.221595 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 166 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.020227 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30145 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 15189 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 7438 # Number of integer instruction queue wakeup accesses
701c701
< system.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses
703c703
< system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores
705c705
< system.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1266 # Number of loads squashed
708c708
< system.cpu.iew.lsq.thread0.squashedStores 605 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed
711c711
< system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled
714,720c714,720
< system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 696 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 10222 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 2197 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1543 # Number of dispatched store instructions
---
> system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 707 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 10349 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions
722c722
< system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
---
> system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
725,730c725,730
< system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 356 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 7806 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1768 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 290 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedTakenIncorrect 93 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 267 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 7885 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1840 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute
733,743c733,743
< system.cpu.iew.exec_refs 2921 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1491 # Number of branches executed
< system.cpu.iew.exec_stores 1153 # Number of stores executed
< system.cpu.iew.exec_rate 0.211855 # Inst execution rate
< system.cpu.iew.wb_sent 7533 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 7436 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 3503 # num instructions producing a value
< system.cpu.iew.wb_consumers 6835 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.201813 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.512509 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4843 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 3007 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1490 # Number of branches executed
> system.cpu.iew.exec_stores 1167 # Number of stores executed
> system.cpu.iew.exec_rate 0.212901 # Inst execution rate
> system.cpu.iew.wb_sent 7581 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 7470 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 3518 # num instructions producing a value
> system.cpu.iew.wb_consumers 6872 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.201696 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.511932 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4970 # The number of squashed insts skipped by commit
745,748c745,748
< system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 12682 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.424066 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.266213 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 12743 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.422036 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.264076 # Number of insts commited each cycle
750,754c750,754
< system.cpu.commit.committed_per_cycle::0 10636 83.87% 83.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 879 6.93% 90.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 416 3.28% 94.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 218 1.72% 95.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 111 0.88% 96.67% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% # Number of insts commited each cycle
756c756
< system.cpu.commit.committed_per_cycle::6 54 0.43% 98.83% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% # Number of insts commited each cycle
762c762
< system.cpu.commit.committed_per_cycle::total 12682 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 12743 # Number of insts commited each cycle
813,816c813,816
< system.cpu.rob.rob_reads 22637 # The number of ROB reads
< system.cpu.rob.rob_writes 21308 # The number of ROB writes
< system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 23311 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 22825 # The number of ROB reads
> system.cpu.rob.rob_writes 21580 # The number of ROB writes
> system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 23420 # Total number of cycles that the CPU has spent unscheduled due to idling
819,824c819,824
< system.cpu.cpi 8.023955 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 8.023955 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.124627 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.124627 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 7656 # number of integer regfile reads
< system.cpu.int_regfile_writes 4268 # number of integer regfile writes
---
> system.cpu.cpi 8.065331 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 8.065331 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.123987 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.123987 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 7779 # number of integer regfile reads
> system.cpu.int_regfile_writes 4297 # number of integer regfile writes
826,828c826,828
< system.cpu.cc_regfile_reads 27780 # number of cc regfile reads
< system.cpu.cc_regfile_writes 3273 # number of cc regfile writes
< system.cpu.misc_regfile_reads 2974 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 28140 # number of cc regfile reads
> system.cpu.cc_regfile_writes 3276 # number of cc regfile writes
> system.cpu.misc_regfile_reads 3029 # number of misc regfile reads
830c830
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
832,833c832,833
< system.cpu.dcache.tags.tagsinuse 88.014551 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2093 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 87.889702 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2158 # Total number of references to valid blocks.
835c835
< system.cpu.dcache.tags.avg_refs 14.238095 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 14.680272 # Average number of references to valid blocks.
837,839c837,839
< system.cpu.dcache.tags.occ_blocks::cpu.data 88.014551 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021488 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021488 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 87.889702 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021457 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021457 # Average percentage of cache occupancy
844,848c844,848
< system.cpu.dcache.tags.tag_accesses 5335 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5335 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 5471 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5471 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 1540 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1540 # number of ReadReq hits
855,860c855,860
< system.cpu.dcache.demand_hits::cpu.data 2072 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2072 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2072 # number of overall hits
< system.cpu.dcache.overall_hits::total 2072 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits
> system.cpu.dcache.overall_hits::total 2137 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses
865,872c865,872
< system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses
< system.cpu.dcache.overall_misses::total 499 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11345000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11345000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 24463500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 24463500 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses
> system.cpu.dcache.overall_misses::total 502 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11381500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11381500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 24478000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 24478000 # number of WriteReq miss cycles
875,880c875,880
< system.cpu.dcache.demand_miss_latency::cpu.data 35808500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 35808500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 35808500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 35808500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1658 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1658 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 35859500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 35859500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 35859500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 35859500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1726 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1726 # number of ReadReq accesses(hits+misses)
887,892c887,892
< system.cpu.dcache.demand_accesses::cpu.data 2571 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2571 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2571 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2571 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110374 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.110374 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2639 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2639 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2639 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2639 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107764 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.107764 # miss rate for ReadReq accesses
897,904c897,904
< system.cpu.dcache.demand_miss_rate::cpu.data 0.194088 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.194088 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.194088 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.194088 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241 # average WriteReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.190224 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.190224 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.190224 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.190224 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61190.860215 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 61190.860215 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77462.025316 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 77462.025316 # average WriteReq miss latency
907,910c907,910
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 71760.521042 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 71760.521042 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 71433.266932 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 71433.266932 # average overall miss latency
917,918c917,918
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
923,926c923,926
< system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits
935,936c935,936
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7355500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7355500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7338000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7338000 # number of ReadReq MSHR miss cycles
939,944c939,944
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11023500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11023500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11023500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11023500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063329 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063329 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11006000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11006000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11006000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11006000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060834 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060834 # mshr miss rate for ReadReq accesses
947,952c947,952
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.057176 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.057176 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.055703 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.055703 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69885.714286 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69885.714286 # average ReadReq mshr miss latency
955,959c955,959
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
961,964c961,964
< system.cpu.icache.tags.tagsinuse 149.507349 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 148.671994 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1587 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 5.416382 # Average number of references to valid blocks.
966,970c966,970
< system.cpu.icache.tags.occ_blocks::cpu.inst 149.507349 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.073002 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.073002 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 148.671994 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.072594 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.072594 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id
972,1012c972,1012
< system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 4218 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4218 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits
< system.cpu.icache.overall_hits::total 1577 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses
< system.cpu.icache.overall_misses::total 385 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28997500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28997500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28997500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28997500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28997500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28997500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1962 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1962 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1962 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1962 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1962 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1962 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196228 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.196228 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.196228 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.196228 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.196228 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.196228 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75318.181818 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 75318.181818 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 75318.181818 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 75318.181818 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 493 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 4257 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4257 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1587 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1587 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1587 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1587 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1587 # number of overall hits
> system.cpu.icache.overall_hits::total 1587 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 395 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 395 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 395 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 395 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 395 # number of overall misses
> system.cpu.icache.overall_misses::total 395 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 29663500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 29663500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 29663500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 29663500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 29663500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 29663500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199294 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.199294 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.199294 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.199294 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.199294 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.199294 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75097.468354 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 75097.468354 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 75097.468354 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 75097.468354 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 422 # number of cycles access was blocked
1014c1014
< system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
1016c1016
< system.cpu.icache.avg_blocked_cycles::no_mshrs 98.600000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 105.500000 # average number of cycles each access was blocked
1020,1050c1020,1050
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23482000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23482000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23482000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23482000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23482000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23482000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149847 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.149847 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.149847 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79870.748299 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79870.748299 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 102 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 102 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 102 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 102 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23439000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23439000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23439000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23439000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23439000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23439000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147830 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.147830 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.147830 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79996.587031 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79996.587031 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
1052c1052
< system.cpu.l2cache.tags.tagsinuse 214.408451 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 213.492112 # Cycle average of tags in use
1054,1055c1054,1055
< system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.098485 # Average number of references to valid blocks.
1057,1063c1057,1063
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.281348 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 74.127103 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004281 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.002262 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.006543 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.462705 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 74.029407 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004256 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002259 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006515 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
1065,1068c1065,1068
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 3924 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 3924 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
1083,1084c1083,1084
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses
1087c1087
< system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses
1089,1090c1089,1090
< system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses
1092c1092
< system.cpu.l2cache.overall_misses::total 403 # number of overall misses
---
> system.cpu.l2cache.overall_misses::total 402 # number of overall misses
1095,1104c1095,1104
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22833000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22833000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6961000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 6961000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22833000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10564000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 33397000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22833000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10564000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 33397000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22791500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22791500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6943500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 6943500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22791500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10546500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 33338000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22791500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10546500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 33338000 # number of overall miss cycles
1109,1110c1109,1110
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses)
1113c1113
< system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses
1115,1116c1115,1116
< system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses
1118c1118
< system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses
1121,1122c1121,1122
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses
1125c1125
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses
1127,1128c1127,1128
< system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.913636 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses
1130c1130
< system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::total 0.913636 # miss rate for overall accesses
1133,1142c1133,1142
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82728.260870 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81894.117647 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81894.117647 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 82870.967742 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 82870.967742 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82878.181818 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82878.181818 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.235294 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.235294 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 82930.348259 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 82930.348259 # average overall miss latency
1157,1158c1157,1158
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses
1161c1161
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
1163,1164c1163,1164
< system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
1166c1166
< system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses
1169,1178c1169,1178
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20073000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20073000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5729500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5729500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20073000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 28985500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20073000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 28985500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 # number of overall MSHR miss cycles
1181,1182c1181,1182
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses
1185c1185
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses
1187,1188c1187,1188
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses
1190c1190
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses
1193,1203c1193,1203
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter.
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 442 # Total number of requests made to the snoop filter.
1209,1210c1209,1210
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
1214c1214
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution
1216c1216
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes)
1218,1219c1218,1219
< system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes)
1221c1221
< system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes)
1224,1226c1224,1226
< system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram
1228,1229c1228,1229
< system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram
1234,1235c1234,1235
< system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 223000 # Layer occupancy (ticks)
1237c1237
< system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks)
1241c1241
< system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter.
---
> system.membus.snoop_filter.tot_requests 396 # Total number of requests made to the snoop filter.
1247,1248c1247,1248
< system.membus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 355 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 354 # Transaction distribution
1251,1255c1251,1255
< system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes)
1258c1258
< system.membus.snoop_fanout::samples 397 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 396 # Request fanout histogram
1262c1262
< system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram
1267,1268c1267,1268
< system.membus.snoop_fanout::total 397 # Request fanout histogram
< system.membus.reqLayer0.occupancy 486500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 396 # Request fanout histogram
> system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
1270,1271c1270,1271
< system.membus.respLayer1.occupancy 2098750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 11.4 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 2091500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 11.3 # Layer utilization (%)