4,5c4,5
< sim_ticks 17232500 # Number of ticks simulated
< final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 17458500 # Number of ticks simulated
> final_tick 17458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 74373 # Simulator instruction rate (inst/s)
< host_op_rate 87086 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 279001739 # Simulator tick rate (ticks/s)
< host_mem_usage 265896 # Number of bytes of host memory used
< host_seconds 0.06 # Real time elapsed on the host
---
> host_inst_rate 52261 # Simulator instruction rate (inst/s)
> host_op_rate 61197 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 198636102 # Simulator tick rate (ticks/s)
> host_mem_usage 269760 # Number of bytes of host memory used
> host_seconds 0.09 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1011770771 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 443566171 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1455336942 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1011770771 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1011770771 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1011770771 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 443566171 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1455336942 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 17147000 # Total gap between requests
---
> system.physmem.totGap 17373000 # Total gap between requests
94,97c94,97
< system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
190,205c190,205
< system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
< system.physmem.totQLat 3287250 # Total ticks spent queuing
< system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 398.688525 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 264.215339 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 341.944807 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 12 19.67% 19.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 15 24.59% 44.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9 14.75% 59.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7 11.48% 70.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.92% 75.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 3.28% 78.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 3.28% 81.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2 3.28% 85.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9 14.75% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation
> system.physmem.totQLat 3455750 # Total ticks spent queuing
> system.physmem.totMemAccLat 10899500 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8704.66 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27454.66 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1455.34 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1455.34 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 11.52 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.37 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads
218c218
< system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing
220c220
< system.physmem.readRowHits 331 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 330 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 43191.44 # Average gap between requests
< system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 43760.71 # Average gap between requests
> system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ)
233,235c233,235
< system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ)
< system.physmem_0.averagePower 910.249171 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states
---
> system.physmem_0.totalEnergy 14349150 # Total energy per rank (pJ)
> system.physmem_0.averagePower 906.309806 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
238c238
< system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states
240,242c240,242
< system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ)
245,249c245,249
< system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ)
< system.physmem_1.averagePower 808.014211 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states
---
> system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 466500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 12753765 # Total energy per rank (pJ)
> system.physmem_1.averagePower 805.416167 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 734500 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 14593500 # Time in different power states
254,255c254,255
< system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 2837 # Number of BP lookups
---
> system.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 2836 # Number of BP lookups
258,259c258,259
< system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 865 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 2400 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 864 # Number of BTB hits
261c261
< system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 36.000000 # BTB Hit Percentage
269c269
< system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
299c299
< system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
329c329
< system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
359c359
< system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
390c390
< system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.checker.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states
394c394
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
424c424
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
454c454
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
484c484
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
514,515c514,515
< system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 34466 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 34918 # number of cpu cycles simulated
518,522c518,522
< system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.icacheStallCycles 7601 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 12293 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2836 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 1192 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 4902 # Number of cycles fetch has run and was not squashing or blocked
525c525
< system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.PendingTrapStallCycles 248 # Number of stall cycles due to pending traps
527,531c527,531
< system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 13257 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.116542 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.478893 # Number of instructions fetched each cycle (Total)
533,541c533,541
< system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10565 79.69% 79.69% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 264 1.99% 81.69% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 184 1.39% 83.07% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 203 1.53% 84.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 282 2.13% 86.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 396 2.99% 89.72% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 139 1.05% 90.77% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 173 1.30% 92.07% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1051 7.93% 100.00% # Number of instructions fetched each cycle (Total)
545,551c545,551
< system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2142 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
---
> system.cpu.fetch.rateDist::total 13257 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.081219 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.352053 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 6292 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 4354 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2143 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking
555c555
< system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 12137 # Number of instructions handled by decode
558,563c558,563
< system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2037 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 6521 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 773 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 2325 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2036 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1268 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 11426 # Number of instructions processed by rename
565,570c565,570
< system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 52321 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups
---
> system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 1090 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 11634 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 52309 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 12345 # Number of integer rename lookups
573c573
< system.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 6140 # Number of HB maps that are undone due to squashing
581c581
< system.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 10163 # Number of instructions added to the IQ (excludes non-spec)
583,586c583,586
< system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 12329 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 8100 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 4828 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 12342 # Number of squashed operands that are examined and possibly removed from graph
588,590c588,590
< system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 13257 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.610998 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.340069 # Number of insts issued each cycle
592,598c592,598
< system.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10033 75.68% 75.68% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1170 8.83% 84.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 770 5.81% 90.31% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 479 3.61% 93.93% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 341 2.57% 96.50% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 274 2.07% 98.57% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 121 0.91% 99.48% # Number of insts issued each cycle
604c604
< system.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 13257 # Number of insts issued each cycle
606,636c606,636
< system.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 9 6.16% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.16% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 65 44.52% 50.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 72 49.32% 100.00% # attempts to use FU when none available
640,670c640,670
< system.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 5026 62.05% 62.05% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.14% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1881 23.22% 85.40% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1183 14.60% 100.00% # Type of FU issued
673,679c673,679
< system.cpu.iq.FU_type_0::total 8103 # Type of FU issued
< system.cpu.iq.rate 0.235101 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 145 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 8100 # Type of FU issued
> system.cpu.iq.rate 0.231972 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 146 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.018025 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 29552 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 14921 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 7399 # Number of integer instruction queue wakeup accesses
683c683
< system.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8203 # Number of integer alu accesses
697c697
< system.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 684 # Number of cycles IEW is blocking
699,700c699,700
< system.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispatchedInsts 10215 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch
710,712c710,712
< system.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 7807 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1773 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 293 # Number of squashed instructions skipped in execute
715c715
< system.cpu.iew.exec_refs 2923 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 2920 # number of memory reference insts executed
717,725c717,725
< system.cpu.iew.exec_stores 1151 # Number of stores executed
< system.cpu.iew.exec_rate 0.226716 # Inst execution rate
< system.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 7439 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 3504 # num instructions producing a value
< system.cpu.iew.wb_consumers 6831 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.215836 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_stores 1147 # Number of stores executed
> system.cpu.iew.exec_rate 0.223581 # Inst execution rate
> system.cpu.iew.wb_sent 7528 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 7431 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 3502 # num instructions producing a value
> system.cpu.iew.wb_consumers 6830 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.212813 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.512738 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4836 # The number of squashed insts skipped by commit
728,730c728,730
< system.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.278209 # Number of insts commited each cycle
732,739c732,739
< system.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 10353 83.47% 83.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 884 7.13% 90.59% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 420 3.39% 93.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 217 1.75% 95.73% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 107 0.86% 96.59% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 220 1.77% 98.36% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 55 0.44% 98.81% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 39 0.31% 99.12% # Number of insts commited each cycle
744c744
< system.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle
791,792c791,792
< system.cpu.rob.rob_reads 22311 # The number of ROB reads
< system.cpu.rob.rob_writes 21303 # The number of ROB writes
---
> system.cpu.rob.rob_reads 22352 # The number of ROB reads
> system.cpu.rob.rob_writes 21294 # The number of ROB writes
794c794
< system.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 21661 # Total number of cycles that the CPU has spent unscheduled due to idling
797,802c797,802
< system.cpu.cpi 7.505662 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.133233 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 7659 # number of integer regfile reads
< system.cpu.int_regfile_writes 4270 # number of integer regfile writes
---
> system.cpu.cpi 7.604094 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.604094 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.131508 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.131508 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 7649 # number of integer regfile reads
> system.cpu.int_regfile_writes 4266 # number of integer regfile writes
804,806c804,806
< system.cpu.cc_regfile_reads 27801 # number of cc regfile reads
< system.cpu.cc_regfile_writes 3276 # number of cc regfile writes
< system.cpu.misc_regfile_reads 2980 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 27780 # number of cc regfile reads
> system.cpu.cc_regfile_writes 3273 # number of cc regfile writes
> system.cpu.misc_regfile_reads 2976 # number of misc regfile reads
808c808
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
810,811c810,811
< system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 88.222961 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2096 # Total number of references to valid blocks.
813c813
< system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 14.258503 # Average number of references to valid blocks.
815,817c815,817
< system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 88.222961 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021539 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021539 # Average percentage of cache occupancy
822,826c822,826
< system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 5341 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5341 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 1478 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1478 # number of ReadReq hits
833,836c833,836
< system.cpu.dcache.demand_hits::cpu.data 2074 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2074 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2074 # number of overall hits
< system.cpu.dcache.overall_hits::total 2074 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 2075 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2075 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2075 # number of overall hits
> system.cpu.dcache.overall_hits::total 2075 # number of overall hits
847,858c847,858
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 10736000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 10736000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 22555500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 22555500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 33291500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 33291500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 33291500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 33291500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1660 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1660 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10847000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10847000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 22859500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22859500 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 144000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 33706500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 33706500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 33706500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 33706500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1661 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1661 # number of ReadReq accesses(hits+misses)
865,870c865,870
< system.cpu.dcache.demand_accesses::cpu.data 2573 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2573 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2573 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2573 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110241 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.110241 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2574 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2574 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2574 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2574 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110175 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.110175 # miss rate for ReadReq accesses
875,889c875,889
< system.cpu.dcache.demand_miss_rate::cpu.data 0.193937 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.193937 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.193937 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.193937 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58666.666667 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 58666.666667 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71378.164557 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 71378.164557 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66716.432866 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.193862 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.193862 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.193862 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.193862 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59273.224044 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 59273.224044 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72340.189873 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 72340.189873 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 67548.096192 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67548.096192 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 147 # number of cycles access was blocked
893c893
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked
913,922c913,922
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7020000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7020000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10418000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10418000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10418000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10418000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063253 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063253 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7089000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7089000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3440000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3440000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10529000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10529000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10529000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10529000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063215 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063215 # mshr miss rate for ReadReq accesses
925,937c925,937
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.057132 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.057132 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.057110 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.057110 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67514.285714 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67514.285714 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81904.761905 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81904.761905 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
939,940c939,940
< system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 149.958367 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1576 # Total number of references to valid blocks.
942c942
< system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 5.360544 # Average number of references to valid blocks.
944,946c944,946
< system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 149.958367 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.073222 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.073222 # Average percentage of cache occupancy
948,949c948,949
< system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
951,959c951,959
< system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4216 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits
< system.cpu.icache.overall_hits::total 1577 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4214 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4214 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits
> system.cpu.icache.overall_hits::total 1576 # number of overall hits
966,990c966,990
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26669500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26669500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26669500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26669500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26669500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26669500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195818 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.195818 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.195818 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.195818 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.195818 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.195818 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69451.822917 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 69451.822917 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 69451.822917 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 27225000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 27225000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 27225000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 27225000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 27225000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 27225000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195918 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.195918 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.195918 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.195918 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.195918 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.195918 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70898.437500 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 70898.437500 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 70898.437500 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 70898.437500 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked
994c994
< system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 86.600000 # average number of cycles each access was blocked
1010,1028c1010,1028
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21733500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 21733500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21733500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 21733500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21733500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 21733500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149924 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.149924 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22193500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22193500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22193500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22193500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22193500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22193500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150000 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.150000 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.150000 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75488.095238 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75488.095238 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
1030c1030
< system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 215.001500 # Cycle average of tags in use
1032,1033c1032,1033
< system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks.
1035,1043c1035,1043
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.723037 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 74.278463 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004295 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002267 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006561 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id
1046c1046
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
1071,1082c1071,1082
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21084500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 21084500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6625500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 6625500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21084500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9958500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31043000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21084500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9958500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31043000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3375000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3375000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21544500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 21544500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6694500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 6694500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21544500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10069500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31614000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21544500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10069500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31614000 # number of overall miss cycles
1109,1120c1109,1120
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80357.142857 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80357.142857 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78059.782609 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78059.782609 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78758.823529 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78758.823529 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78446.650124 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78446.650124 # average overall miss latency
1145,1156c1145,1156
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2955000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2955000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18784500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18784500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5499000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5499000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18784500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8454000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 27238500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18784500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8454000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 27238500 # number of overall MSHR miss cycles
1169,1180c1169,1180
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70357.142857 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70357.142857 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68059.782609 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68059.782609 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69607.594937 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69607.594937 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency
1187c1187
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
1216c1216
< system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%)
1219c1219,1225
< system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states
1242,1243c1248,1249
< system.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.2 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 12.0 # Layer utilization (%)