3,5c3,5
< sim_seconds 0.000016 # Number of seconds simulated
< sim_ticks 16223000 # Number of ticks simulated
< final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000017 # Number of seconds simulated
> sim_ticks 17307500 # Number of ticks simulated
> final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 54860 # Simulator instruction rate (inst/s)
< host_op_rate 64243 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 193800024 # Simulator tick rate (ticks/s)
< host_mem_usage 308908 # Number of bytes of host memory used
---
> host_inst_rate 56147 # Simulator instruction rate (inst/s)
> host_op_rate 65749 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 211593476 # Simulator tick rate (ticks/s)
> host_mem_usage 308560 # Number of bytes of host memory used
16,17c16,17
< system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory
19,22c19,22
< system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
---
> system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory
24,31c24,31
< system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1020598007 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 447436083 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1468034089 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1020598007 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1020598007 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1020598007 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 447436083 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1468034089 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 16156000 # Total gap between requests
---
> system.physmem.totGap 17240500 # Total gap between requests
190,196c190,196
< system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 388.063492 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 254.022879 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 340.382701 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16 25.40% 46.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9 14.29% 60.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation
199c199,200
< system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 1.59% 84.13% # Bytes accessed per row activation
202,203c203,204
< system.physmem.totQLat 3126000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3336500 # Total ticks spent queuing
> system.physmem.totMemAccLat 10780250 # Total ticks spent from burst creation until serviced by the DRAM
205c206
< system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8404.28 # Average queueing delay per DRAM burst
207,208c208,209
< system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27154.28 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1468.03 # Average DRAM read bandwidth in MiByte/s
210c211
< system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1468.03 # Average system read bandwidth in MiByte/s
213,214c214,215
< system.physmem.busUtil 12.24 # Data bus utilization in percentage
< system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.47 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.47 # Data bus utilization in percentage for reads
216c217
< system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
218c219
< system.physmem.readRowHits 331 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 330 # Number of row buffer hits during reads
220c221
< system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads
222,226c223,227
< system.physmem.avgGap 40695.21 # Average gap between requests
< system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 43426.95 # Average gap between requests
> system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 2074800 # Energy for read commands per rank (pJ)
229,233c230,234
< system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ)
< system.physmem_0.averagePower 920.354334 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states
---
> system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 14395920 # Total energy per rank (pJ)
> system.physmem_0.averagePower 909.263856 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
236c237
< system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states
240c241
< system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ)
---
> system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ)
243,247c244,248
< system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ)
< system.physmem_1.averagePower 810.522027 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states
---
> system.physmem_1.actBackEnergy 10358325 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 414750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 12772695 # Total energy per rank (pJ)
> system.physmem_1.averagePower 806.611620 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 897000 # Time in different power states
250c251
< system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 14679500 # Time in different power states
252,253c253,254
< system.cpu.branchPred.lookups 2638 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 2634 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1633 # Number of conditional branches predicted
255,256c256,257
< system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 783 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 2098 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 781 # Number of BTB hits
258,259c259,260
< system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 37.225929 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 353 # Number of times the RAS was used to get a target.
498c499
< system.cpu.numCycles 32447 # number of cpu cycles simulated
---
> system.cpu.numCycles 34616 # number of cpu cycles simulated
501,506c502,507
< system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1011 # Number of cycles fetch has spent squashing
---
> system.cpu.fetch.icacheStallCycles 7775 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 12462 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2634 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 1134 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 4935 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1009 # Number of cycles fetch has spent squashing
508c509
< system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.PendingTrapStallCycles 273 # Number of stall cycles due to pending traps
510,514c511,515
< system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 2063 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 315 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 13520 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.090163 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.470015 # Number of instructions fetched each cycle (Total)
516,524c517,525
< system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10832 80.12% 80.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 265 1.96% 82.08% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 242 1.79% 83.87% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 236 1.75% 85.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 238 1.76% 87.37% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 290 2.14% 89.52% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 142 1.05% 90.57% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 172 1.27% 91.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1103 8.16% 100.00% # Number of instructions fetched each cycle (Total)
528,535c529,536
< system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2145 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing
---
> system.cpu.fetch.rateDist::total 13520 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.076092 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.360007 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 6427 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 4469 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2141 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 348 # Number of cycles decode is squashing
538c539
< system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 12076 # Number of instructions handled by decode
540,552c541,553
< system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2064 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename
< system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups
---
> system.cpu.rename.SquashCycles 348 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 6634 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 859 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 2379 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2057 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1243 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename
> system.cpu.rename.IQFullEvents 177 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 1054 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 11789 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 52593 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 12687 # Number of integer rename lookups
555c556
< system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 6295 # Number of HB maps that are undone due to squashing
558,560c559,561
< system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 434 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 2310 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1632 # Number of stores inserted to the mem dependence unit.
563c564
< system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 10336 # Number of instructions added to the IQ (excludes non-spec)
565c566
< system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 8345 # Number of instructions issued
567,568c568,569
< system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 4743 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 12819 # Number of squashed operands that are examined and possibly removed from graph
570,572c571,573
< system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 13520 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.617234 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.373407 # Number of insts issued each cycle
574,581c575,582
< system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10276 76.01% 76.01% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1181 8.74% 84.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 737 5.45% 90.19% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 452 3.34% 93.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 368 2.72% 96.26% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 283 2.09% 98.35% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 137 1.01% 99.36% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 63 0.47% 99.83% # Number of insts issued each cycle
586c587
< system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 13520 # Number of insts issued each cycle
622,646c623,647
< system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 5033 60.31% 60.31% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.38% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.38% # Type of FU issued
651,652c652,653
< system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 2011 24.10% 84.52% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1292 15.48% 100.00% # Type of FU issued
655,656c656,657
< system.cpu.iq.FU_type_0::total 8358 # Type of FU issued
< system.cpu.iq.rate 0.257589 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 8345 # Type of FU issued
> system.cpu.iq.rate 0.241073 # Inst issue rate
658,661c659,662
< system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.fu_busy_rate 0.020252 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30336 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 15016 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 7551 # Number of integer instruction queue wakeup accesses
664,665c665,666
< system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses
---
> system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 8471 # Number of integer alu accesses
669c670
< system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed
671,672c672,673
< system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 694 # Number of stores squashed
676c677
< system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
678,681c679,682
< system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 348 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 819 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 10393 # Number of instructions dispatched to IQ
683,684c684,685
< system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 2310 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1632 # Number of dispatched store instructions
686,688c687,689
< system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
---
> system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
690,694c691,695
< system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedNotTakenIncorrect 251 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 363 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 8047 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1910 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute
697,704c698,705
< system.cpu.iew.exec_refs 3148 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1457 # Number of branches executed
< system.cpu.iew.exec_stores 1240 # Number of stores executed
< system.cpu.iew.exec_rate 0.248498 # Inst execution rate
< system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 7601 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 3572 # num instructions producing a value
< system.cpu.iew.wb_consumers 6998 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 3142 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1452 # Number of branches executed
> system.cpu.iew.exec_stores 1232 # Number of stores executed
> system.cpu.iew.exec_rate 0.232465 # Inst execution rate
> system.cpu.iew.wb_sent 7714 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 7583 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 3567 # num instructions producing a value
> system.cpu.iew.wb_consumers 6985 # num instructions consuming a value
706,707c707,708
< system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.219061 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.510666 # average fanout of values written-back
709c710
< system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 5019 # The number of squashed insts skipped by commit
712,714c713,715
< system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 12644 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.425261 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.266647 # Number of insts commited each cycle
716,724c717,725
< system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 10588 83.74% 83.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 887 7.02% 90.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 425 3.36% 94.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 213 1.68% 95.80% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 117 0.93% 96.73% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 214 1.69% 98.42% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 50 0.40% 98.81% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 37 0.29% 99.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 113 0.89% 100.00% # Number of insts commited each cycle
728c729
< system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 12644 # Number of insts commited each cycle
774c775
< system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached
776,779c777,780
< system.cpu.rob.rob_reads 22692 # The number of ROB reads
< system.cpu.rob.rob_writes 21720 # The number of ROB writes
< system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 22770 # The number of ROB reads
> system.cpu.rob.rob_writes 21679 # The number of ROB writes
> system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 21096 # Total number of cycles that the CPU has spent unscheduled due to idling
782,791c783,792
< system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 7945 # number of integer regfile reads
< system.cpu.int_regfile_writes 4420 # number of integer regfile writes
< system.cpu.fp_regfile_reads 31 # number of floating regfile reads
< system.cpu.cc_regfile_reads 28734 # number of cc regfile reads
< system.cpu.cc_regfile_writes 3302 # number of cc regfile writes
< system.cpu.misc_regfile_reads 3189 # number of misc regfile reads
---
> system.cpu.cpi 7.539970 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.539970 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.132627 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.132627 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 7923 # number of integer regfile reads
> system.cpu.int_regfile_writes 4408 # number of integer regfile writes
> system.cpu.fp_regfile_reads 32 # number of floating regfile reads
> system.cpu.cc_regfile_reads 28677 # number of cc regfile reads
> system.cpu.cc_regfile_writes 3298 # number of cc regfile writes
> system.cpu.misc_regfile_reads 3185 # number of misc regfile reads
794,795c795,796
< system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 87.291293 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2178 # Total number of references to valid blocks.
797c798
< system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 14.917808 # Average number of references to valid blocks.
799,801c800,802
< system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 87.291293 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021311 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021311 # Average percentage of cache occupancy
803,804c804,805
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
806,811c807,812
< system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 5532 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5532 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1558 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1558 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits
816,823c817,824
< system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits
< system.cpu.dcache.overall_hits::total 2146 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits
> system.cpu.dcache.overall_hits::total 2156 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 198 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 198 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses
826,841c827,842
< system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses
< system.cpu.dcache.overall_misses::total 521 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses
> system.cpu.dcache.overall_misses::total 513 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12309993 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12309993 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 22746000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22746000 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 35055993 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 35055993 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 35055993 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 35055993 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1756 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1756 # number of ReadReq accesses(hits+misses)
848,855c849,856
< system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2669 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2669 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2669 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2669 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.112756 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.112756 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses
858,872c859,873
< system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.192207 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.192207 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.192207 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.192207 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62171.681818 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 62171.681818 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72209.523810 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 72209.523810 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 68335.269006 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 68335.269006 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked
874c875
< system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
876c877
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked
880,883c881,884
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 93 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits
886,889c887,890
< system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits
898,907c899,908
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6906505 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6906505 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10297005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10297005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10297005 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10297005 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059795 # mshr miss rate for ReadReq accesses
910,921c911,922
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.055077 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.055077 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65776.238095 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65776.238095 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency
924,925c925,926
< system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 149.998434 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1659 # Total number of references to valid blocks.
927c928
< system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 5.642857 # Average number of references to valid blocks.
929,931c930,932
< system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 149.998434 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.073241 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.073241 # Average percentage of cache occupancy
933,934c934,935
< system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
936,974c937,975
< system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4430 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits
< system.cpu.icache.overall_hits::total 1666 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses
< system.cpu.icache.overall_misses::total 402 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 4420 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4420 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1659 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1659 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1659 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1659 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1659 # number of overall hits
> system.cpu.icache.overall_hits::total 1659 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 404 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 404 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 404 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 404 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 404 # number of overall misses
> system.cpu.icache.overall_misses::total 404 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 28289500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 28289500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 28289500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 28289500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 28289500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 28289500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2063 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2063 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2063 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2063 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2063 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195831 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.195831 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.195831 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.195831 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.195831 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.195831 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70023.514851 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 70023.514851 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 70023.514851 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 70023.514851 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 361 # number of cycles access was blocked
978c979
< system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 72.200000 # average number of cycles each access was blocked
982,987c983,988
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 110 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 110 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 110 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 110 # number of overall MSHR hits
994,1011c995,1012
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21612000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 21612000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21612000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 21612000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21612000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 21612000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142511 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.142511 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.142511 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73510.204082 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73510.204082 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency
1014c1015
< system.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 186.994376 # Cycle average of tags in use
1019,1023c1020,1024
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.852442 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 46.141935 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001408 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005707 # Average percentage of cache occupancy
1025,1026c1026,1027
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
1030,1031c1031,1032
< system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits
1033,1034c1034,1035
< system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits
1036,1037c1037,1038
< system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits
1039,1040c1040,1041
< system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 84 # number of ReadReq misses
1044,1045c1045,1046
< system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses
1047,1048c1048,1049
< system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses
1050,1060c1051,1061
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21127500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6646750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 27774250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3346500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3346500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21127500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9993250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31120750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21127500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9993250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31120750 # number of overall miss cycles
1072,1073c1073,1074
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935374 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.800000 # miss rate for ReadReq accesses
1077,1078c1078,1079
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses
1080,1081c1081,1082
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses
1083,1093c1084,1094
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76548.913043 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79127.976190 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 77150.694444 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77414.800995 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77414.800995 # average overall miss latency
1108,1109c1109,1110
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 79 # number of ReadReq MSHR misses
1113,1114c1114,1115
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses
1116,1117c1117,1118
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses
1119,1131c1120,1132
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17683000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5328000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17683000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8152000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 25835000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17683000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8152000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 25835000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadReq accesses
1135,1136c1136,1137
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses
1138,1139c1139,1140
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses
1141,1151c1142,1152
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64068.840580 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67443.037975 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64819.718310 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67238.095238 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67238.095238 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency
1165c1166
< system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
1173,1178c1174,1175
< system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::5 441 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
1180,1181c1177,1178
< system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
1184,1187c1181,1184
< system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 495000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 238495 # Layer occupancy (ticks)
1208,1211c1205,1208
< system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 22.8 # Layer utilization (%)
---
> system.membus.reqLayer0.occupancy 499500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 12.1 # Layer utilization (%)