7,11c7,11
< host_inst_rate 32617 # Simulator instruction rate (inst/s)
< host_op_rate 38195 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 115221437 # Simulator tick rate (ticks/s)
< host_mem_usage 253076 # Number of bytes of host memory used
< host_seconds 0.14 # Real time elapsed on the host
---
> host_inst_rate 55920 # Simulator instruction rate (inst/s)
> host_op_rate 65484 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 197542740 # Simulator tick rate (ticks/s)
> host_mem_usage 304472 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
93,94c93,94
< system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
202,203c202,203
< system.physmem.totQLat 2970000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3126000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM
205c205
< system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst
207c207
< system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst
229d228
< system.membus.throughput 1566171485 # Throughput (bytes/s)
236,239c235,247
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 25408 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 397 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 397 # Request fanout histogram
721d728
< system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s)
729,733c736,758
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
741c766
< system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use
746,748c771,773
< system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy
767,772c792,797
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles
785,790c810,815
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency
811,816c836,841
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles
823,828c848,853
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency
831c856
< system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use
836,838c861,863
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy
840c865
< system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy
867,868c892,893
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19251250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6010750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles
872,873c897,898
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19251250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9112500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles
875,876c900,901
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19251250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9112500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles
900,901c925,926
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency
905,906c930,931
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency
908,909c933,934
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency
936,937c961,962
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles
941,942c966,967
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles
944,945c969,970
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles
958,959c983,984
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency
963,964c988,989
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency
966,967c991,992
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency
971c996
< system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use
976,978c1001,1003
< system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy
1007,1008c1032,1033
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles
1013,1016c1038,1041
< system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles
1039,1040c1064,1065
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency
1045,1048c1070,1073
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency
1075,1076c1100,1101
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles
1079,1082c1104,1107
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles
1091,1092c1116,1117
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency
1095,1098c1120,1123
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency
< host_inst_rate 32617 # Simulator instruction rate (inst/s)
< host_op_rate 38195 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 115221437 # Simulator tick rate (ticks/s)
< host_mem_usage 253076 # Number of bytes of host memory used
< host_seconds 0.14 # Real time elapsed on the host
---
> host_inst_rate 55920 # Simulator instruction rate (inst/s)
> host_op_rate 65484 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 197542740 # Simulator tick rate (ticks/s)
> host_mem_usage 304472 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
93,94c93,94
< system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
202,203c202,203
< system.physmem.totQLat 2970000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3126000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM
205c205
< system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst
207c207
< system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst
229d228
< system.membus.throughput 1566171485 # Throughput (bytes/s)
236,239c235,247
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 25408 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 397 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 397 # Request fanout histogram
721d728
< system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s)
729,733c736,758
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
741c766
< system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use
746,748c771,773
< system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy
767,772c792,797
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles
785,790c810,815
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency
811,816c836,841
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles
823,828c848,853
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency
831c856
< system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use
836,838c861,863
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy
840c865
< system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy
867,868c892,893
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19251250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6010750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles
872,873c897,898
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19251250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9112500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles
875,876c900,901
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19251250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9112500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles
900,901c925,926
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency
905,906c930,931
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency
908,909c933,934
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency
936,937c961,962
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles
941,942c966,967
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles
944,945c969,970
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles
958,959c983,984
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency
963,964c988,989
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency
966,967c991,992
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency
971c996
< system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use
976,978c1001,1003
< system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy
1007,1008c1032,1033
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles
1013,1016c1038,1041
< system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles
1039,1040c1064,1065
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency
1045,1048c1070,1073
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency
1075,1076c1100,1101
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles
1079,1082c1104,1107
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles
1091,1092c1116,1117
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency
1095,1098c1120,1123
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency