Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt

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stats.txt (9838:43d22d746e7a)	stats.txt (9924:31ef410b6843)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16494000 # Number of ticks simulated 5final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16494000 # Number of ticks simulated 5final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 32065 # Simulator instruction rate (inst/s) 8host_op_rate 40006 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 115159682 # Simulator tick rate (ticks/s) 10host_mem_usage 240696 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host	7host_inst_rate 19652 # Simulator instruction rate (inst/s) 8host_op_rate 24522 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 70593484 # Simulator tick rate (ticks/s) 10host_mem_usage 246136 # Number of bytes of host memory used 11host_seconds 0.23 # Real time elapsed on the host
12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25152 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 393 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 34system.physmem.bytesRead 25152 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 39system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis 56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 74system.physmem.totGap 16436500 # Total gap between requests 75system.physmem.readPktSize::0 0 # Categorize read packet sizes 76system.physmem.readPktSize::1 0 # Categorize read packet sizes 77system.physmem.readPktSize::2 0 # Categorize read packet sizes 78system.physmem.readPktSize::3 0 # Categorize read packet sizes 79system.physmem.readPktSize::4 0 # Categorize read packet sizes 80system.physmem.readPktSize::5 0 # Categorize read packet sizes 81system.physmem.readPktSize::6 393 # Categorize read packet sizes 82system.physmem.writePktSize::0 0 # Categorize write packet sizes 83system.physmem.writePktSize::1 0 # Categorize write packet sizes 84system.physmem.writePktSize::2 0 # Categorize write packet sizes 85system.physmem.writePktSize::3 0 # Categorize write packet sizes 86system.physmem.writePktSize::4 0 # Categorize write packet sizes 87system.physmem.writePktSize::5 0 # Categorize write packet sizes 88system.physmem.writePktSize::6 0 # Categorize write packet sizes 89system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 121system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 153system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation 172system.physmem.totQLat 2047500 # Total cycles spent in queuing delays 173system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests 174system.physmem.totBusLat 1965000 # Total cycles spent in databus access 175system.physmem.totBankLat 5445000 # Total cycles spent in bank access 176system.physmem.avgQLat 5209.92 # Average queueing delay per request 177system.physmem.avgBankLat 13854.96 # Average bank access latency per request 178system.physmem.avgBusLat 5000.00 # Average bus latency per request 179system.physmem.avgMemAccLat 24064.89 # Average memory access latency 180system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s 181system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 182system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s 183system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 184system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 185system.physmem.busUtil 11.91 # Data bus utilization in percentage 186system.physmem.avgRdQLen 0.57 # Average read queue length over time 187system.physmem.avgWrQLen 0.00 # Average write queue length over time 188system.physmem.readRowHits 348 # Number of row buffer hits during reads 189system.physmem.writeRowHits 0 # Number of row buffer hits during writes 190system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads 191system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 192system.physmem.avgGap 41823.16 # Average gap between requests 193system.membus.throughput 1524918152 # Throughput (bytes/s) 194system.membus.trans_dist::ReadReq 352 # Transaction distribution 195system.membus.trans_dist::ReadResp 352 # Transaction distribution 196system.membus.trans_dist::ReadExReq 41 # Transaction distribution 197system.membus.trans_dist::ReadExResp 41 # Transaction distribution 198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) 199system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) 200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) 201system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) 202system.membus.data_through_bus 25152 # Total data (bytes) 203system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 204system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) 205system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 206system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) 207system.membus.respLayer1.utilization 22.3 # Layer utilization (%) 208system.cpu.branchPred.lookups 2479 # Number of BP lookups 209system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted 210system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 211system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups 212system.cpu.branchPred.BTBHits 697 # Number of BTB hits 213system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 214system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage 215system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 216system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 217system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 218system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 219system.cpu.checker.dtb.read_hits 0 # DTB read hits 220system.cpu.checker.dtb.read_misses 0 # DTB read misses 221system.cpu.checker.dtb.write_hits 0 # DTB write hits 222system.cpu.checker.dtb.write_misses 0 # DTB write misses 223system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 224system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 225system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 226system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 227system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 228system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 229system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 230system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 231system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 232system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 233system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 234system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 235system.cpu.checker.dtb.hits 0 # DTB hits 236system.cpu.checker.dtb.misses 0 # DTB misses 237system.cpu.checker.dtb.accesses 0 # DTB accesses 238system.cpu.checker.itb.inst_hits 0 # ITB inst hits 239system.cpu.checker.itb.inst_misses 0 # ITB inst misses 240system.cpu.checker.itb.read_hits 0 # DTB read hits 241system.cpu.checker.itb.read_misses 0 # DTB read misses 242system.cpu.checker.itb.write_hits 0 # DTB write hits 243system.cpu.checker.itb.write_misses 0 # DTB write misses 244system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 245system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 246system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 247system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 248system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 249system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 250system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 251system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 252system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 253system.cpu.checker.itb.read_accesses 0 # DTB read accesses 254system.cpu.checker.itb.write_accesses 0 # DTB write accesses 255system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 256system.cpu.checker.itb.hits 0 # DTB hits 257system.cpu.checker.itb.misses 0 # DTB misses 258system.cpu.checker.itb.accesses 0 # DTB accesses 259system.cpu.workload.num_syscalls 13 # Number of system calls 260system.cpu.checker.numCycles 5742 # number of cpu cycles simulated 261system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 262system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 263system.cpu.dtb.inst_hits 0 # ITB inst hits 264system.cpu.dtb.inst_misses 0 # ITB inst misses 265system.cpu.dtb.read_hits 0 # DTB read hits 266system.cpu.dtb.read_misses 0 # DTB read misses 267system.cpu.dtb.write_hits 0 # DTB write hits 268system.cpu.dtb.write_misses 0 # DTB write misses 269system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 270system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 271system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 272system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 273system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 274system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 275system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 276system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 277system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 278system.cpu.dtb.read_accesses 0 # DTB read accesses 279system.cpu.dtb.write_accesses 0 # DTB write accesses 280system.cpu.dtb.inst_accesses 0 # ITB inst accesses 281system.cpu.dtb.hits 0 # DTB hits 282system.cpu.dtb.misses 0 # DTB misses 283system.cpu.dtb.accesses 0 # DTB accesses 284system.cpu.itb.inst_hits 0 # ITB inst hits 285system.cpu.itb.inst_misses 0 # ITB inst misses 286system.cpu.itb.read_hits 0 # DTB read hits 287system.cpu.itb.read_misses 0 # DTB read misses 288system.cpu.itb.write_hits 0 # DTB write hits 289system.cpu.itb.write_misses 0 # DTB write misses 290system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 291system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 292system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 293system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 294system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 295system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 296system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 297system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 298system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 299system.cpu.itb.read_accesses 0 # DTB read accesses 300system.cpu.itb.write_accesses 0 # DTB write accesses 301system.cpu.itb.inst_accesses 0 # ITB inst accesses 302system.cpu.itb.hits 0 # DTB hits 303system.cpu.itb.misses 0 # DTB misses 304system.cpu.itb.accesses 0 # DTB accesses 305system.cpu.numCycles 32989 # number of cpu cycles simulated 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 308system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 314system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked 315system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 316system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed 317system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle 335system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle 336system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle 337system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked 338system.cpu.decode.RunCycles 2420 # Number of cycles decode is running 339system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking 340system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 341system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 342system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 343system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode 344system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 345system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 346system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle 347system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking 348system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst 349system.cpu.rename.RunCycles 2221 # Number of cycles rename is running 350system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking 351system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename 352system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 353system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full 354system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full 355system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed 356system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made	12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25152 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 393 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 34system.physmem.bytesRead 25152 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 39system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis 56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 74system.physmem.totGap 16436500 # Total gap between requests 75system.physmem.readPktSize::0 0 # Categorize read packet sizes 76system.physmem.readPktSize::1 0 # Categorize read packet sizes 77system.physmem.readPktSize::2 0 # Categorize read packet sizes 78system.physmem.readPktSize::3 0 # Categorize read packet sizes 79system.physmem.readPktSize::4 0 # Categorize read packet sizes 80system.physmem.readPktSize::5 0 # Categorize read packet sizes 81system.physmem.readPktSize::6 393 # Categorize read packet sizes 82system.physmem.writePktSize::0 0 # Categorize write packet sizes 83system.physmem.writePktSize::1 0 # Categorize write packet sizes 84system.physmem.writePktSize::2 0 # Categorize write packet sizes 85system.physmem.writePktSize::3 0 # Categorize write packet sizes 86system.physmem.writePktSize::4 0 # Categorize write packet sizes 87system.physmem.writePktSize::5 0 # Categorize write packet sizes 88system.physmem.writePktSize::6 0 # Categorize write packet sizes 89system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 121system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 153system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation 172system.physmem.totQLat 2047500 # Total cycles spent in queuing delays 173system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests 174system.physmem.totBusLat 1965000 # Total cycles spent in databus access 175system.physmem.totBankLat 5445000 # Total cycles spent in bank access 176system.physmem.avgQLat 5209.92 # Average queueing delay per request 177system.physmem.avgBankLat 13854.96 # Average bank access latency per request 178system.physmem.avgBusLat 5000.00 # Average bus latency per request 179system.physmem.avgMemAccLat 24064.89 # Average memory access latency 180system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s 181system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 182system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s 183system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 184system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 185system.physmem.busUtil 11.91 # Data bus utilization in percentage 186system.physmem.avgRdQLen 0.57 # Average read queue length over time 187system.physmem.avgWrQLen 0.00 # Average write queue length over time 188system.physmem.readRowHits 348 # Number of row buffer hits during reads 189system.physmem.writeRowHits 0 # Number of row buffer hits during writes 190system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads 191system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 192system.physmem.avgGap 41823.16 # Average gap between requests 193system.membus.throughput 1524918152 # Throughput (bytes/s) 194system.membus.trans_dist::ReadReq 352 # Transaction distribution 195system.membus.trans_dist::ReadResp 352 # Transaction distribution 196system.membus.trans_dist::ReadExReq 41 # Transaction distribution 197system.membus.trans_dist::ReadExResp 41 # Transaction distribution 198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) 199system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) 200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) 201system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) 202system.membus.data_through_bus 25152 # Total data (bytes) 203system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 204system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) 205system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 206system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) 207system.membus.respLayer1.utilization 22.3 # Layer utilization (%) 208system.cpu.branchPred.lookups 2479 # Number of BP lookups 209system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted 210system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 211system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups 212system.cpu.branchPred.BTBHits 697 # Number of BTB hits 213system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 214system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage 215system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 216system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 217system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 218system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 219system.cpu.checker.dtb.read_hits 0 # DTB read hits 220system.cpu.checker.dtb.read_misses 0 # DTB read misses 221system.cpu.checker.dtb.write_hits 0 # DTB write hits 222system.cpu.checker.dtb.write_misses 0 # DTB write misses 223system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 224system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 225system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 226system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 227system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 228system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 229system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 230system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 231system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 232system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 233system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 234system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 235system.cpu.checker.dtb.hits 0 # DTB hits 236system.cpu.checker.dtb.misses 0 # DTB misses 237system.cpu.checker.dtb.accesses 0 # DTB accesses 238system.cpu.checker.itb.inst_hits 0 # ITB inst hits 239system.cpu.checker.itb.inst_misses 0 # ITB inst misses 240system.cpu.checker.itb.read_hits 0 # DTB read hits 241system.cpu.checker.itb.read_misses 0 # DTB read misses 242system.cpu.checker.itb.write_hits 0 # DTB write hits 243system.cpu.checker.itb.write_misses 0 # DTB write misses 244system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 245system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 246system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 247system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 248system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 249system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 250system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 251system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 252system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 253system.cpu.checker.itb.read_accesses 0 # DTB read accesses 254system.cpu.checker.itb.write_accesses 0 # DTB write accesses 255system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 256system.cpu.checker.itb.hits 0 # DTB hits 257system.cpu.checker.itb.misses 0 # DTB misses 258system.cpu.checker.itb.accesses 0 # DTB accesses 259system.cpu.workload.num_syscalls 13 # Number of system calls 260system.cpu.checker.numCycles 5742 # number of cpu cycles simulated 261system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 262system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 263system.cpu.dtb.inst_hits 0 # ITB inst hits 264system.cpu.dtb.inst_misses 0 # ITB inst misses 265system.cpu.dtb.read_hits 0 # DTB read hits 266system.cpu.dtb.read_misses 0 # DTB read misses 267system.cpu.dtb.write_hits 0 # DTB write hits 268system.cpu.dtb.write_misses 0 # DTB write misses 269system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 270system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 271system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 272system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 273system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 274system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 275system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 276system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 277system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 278system.cpu.dtb.read_accesses 0 # DTB read accesses 279system.cpu.dtb.write_accesses 0 # DTB write accesses 280system.cpu.dtb.inst_accesses 0 # ITB inst accesses 281system.cpu.dtb.hits 0 # DTB hits 282system.cpu.dtb.misses 0 # DTB misses 283system.cpu.dtb.accesses 0 # DTB accesses 284system.cpu.itb.inst_hits 0 # ITB inst hits 285system.cpu.itb.inst_misses 0 # ITB inst misses 286system.cpu.itb.read_hits 0 # DTB read hits 287system.cpu.itb.read_misses 0 # DTB read misses 288system.cpu.itb.write_hits 0 # DTB write hits 289system.cpu.itb.write_misses 0 # DTB write misses 290system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 291system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 292system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 293system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 294system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 295system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 296system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 297system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 298system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 299system.cpu.itb.read_accesses 0 # DTB read accesses 300system.cpu.itb.write_accesses 0 # DTB write accesses 301system.cpu.itb.inst_accesses 0 # ITB inst accesses 302system.cpu.itb.hits 0 # DTB hits 303system.cpu.itb.misses 0 # DTB misses 304system.cpu.itb.accesses 0 # DTB accesses 305system.cpu.numCycles 32989 # number of cpu cycles simulated 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 308system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 314system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked 315system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 316system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed 317system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle 335system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle 336system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle 337system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked 338system.cpu.decode.RunCycles 2420 # Number of cycles decode is running 339system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking 340system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 341system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 342system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 343system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode 344system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 345system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 346system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle 347system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking 348system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst 349system.cpu.rename.RunCycles 2221 # Number of cycles rename is running 350system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking 351system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename 352system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 353system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full 354system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full 355system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed 356system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made
357system.cpu.rename.int_rename_lookups 56202 # Number of integer rename lookups 358system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups	357system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups 358system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups
359system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 360system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing 361system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 362system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 363system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer 364system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. 365system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. 366system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 367system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 368system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) 369system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 370system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued 371system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued 372system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling 373system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph 374system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 375system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle 392system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 393system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available 394system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available 395system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available 422system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available 423system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available 424system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 425system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 427system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued 428system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued 429system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued 456system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued 457system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued 458system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 459system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type_0::total 8917 # Type of FU issued 461system.cpu.iq.rate 0.270302 # Inst issue rate 462system.cpu.iq.fu_busy_cnt 222 # FU busy when requested 463system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) 464system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads 465system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes 466system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses 467system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 468system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 469system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 470system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses 471system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 472system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 473system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 474system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed 475system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 476system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 477system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed 478system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 479system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 480system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 481system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 482system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 483system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 484system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 485system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking 486system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ 487system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch 488system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions 489system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions 490system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 491system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall 492system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 493system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 494system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 495system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 496system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 497system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions 498system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed 499system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute 500system.cpu.iew.exec_swp 0 # number of swp insts executed 501system.cpu.iew.exec_nop 0 # number of nop insts executed 502system.cpu.iew.exec_refs 3296 # number of memory reference insts executed 503system.cpu.iew.exec_branches 1437 # Number of branches executed 504system.cpu.iew.exec_stores 1160 # Number of stores executed 505system.cpu.iew.exec_rate 0.258268 # Inst execution rate 506system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit 507system.cpu.iew.wb_count 8067 # cumulative count of insts written-back 508system.cpu.iew.wb_producers 3881 # num instructions producing a value 509system.cpu.iew.wb_consumers 7779 # num instructions consuming a value 510system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 511system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle 512system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back 513system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 514system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit 515system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 516system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 517system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle 534system.cpu.commit.committedInsts 4591 # Number of instructions committed 535system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 536system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 537system.cpu.commit.refs 2138 # Number of memory references committed 538system.cpu.commit.loads 1200 # Number of loads committed 539system.cpu.commit.membars 12 # Number of memory barriers committed 540system.cpu.commit.branches 1007 # Number of branches committed 541system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 542system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 543system.cpu.commit.function_calls 82 # Number of function calls committed. 544system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached 545system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 546system.cpu.rob.rob_reads 23271 # The number of ROB reads 547system.cpu.rob.rob_writes 23399 # The number of ROB writes 548system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself 549system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling 550system.cpu.committedInsts 4591 # Number of Instructions Simulated 551system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 552system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 553system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction 554system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads 555system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle 556system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads 557system.cpu.int_regfile_reads 39193 # number of integer regfile reads 558system.cpu.int_regfile_writes 7983 # number of integer regfile writes 559system.cpu.fp_regfile_reads 16 # number of floating regfile reads 560system.cpu.misc_regfile_reads 2975 # number of misc regfile reads 561system.cpu.misc_regfile_writes 24 # number of misc regfile writes 562system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) 563system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution 564system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution 565system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 567system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) 568system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 569system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) 570system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) 571system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 572system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) 573system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) 574system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 575system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) 576system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 577system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) 578system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) 579system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) 580system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 581system.cpu.icache.tags.replacements 4 # number of replacements 582system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use 583system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. 584system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. 585system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. 586system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 587system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor 588system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy 589system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy 590system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits 591system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits 592system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits 593system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits 594system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits 595system.cpu.icache.overall_hits::total 1583 # number of overall hits 596system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 597system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 598system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 599system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 600system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 601system.cpu.icache.overall_misses::total 364 # number of overall misses 602system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles 603system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles 604system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles 605system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles 606system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles 607system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles 608system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 609system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 610system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 611system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 612system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 613system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses 615system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses 616system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses 617system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses 618system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses 619system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses 620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency 621system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency 622system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency 623system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency 625system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency 626system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked 627system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 628system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 629system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 630system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked 631system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu.icache.fast_writes 0 # number of fast writes performed 633system.cpu.icache.cache_copies 0 # number of cache copies performed 634system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 635system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 636system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 637system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 638system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 639system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 640system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses 641system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses 642system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses 643system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses 644system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses 645system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses 646system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles 647system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles 648system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles 649system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles 650system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles 651system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles 652system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses 653system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses 654system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses 655system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses 656system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses 657system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses 658system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency 660system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency 662system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency 664system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 665system.cpu.l2cache.tags.replacements 0 # number of replacements 666system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use 667system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 668system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. 669system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. 670system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 671system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor 672system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor 673system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy 674system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy 675system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy 676system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 677system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 678system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 679system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 680system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 681system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 682system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 683system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 684system.cpu.l2cache.overall_hits::total 40 # number of overall hits 685system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses 686system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 687system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses 688system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 689system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 690system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses 691system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 692system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses 693system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses 694system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 695system.cpu.l2cache.overall_misses::total 398 # number of overall misses 696system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles 697system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles 698system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles 701system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles 704system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles 707system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) 708system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 709system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) 710system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 711system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 712system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses 713system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 714system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses 715system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses 716system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 717system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses 718system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses 721system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 722system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 723system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses 724system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 725system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses 726system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses 727system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 728system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses 729system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency 730system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency 731system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency 732system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency 733system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency 734system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency 735system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency 736system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency 737system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency 738system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency 740system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 741system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 742system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 744system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 745system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 746system.cpu.l2cache.fast_writes 0 # number of fast writes performed 747system.cpu.l2cache.cache_copies 0 # number of cache copies performed 748system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 749system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 750system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 751system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 752system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 753system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 754system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses 755system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 756system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses 757system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 758system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 759system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses 760system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 761system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses 762system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses 763system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 764system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses 765system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles 766system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles 767system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles 768system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles 769system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles 770system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles 771system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles 772system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles 773system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles 774system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles 775system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles 776system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses 777system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 778system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses 779system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 780system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 781system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses 782system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 783system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses 784system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses 785system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 786system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses 787system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency 788system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency 789system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency 790system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency 791system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency 792system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency 793system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency 794system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency 795system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency 796system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency 797system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency 798system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 799system.cpu.dcache.tags.replacements 0 # number of replacements 800system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use 801system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. 802system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 803system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. 804system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 805system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor 806system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy 807system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy 808system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits 809system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits 810system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 811system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 812system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 813system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 814system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 815system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 816system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits 817system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits 818system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits 819system.cpu.dcache.overall_hits::total 2369 # number of overall hits 820system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses 821system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses 822system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 823system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 824system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 825system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 826system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses 827system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses 828system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses 829system.cpu.dcache.overall_misses::total 497 # number of overall misses 830system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles 831system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles 832system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles 833system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles 834system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 835system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 836system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles 837system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles 838system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles 839system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles 840system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) 841system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) 842system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 843system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 844system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 845system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 846system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 847system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 848system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses 849system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses 850system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses 851system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses 852system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 856system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 857system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 858system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses 859system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses 860system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses 861system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses 862system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency 863system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency 865system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency 866system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 867system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 874system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed 880system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits 881system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits 882system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 883system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 884system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 885system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses 907system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses 908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 909system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses 911system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses 912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses 913system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses 914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency 915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency 916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency 917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency 918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency 919system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency 920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency 921system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency 922system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 923 924---------- End Simulation Statistics ----------	359system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 360system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing 361system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 362system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 363system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer 364system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. 365system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. 366system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 367system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 368system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) 369system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 370system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued 371system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued 372system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling 373system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph 374system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 375system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle 392system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 393system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available 394system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available 395system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available 422system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available 423system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available 424system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 425system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 427system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued 428system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued 429system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued 456system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued 457system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued 458system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 459system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type_0::total 8917 # Type of FU issued 461system.cpu.iq.rate 0.270302 # Inst issue rate 462system.cpu.iq.fu_busy_cnt 222 # FU busy when requested 463system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) 464system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads 465system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes 466system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses 467system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 468system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 469system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 470system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses 471system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 472system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 473system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 474system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed 475system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 476system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 477system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed 478system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 479system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 480system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 481system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 482system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 483system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 484system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 485system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking 486system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ 487system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch 488system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions 489system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions 490system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 491system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall 492system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 493system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 494system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 495system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 496system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 497system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions 498system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed 499system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute 500system.cpu.iew.exec_swp 0 # number of swp insts executed 501system.cpu.iew.exec_nop 0 # number of nop insts executed 502system.cpu.iew.exec_refs 3296 # number of memory reference insts executed 503system.cpu.iew.exec_branches 1437 # Number of branches executed 504system.cpu.iew.exec_stores 1160 # Number of stores executed 505system.cpu.iew.exec_rate 0.258268 # Inst execution rate 506system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit 507system.cpu.iew.wb_count 8067 # cumulative count of insts written-back 508system.cpu.iew.wb_producers 3881 # num instructions producing a value 509system.cpu.iew.wb_consumers 7779 # num instructions consuming a value 510system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 511system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle 512system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back 513system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 514system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit 515system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 516system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 517system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle 534system.cpu.commit.committedInsts 4591 # Number of instructions committed 535system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 536system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 537system.cpu.commit.refs 2138 # Number of memory references committed 538system.cpu.commit.loads 1200 # Number of loads committed 539system.cpu.commit.membars 12 # Number of memory barriers committed 540system.cpu.commit.branches 1007 # Number of branches committed 541system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 542system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 543system.cpu.commit.function_calls 82 # Number of function calls committed. 544system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached 545system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 546system.cpu.rob.rob_reads 23271 # The number of ROB reads 547system.cpu.rob.rob_writes 23399 # The number of ROB writes 548system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself 549system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling 550system.cpu.committedInsts 4591 # Number of Instructions Simulated 551system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 552system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 553system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction 554system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads 555system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle 556system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads 557system.cpu.int_regfile_reads 39193 # number of integer regfile reads 558system.cpu.int_regfile_writes 7983 # number of integer regfile writes 559system.cpu.fp_regfile_reads 16 # number of floating regfile reads 560system.cpu.misc_regfile_reads 2975 # number of misc regfile reads 561system.cpu.misc_regfile_writes 24 # number of misc regfile writes 562system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) 563system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution 564system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution 565system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 567system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) 568system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 569system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) 570system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) 571system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 572system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) 573system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) 574system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 575system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) 576system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 577system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) 578system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) 579system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) 580system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 581system.cpu.icache.tags.replacements 4 # number of replacements 582system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use 583system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. 584system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. 585system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. 586system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 587system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor 588system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy 589system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy 590system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits 591system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits 592system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits 593system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits 594system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits 595system.cpu.icache.overall_hits::total 1583 # number of overall hits 596system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 597system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 598system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 599system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 600system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 601system.cpu.icache.overall_misses::total 364 # number of overall misses 602system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles 603system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles 604system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles 605system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles 606system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles 607system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles 608system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 609system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 610system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 611system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 612system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 613system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses 615system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses 616system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses 617system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses 618system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses 619system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses 620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency 621system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency 622system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency 623system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency 625system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency 626system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked 627system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 628system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 629system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 630system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked 631system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu.icache.fast_writes 0 # number of fast writes performed 633system.cpu.icache.cache_copies 0 # number of cache copies performed 634system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 635system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 636system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 637system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 638system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 639system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 640system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses 641system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses 642system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses 643system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses 644system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses 645system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses 646system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles 647system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles 648system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles 649system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles 650system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles 651system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles 652system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses 653system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses 654system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses 655system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses 656system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses 657system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses 658system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency 660system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency 662system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency 664system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 665system.cpu.l2cache.tags.replacements 0 # number of replacements 666system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use 667system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 668system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. 669system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. 670system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 671system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor 672system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor 673system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy 674system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy 675system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy 676system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 677system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 678system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 679system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 680system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 681system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 682system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 683system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 684system.cpu.l2cache.overall_hits::total 40 # number of overall hits 685system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses 686system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 687system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses 688system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 689system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 690system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses 691system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 692system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses 693system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses 694system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 695system.cpu.l2cache.overall_misses::total 398 # number of overall misses 696system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles 697system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles 698system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles 701system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles 704system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles 707system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) 708system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 709system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) 710system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 711system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 712system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses 713system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 714system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses 715system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses 716system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 717system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses 718system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses 721system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 722system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 723system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses 724system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 725system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses 726system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses 727system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 728system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses 729system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency 730system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency 731system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency 732system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency 733system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency 734system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency 735system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency 736system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency 737system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency 738system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency 740system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 741system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 742system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 744system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 745system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 746system.cpu.l2cache.fast_writes 0 # number of fast writes performed 747system.cpu.l2cache.cache_copies 0 # number of cache copies performed 748system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 749system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 750system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 751system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 752system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 753system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 754system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses 755system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 756system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses 757system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 758system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 759system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses 760system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 761system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses 762system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses 763system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 764system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses 765system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles 766system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles 767system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles 768system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles 769system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles 770system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles 771system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles 772system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles 773system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles 774system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles 775system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles 776system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses 777system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 778system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses 779system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 780system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 781system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses 782system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 783system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses 784system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses 785system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 786system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses 787system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency 788system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency 789system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency 790system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency 791system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency 792system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency 793system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency 794system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency 795system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency 796system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency 797system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency 798system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 799system.cpu.dcache.tags.replacements 0 # number of replacements 800system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use 801system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. 802system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 803system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. 804system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 805system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor 806system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy 807system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy 808system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits 809system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits 810system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 811system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 812system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 813system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 814system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 815system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 816system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits 817system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits 818system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits 819system.cpu.dcache.overall_hits::total 2369 # number of overall hits 820system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses 821system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses 822system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 823system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 824system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 825system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 826system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses 827system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses 828system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses 829system.cpu.dcache.overall_misses::total 497 # number of overall misses 830system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles 831system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles 832system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles 833system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles 834system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 835system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 836system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles 837system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles 838system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles 839system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles 840system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) 841system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) 842system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 843system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 844system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 845system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 846system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 847system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 848system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses 849system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses 850system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses 851system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses 852system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 856system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 857system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 858system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses 859system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses 860system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses 861system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses 862system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency 863system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency 865system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency 866system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 867system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 874system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed 880system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits 881system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits 882system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 883system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 884system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 885system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses 907system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses 908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 909system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses 911system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses 912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses 913system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses 914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency 915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency 916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency 917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency 918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency 919system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency 920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency 921system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency 922system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 923 924---------- End Simulation Statistics ----------