12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 397 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 397 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 89 # Per bank write bursts 45system.physmem.perBankRdBursts::1 45 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 43 # Per bank write bursts 48system.physmem.perBankRdBursts::4 18 # Per bank write bursts 49system.physmem.perBankRdBursts::5 32 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 9 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 10 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 17147000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 397 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 203system.physmem.totQLat 3287250 # Total ticks spent queuing 204system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.52 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 331 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 43191.44 # Average gap between requests 224system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ) 233system.physmem_0.averagePower 910.249171 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) 247system.physmem_1.averagePower 808.014211 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 2837 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 865 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 275system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 276system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 277system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 278system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 279system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 280system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 281system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 282system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 283system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 284system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 285system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 286system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 287system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 288system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 296system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 304system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 305system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 306system.cpu.checker.dtb.read_hits 0 # DTB read hits 307system.cpu.checker.dtb.read_misses 0 # DTB read misses 308system.cpu.checker.dtb.write_hits 0 # DTB write hits 309system.cpu.checker.dtb.write_misses 0 # DTB write misses 310system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 320system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 321system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.checker.dtb.hits 0 # DTB hits 323system.cpu.checker.dtb.misses 0 # DTB misses 324system.cpu.checker.dtb.accesses 0 # DTB accesses 325system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 354system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 355system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 362system.cpu.checker.itb.inst_hits 0 # ITB inst hits 363system.cpu.checker.itb.inst_misses 0 # ITB inst misses 364system.cpu.checker.itb.read_hits 0 # DTB read hits 365system.cpu.checker.itb.read_misses 0 # DTB read misses 366system.cpu.checker.itb.write_hits 0 # DTB write hits 367system.cpu.checker.itb.write_misses 0 # DTB write misses 368system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 370system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 371system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 372system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 373system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 374system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 375system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.checker.itb.read_accesses 0 # DTB read accesses 378system.cpu.checker.itb.write_accesses 0 # DTB write accesses 379system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.checker.itb.hits 0 # DTB hits 381system.cpu.checker.itb.misses 0 # DTB misses 382system.cpu.checker.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 13 # Number of system calls 384system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 385system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 387system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 388system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 391system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 394system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 395system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 396system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 397system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 398system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 399system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 400system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 401system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 402system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 403system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 404system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 405system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 406system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 407system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 408system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 409system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 411system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 412system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 413system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 414system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 415system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 416system.cpu.dtb.walker.walks 0 # Table walker walks requested 417system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 421system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 424system.cpu.dtb.inst_hits 0 # ITB inst hits 425system.cpu.dtb.inst_misses 0 # ITB inst misses 426system.cpu.dtb.read_hits 0 # DTB read hits 427system.cpu.dtb.read_misses 0 # DTB read misses 428system.cpu.dtb.write_hits 0 # DTB write hits 429system.cpu.dtb.write_misses 0 # DTB write misses 430system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 431system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 432system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 433system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 434system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 435system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 436system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 437system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 438system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 439system.cpu.dtb.read_accesses 0 # DTB read accesses 440system.cpu.dtb.write_accesses 0 # DTB write accesses 441system.cpu.dtb.inst_accesses 0 # ITB inst accesses 442system.cpu.dtb.hits 0 # DTB hits 443system.cpu.dtb.misses 0 # DTB misses 444system.cpu.dtb.accesses 0 # DTB accesses 445system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 454system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 455system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 456system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 457system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 458system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 459system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 460system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 461system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 462system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 463system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 464system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 465system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 466system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 468system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 469system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 470system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 471system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 472system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 473system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 474system.cpu.itb.walker.walks 0 # Table walker walks requested 475system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 478system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 479system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 480system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 481system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 482system.cpu.itb.inst_hits 0 # ITB inst hits 483system.cpu.itb.inst_misses 0 # ITB inst misses 484system.cpu.itb.read_hits 0 # DTB read hits 485system.cpu.itb.read_misses 0 # DTB read misses 486system.cpu.itb.write_hits 0 # DTB write hits 487system.cpu.itb.write_misses 0 # DTB write misses 488system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 489system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 490system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 491system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 492system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 493system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 494system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 495system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 496system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 497system.cpu.itb.read_accesses 0 # DTB read accesses 498system.cpu.itb.write_accesses 0 # DTB write accesses 499system.cpu.itb.inst_accesses 0 # ITB inst accesses 500system.cpu.itb.hits 0 # DTB hits 501system.cpu.itb.misses 0 # DTB misses 502system.cpu.itb.accesses 0 # DTB accesses 503system.cpu.numCycles 34466 # number of cpu cycles simulated 504system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 505system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 506system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss 507system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed 508system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered 509system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken 510system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked 511system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing 512system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 513system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps 514system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 515system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched 516system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed 517system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total) 518system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total) 519system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total) 520system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 521system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total) 522system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total) 523system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total) 524system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total) 525system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total) 526system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total) 527system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) 528system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total) 529system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total) 530system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 531system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 532system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 533system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total) 534system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle 535system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle 536system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle 537system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked 538system.cpu.decode.RunCycles 2142 # Number of cycles decode is running 539system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 540system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing 541system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch 542system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 543system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode 544system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode 545system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing 546system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle 547system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking 548system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst 549system.cpu.rename.RunCycles 2037 # Number of cycles rename is running 550system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking 551system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename 552system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 553system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full 554system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full 555system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full 556system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed
| 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 397 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 397 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 89 # Per bank write bursts 45system.physmem.perBankRdBursts::1 45 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 43 # Per bank write bursts 48system.physmem.perBankRdBursts::4 18 # Per bank write bursts 49system.physmem.perBankRdBursts::5 32 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 9 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 10 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 17147000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 397 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 203system.physmem.totQLat 3287250 # Total ticks spent queuing 204system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.52 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 331 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 43191.44 # Average gap between requests 224system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ) 233system.physmem_0.averagePower 910.249171 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) 247system.physmem_1.averagePower 808.014211 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 2837 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 865 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 275system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 276system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 277system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 278system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 279system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 280system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 281system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 282system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 283system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 284system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 285system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 286system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 287system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 288system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 296system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 304system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 305system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 306system.cpu.checker.dtb.read_hits 0 # DTB read hits 307system.cpu.checker.dtb.read_misses 0 # DTB read misses 308system.cpu.checker.dtb.write_hits 0 # DTB write hits 309system.cpu.checker.dtb.write_misses 0 # DTB write misses 310system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 320system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 321system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.checker.dtb.hits 0 # DTB hits 323system.cpu.checker.dtb.misses 0 # DTB misses 324system.cpu.checker.dtb.accesses 0 # DTB accesses 325system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 354system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 355system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 362system.cpu.checker.itb.inst_hits 0 # ITB inst hits 363system.cpu.checker.itb.inst_misses 0 # ITB inst misses 364system.cpu.checker.itb.read_hits 0 # DTB read hits 365system.cpu.checker.itb.read_misses 0 # DTB read misses 366system.cpu.checker.itb.write_hits 0 # DTB write hits 367system.cpu.checker.itb.write_misses 0 # DTB write misses 368system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 370system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 371system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 372system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 373system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 374system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 375system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.checker.itb.read_accesses 0 # DTB read accesses 378system.cpu.checker.itb.write_accesses 0 # DTB write accesses 379system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.checker.itb.hits 0 # DTB hits 381system.cpu.checker.itb.misses 0 # DTB misses 382system.cpu.checker.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 13 # Number of system calls 384system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 385system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 387system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 388system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 391system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 394system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 395system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 396system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 397system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 398system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 399system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 400system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 401system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 402system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 403system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 404system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 405system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 406system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 407system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 408system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 409system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 411system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 412system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 413system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 414system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 415system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 416system.cpu.dtb.walker.walks 0 # Table walker walks requested 417system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 421system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 424system.cpu.dtb.inst_hits 0 # ITB inst hits 425system.cpu.dtb.inst_misses 0 # ITB inst misses 426system.cpu.dtb.read_hits 0 # DTB read hits 427system.cpu.dtb.read_misses 0 # DTB read misses 428system.cpu.dtb.write_hits 0 # DTB write hits 429system.cpu.dtb.write_misses 0 # DTB write misses 430system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 431system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 432system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 433system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 434system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 435system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 436system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 437system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 438system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 439system.cpu.dtb.read_accesses 0 # DTB read accesses 440system.cpu.dtb.write_accesses 0 # DTB write accesses 441system.cpu.dtb.inst_accesses 0 # ITB inst accesses 442system.cpu.dtb.hits 0 # DTB hits 443system.cpu.dtb.misses 0 # DTB misses 444system.cpu.dtb.accesses 0 # DTB accesses 445system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 454system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 455system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 456system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 457system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 458system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 459system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 460system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 461system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 462system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 463system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 464system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 465system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 466system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 468system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 469system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 470system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 471system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 472system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 473system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 474system.cpu.itb.walker.walks 0 # Table walker walks requested 475system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 478system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 479system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 480system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 481system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 482system.cpu.itb.inst_hits 0 # ITB inst hits 483system.cpu.itb.inst_misses 0 # ITB inst misses 484system.cpu.itb.read_hits 0 # DTB read hits 485system.cpu.itb.read_misses 0 # DTB read misses 486system.cpu.itb.write_hits 0 # DTB write hits 487system.cpu.itb.write_misses 0 # DTB write misses 488system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 489system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 490system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 491system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 492system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 493system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 494system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 495system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 496system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 497system.cpu.itb.read_accesses 0 # DTB read accesses 498system.cpu.itb.write_accesses 0 # DTB write accesses 499system.cpu.itb.inst_accesses 0 # ITB inst accesses 500system.cpu.itb.hits 0 # DTB hits 501system.cpu.itb.misses 0 # DTB misses 502system.cpu.itb.accesses 0 # DTB accesses 503system.cpu.numCycles 34466 # number of cpu cycles simulated 504system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 505system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 506system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss 507system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed 508system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered 509system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken 510system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked 511system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing 512system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 513system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps 514system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 515system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched 516system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed 517system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total) 518system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total) 519system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total) 520system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 521system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total) 522system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total) 523system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total) 524system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total) 525system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total) 526system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total) 527system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) 528system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total) 529system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total) 530system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 531system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 532system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 533system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total) 534system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle 535system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle 536system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle 537system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked 538system.cpu.decode.RunCycles 2142 # Number of cycles decode is running 539system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 540system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing 541system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch 542system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 543system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode 544system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode 545system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing 546system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle 547system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking 548system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst 549system.cpu.rename.RunCycles 2037 # Number of cycles rename is running 550system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking 551system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename 552system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 553system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full 554system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full 555system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full 556system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed
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