Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt

stats.txt (10812:bacaefeb126a)	stats.txt (10827:7f5467f2f8b8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17398000 # Number of ticks simulated 5final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17398000 # Number of ticks simulated 5final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 32773 # Simulator instruction rate (inst/s) 8host_op_rate 38377 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 124135140 # Simulator tick rate (ticks/s) 10host_mem_usage 303432 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host	7host_inst_rate 57922 # Simulator instruction rate (inst/s) 8host_op_rate 67825 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 219380871 # Simulator tick rate (ticks/s) 10host_mem_usage 310080 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host
12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7680 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25344 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 120 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 396 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1015289114 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 441430049 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1456719163 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1015289114 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1015289114 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1015289114 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 441430049 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1456719163 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 396 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 90 # Per bank write bursts 45system.physmem.perBankRdBursts::1 45 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 43 # Per bank write bursts 48system.physmem.perBankRdBursts::4 18 # Per bank write bursts 49system.physmem.perBankRdBursts::5 32 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 8 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 9 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 17318000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 396 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 410.033898 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 279.539573 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 339.305882 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 9 15.25% 15.25% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 16 27.12% 42.37% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 13.56% 55.93% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 9 15.25% 71.19% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 2 3.39% 74.58% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.39% 77.97% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation 203system.physmem.totQLat 3886750 # Total ticks spent queuing 204system.physmem.totMemAccLat 11311750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 9815.03 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 28565.03 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1456.72 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1456.72 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.38 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 331 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 43732.32 # Average gap between requests 224system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10748205 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 71250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 14332005 # Total energy per rank (pJ) 233system.physmem_0.averagePower 905.226907 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 62750 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 15263500 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 741000 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 465000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 12744465 # Total energy per rank (pJ) 247system.physmem_1.averagePower 804.955945 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 732000 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 14594250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 2567 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1598 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2080 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 778 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 37.403846 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 334 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 270system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 271system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 272system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 273system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 274system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 275system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 276system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 277system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 278system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 279system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 280system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 281system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 282system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 283system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 284system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 285system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 286system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 287system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 288system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 289system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 290system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 291system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 292system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 293system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 296system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 299system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 300system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 301system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 302system.cpu.checker.dtb.read_hits 0 # DTB read hits 303system.cpu.checker.dtb.read_misses 0 # DTB read misses 304system.cpu.checker.dtb.write_hits 0 # DTB write hits 305system.cpu.checker.dtb.write_misses 0 # DTB write misses 306system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 307system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 308system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 309system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 310system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 311system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 312system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 313system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 314system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 315system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 316system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 317system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 318system.cpu.checker.dtb.hits 0 # DTB hits 319system.cpu.checker.dtb.misses 0 # DTB misses 320system.cpu.checker.dtb.accesses 0 # DTB accesses 321system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 322system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 325system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 326system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 327system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 328system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 329system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 330system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 331system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 332system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 333system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 334system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 335system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 336system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 337system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 338system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 339system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 340system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 341system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 342system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 343system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 344system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 345system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 346system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 347system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 348system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 349system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 350system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 351system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 354system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 357system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 358system.cpu.checker.itb.inst_hits 0 # ITB inst hits 359system.cpu.checker.itb.inst_misses 0 # ITB inst misses 360system.cpu.checker.itb.read_hits 0 # DTB read hits 361system.cpu.checker.itb.read_misses 0 # DTB read misses 362system.cpu.checker.itb.write_hits 0 # DTB write hits 363system.cpu.checker.itb.write_misses 0 # DTB write misses 364system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 365system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 366system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 367system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 368system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 369system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 370system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 371system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 372system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.checker.itb.read_accesses 0 # DTB read accesses 374system.cpu.checker.itb.write_accesses 0 # DTB write accesses 375system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.checker.itb.hits 0 # DTB hits 377system.cpu.checker.itb.misses 0 # DTB misses 378system.cpu.checker.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 13 # Number of system calls 380system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 381system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 384system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 391system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 392system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 393system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 394system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 395system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 396system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 397system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 398system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 399system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 402system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 407system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 408system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 409system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 410system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 411system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 412system.cpu.dtb.walker.walks 0 # Table walker walks requested 413system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 420system.cpu.dtb.inst_hits 0 # ITB inst hits 421system.cpu.dtb.inst_misses 0 # ITB inst misses 422system.cpu.dtb.read_hits 0 # DTB read hits 423system.cpu.dtb.read_misses 0 # DTB read misses 424system.cpu.dtb.write_hits 0 # DTB write hits 425system.cpu.dtb.write_misses 0 # DTB write misses 426system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 427system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 428system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 429system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 430system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 431system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 432system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 433system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 435system.cpu.dtb.read_accesses 0 # DTB read accesses 436system.cpu.dtb.write_accesses 0 # DTB write accesses 437system.cpu.dtb.inst_accesses 0 # ITB inst accesses 438system.cpu.dtb.hits 0 # DTB hits 439system.cpu.dtb.misses 0 # DTB misses 440system.cpu.dtb.accesses 0 # DTB accesses 441system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 450system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 451system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 452system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 453system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 454system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 455system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 456system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 457system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 459system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 460system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 461system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 462system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 464system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 465system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 466system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 467system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 468system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 469system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 470system.cpu.itb.walker.walks 0 # Table walker walks requested 471system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 472system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 474system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 475system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 478system.cpu.itb.inst_hits 0 # ITB inst hits 479system.cpu.itb.inst_misses 0 # ITB inst misses 480system.cpu.itb.read_hits 0 # DTB read hits 481system.cpu.itb.read_misses 0 # DTB read misses 482system.cpu.itb.write_hits 0 # DTB write hits 483system.cpu.itb.write_misses 0 # DTB write misses 484system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 485system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 486system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 488system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 489system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 490system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 491system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 493system.cpu.itb.read_accesses 0 # DTB read accesses 494system.cpu.itb.write_accesses 0 # DTB write accesses 495system.cpu.itb.inst_accesses 0 # ITB inst accesses 496system.cpu.itb.hits 0 # DTB hits 497system.cpu.itb.misses 0 # DTB misses 498system.cpu.itb.accesses 0 # DTB accesses 499system.cpu.numCycles 34797 # number of cpu cycles simulated 500system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 501system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 502system.cpu.fetch.icacheStallCycles 7703 # Number of cycles fetch is stalled on an Icache miss 503system.cpu.fetch.Insts 12168 # Number of instructions fetch has processed 504system.cpu.fetch.Branches 2567 # Number of branches that fetch encountered 505system.cpu.fetch.predictedBranches 1112 # Number of branches that fetch has predicted taken 506system.cpu.fetch.Cycles 4777 # Number of cycles fetch has run and was not squashing or blocked 507system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing 508system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 509system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps 510system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 511system.cpu.fetch.CacheLines 2007 # Number of cache lines fetched 512system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed 513system.cpu.fetch.rateDist::samples 13242 # Number of instructions fetched each cycle (Total) 514system.cpu.fetch.rateDist::mean 1.084202 # Number of instructions fetched each cycle (Total) 515system.cpu.fetch.rateDist::stdev 2.460827 # Number of instructions fetched each cycle (Total) 516system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 517system.cpu.fetch.rateDist::0 10620 80.20% 80.20% # Number of instructions fetched each cycle (Total) 518system.cpu.fetch.rateDist::1 274 2.07% 82.27% # Number of instructions fetched each cycle (Total) 519system.cpu.fetch.rateDist::2 209 1.58% 83.85% # Number of instructions fetched each cycle (Total) 520system.cpu.fetch.rateDist::3 222 1.68% 85.52% # Number of instructions fetched each cycle (Total) 521system.cpu.fetch.rateDist::4 233 1.76% 87.28% # Number of instructions fetched each cycle (Total) 522system.cpu.fetch.rateDist::5 323 2.44% 89.72% # Number of instructions fetched each cycle (Total) 523system.cpu.fetch.rateDist::6 137 1.03% 90.76% # Number of instructions fetched each cycle (Total) 524system.cpu.fetch.rateDist::7 162 1.22% 91.98% # Number of instructions fetched each cycle (Total) 525system.cpu.fetch.rateDist::8 1062 8.02% 100.00% # Number of instructions fetched each cycle (Total) 526system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 527system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 528system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 529system.cpu.fetch.rateDist::total 13242 # Number of instructions fetched each cycle (Total) 530system.cpu.fetch.branchRate 0.073771 # Number of branch fetches per cycle 531system.cpu.fetch.rate 0.349685 # Number of inst fetches per cycle 532system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle 533system.cpu.decode.BlockedCycles 4330 # Number of cycles decode is blocked 534system.cpu.decode.RunCycles 2103 # Number of cycles decode is running 535system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking 536system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing 537system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 538system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction 539system.cpu.decode.DecodedInsts 11850 # Number of instructions handled by decode 540system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode 541system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing 542system.cpu.rename.IdleCycles 6554 # Number of cycles rename is idle 543system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking 544system.cpu.rename.serializeStallCycles 2396 # count of cycles rename stalled for serializing inst 545system.cpu.rename.RunCycles 2012 # Number of cycles rename is running 546system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking 547system.cpu.rename.RenamedInsts 11194 # Number of instructions processed by rename 548system.cpu.rename.IQFullEvents 171 # Number of times rename has blocked due to IQ full 549system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full 550system.cpu.rename.SQFullEvents 1066 # Number of times rename has blocked due to SQ full 551system.cpu.rename.RenamedOperands 11323 # Number of destination operands rename has renamed 552system.cpu.rename.RenameLookups 51655 # Number of register rename lookups that rename has made 553system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups 554system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups 555system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 556system.cpu.rename.UndoneMaps 5829 # Number of HB maps that are undone due to squashing 557system.cpu.rename.serializingInsts 42 # count of serializing insts renamed 558system.cpu.rename.tempSerializingInsts 36 # count of temporary serializing insts renamed 559system.cpu.rename.skidInsts 409 # count of insts added to the skid buffer 560system.cpu.memDep0.insertedLoads 2284 # Number of loads inserted to the mem dependence unit. 561system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit. 562system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. 563system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. 564system.cpu.iq.iqInstsAdded 10118 # Number of instructions added to the IQ (excludes non-spec) 565system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ 566system.cpu.iq.iqInstsIssued 8189 # Number of instructions issued 567system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued 568system.cpu.iq.iqSquashedInstsExamined 4786 # Number of squashed instructions iterated over during squash; mainly for profiling 569system.cpu.iq.iqSquashedOperandsExamined 12366 # Number of squashed operands that are examined and possibly removed from graph 570system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed 571system.cpu.iq.issued_per_cycle::samples 13242 # Number of insts issued each cycle 572system.cpu.iq.issued_per_cycle::mean 0.618411 # Number of insts issued each cycle 573system.cpu.iq.issued_per_cycle::stdev 1.365218 # Number of insts issued each cycle 574system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 575system.cpu.iq.issued_per_cycle::0 10034 75.77% 75.77% # Number of insts issued each cycle 576system.cpu.iq.issued_per_cycle::1 1166 8.81% 84.58% # Number of insts issued each cycle 577system.cpu.iq.issued_per_cycle::2 746 5.63% 90.21% # Number of insts issued each cycle 578system.cpu.iq.issued_per_cycle::3 448 3.38% 93.60% # Number of insts issued each cycle 579system.cpu.iq.issued_per_cycle::4 359 2.71% 96.31% # Number of insts issued each cycle 580system.cpu.iq.issued_per_cycle::5 279 2.11% 98.41% # Number of insts issued each cycle 581system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle 582system.cpu.iq.issued_per_cycle::7 62 0.47% 99.87% # Number of insts issued each cycle 583system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle 584system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 585system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 586system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 587system.cpu.iq.issued_per_cycle::total 13242 # Number of insts issued each cycle 588system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 589system.cpu.iq.fu_full::IntAlu 9 5.20% 5.20% # attempts to use FU when none available 590system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available 591system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available 592system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available 593system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available 594system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available 595system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available 596system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available 597system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available 598system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available 599system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available 600system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available 601system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available 602system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available 603system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available 604system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available 605system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available 606system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available 607system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available 608system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available 609system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available 610system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available 611system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available 612system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available 613system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available 614system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available 615system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available 616system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available 617system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available 618system.cpu.iq.fu_full::MemRead 84 48.55% 53.76% # attempts to use FU when none available 619system.cpu.iq.fu_full::MemWrite 80 46.24% 100.00% # attempts to use FU when none available 620system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 621system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 622system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 623system.cpu.iq.FU_type_0::IntAlu 4931 60.21% 60.21% # Type of FU issued 624system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.29% # Type of FU issued 625system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.29% # Type of FU issued 626system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.29% # Type of FU issued 627system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.29% # Type of FU issued 628system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.29% # Type of FU issued 629system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.29% # Type of FU issued 630system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.29% # Type of FU issued 631system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.29% # Type of FU issued 632system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.29% # Type of FU issued 633system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.29% # Type of FU issued 634system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.29% # Type of FU issued 635system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.29% # Type of FU issued 636system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.29% # Type of FU issued 637system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.29% # Type of FU issued 638system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.29% # Type of FU issued 639system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.29% # Type of FU issued 640system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.29% # Type of FU issued 641system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.29% # Type of FU issued 642system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.29% # Type of FU issued 643system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.29% # Type of FU issued 644system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.29% # Type of FU issued 645system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.29% # Type of FU issued 646system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.29% # Type of FU issued 647system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.29% # Type of FU issued 648system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.32% # Type of FU issued 649system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued 650system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.32% # Type of FU issued 651system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued 652system.cpu.iq.FU_type_0::MemRead 1952 23.84% 84.16% # Type of FU issued 653system.cpu.iq.FU_type_0::MemWrite 1297 15.84% 100.00% # Type of FU issued 654system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 655system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 656system.cpu.iq.FU_type_0::total 8189 # Type of FU issued 657system.cpu.iq.rate 0.235336 # Inst issue rate 658system.cpu.iq.fu_busy_cnt 173 # FU busy when requested 659system.cpu.iq.fu_busy_rate 0.021126 # FU busy rate (busy events/executed inst) 660system.cpu.iq.int_inst_queue_reads 29748 # Number of integer instruction queue reads 661system.cpu.iq.int_inst_queue_writes 14841 # Number of integer instruction queue writes 662system.cpu.iq.int_inst_queue_wakeup_accesses 7422 # Number of integer instruction queue wakeup accesses 663system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads 664system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes 665system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses 666system.cpu.iq.int_alu_accesses 8319 # Number of integer alu accesses 667system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 668system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores 669system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 670system.cpu.iew.lsq.thread0.squashedLoads 1257 # Number of loads squashed 671system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 672system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 673system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed 674system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 675system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 676system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled 677system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 678system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 679system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing 680system.cpu.iew.iewBlockCycles 662 # Number of cycles IEW is blocking 681system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking 682system.cpu.iew.iewDispatchedInsts 10173 # Number of instructions dispatched to IQ 683system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch 684system.cpu.iew.iewDispLoadInsts 2284 # Number of dispatched load instructions 685system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions 686system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions 687system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall 688system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall 689system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 690system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly 691system.cpu.iew.predictedNotTakenIncorrect 233 # Number of branches that were predicted not taken incorrectly 692system.cpu.iew.branchMispredicts 344 # Number of branch mispredicts detected at execute 693system.cpu.iew.iewExecutedInsts 7858 # Number of executed instructions 694system.cpu.iew.iewExecLoadInsts 1841 # Number of load instructions executed 695system.cpu.iew.iewExecSquashedInsts 331 # Number of squashed instructions skipped in execute 696system.cpu.iew.exec_swp 0 # number of swp insts executed 697system.cpu.iew.exec_nop 9 # number of nop insts executed 698system.cpu.iew.exec_refs 3070 # number of memory reference insts executed 699system.cpu.iew.exec_branches 1431 # Number of branches executed 700system.cpu.iew.exec_stores 1229 # Number of stores executed 701system.cpu.iew.exec_rate 0.225824 # Inst execution rate 702system.cpu.iew.wb_sent 7567 # cumulative count of insts sent to commit 703system.cpu.iew.wb_count 7454 # cumulative count of insts written-back 704system.cpu.iew.wb_producers 3520 # num instructions producing a value 705system.cpu.iew.wb_consumers 6887 # num instructions consuming a value 706system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 707system.cpu.iew.wb_rate 0.214214 # insts written-back per cycle 708system.cpu.iew.wb_fanout 0.511108 # average fanout of values written-back 709system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 710system.cpu.commit.commitSquashedInsts 4794 # The number of squashed insts skipped by commit 711system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 712system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted 713system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle 714system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle 715system.cpu.commit.committed_per_cycle::stdev 1.280415 # Number of insts commited each cycle 716system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 717system.cpu.commit.committed_per_cycle::0 10350 83.44% 83.44% # Number of insts commited each cycle 718system.cpu.commit.committed_per_cycle::1 890 7.18% 90.62% # Number of insts commited each cycle 719system.cpu.commit.committed_per_cycle::2 420 3.39% 94.00% # Number of insts commited each cycle 720system.cpu.commit.committed_per_cycle::3 213 1.72% 95.72% # Number of insts commited each cycle 721system.cpu.commit.committed_per_cycle::4 118 0.95% 96.67% # Number of insts commited each cycle 722system.cpu.commit.committed_per_cycle::5 211 1.70% 98.37% # Number of insts commited each cycle 723system.cpu.commit.committed_per_cycle::6 49 0.40% 98.77% # Number of insts commited each cycle 724system.cpu.commit.committed_per_cycle::7 36 0.29% 99.06% # Number of insts commited each cycle 725system.cpu.commit.committed_per_cycle::8 117 0.94% 100.00% # Number of insts commited each cycle 726system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 727system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 728system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 729system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle 730system.cpu.commit.committedInsts 4592 # Number of instructions committed 731system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 732system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 733system.cpu.commit.refs 1965 # Number of memory references committed 734system.cpu.commit.loads 1027 # Number of loads committed 735system.cpu.commit.membars 12 # Number of memory barriers committed 736system.cpu.commit.branches 1008 # Number of branches committed 737system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 738system.cpu.commit.int_insts 4624 # Number of committed integer instructions. 739system.cpu.commit.function_calls 82 # Number of function calls committed. 740system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 741system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 742system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 743system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 744system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 745system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 746system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 747system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 748system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 749system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 750system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 751system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 752system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 753system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 754system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 755system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 756system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 757system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 758system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 759system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 760system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 761system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 762system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 763system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 764system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 765system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 766system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 767system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 768system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 769system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 770system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 771system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 772system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 773system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 774system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 775system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 776system.cpu.rob.rob_reads 22302 # The number of ROB reads 777system.cpu.rob.rob_writes 21197 # The number of ROB writes 778system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself 779system.cpu.idleCycles 21555 # Total number of cycles that the CPU has spent unscheduled due to idling 780system.cpu.committedInsts 4592 # Number of Instructions Simulated 781system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 782system.cpu.cpi 7.577744 # CPI: Cycles Per Instruction 783system.cpu.cpi_total 7.577744 # CPI: Total CPI of All Threads 784system.cpu.ipc 0.131965 # IPC: Instructions Per Cycle 785system.cpu.ipc_total 0.131965 # IPC: Total IPC of All Threads 786system.cpu.int_regfile_reads 7744 # number of integer regfile reads 787system.cpu.int_regfile_writes 4257 # number of integer regfile writes 788system.cpu.fp_regfile_reads 32 # number of floating regfile reads 789system.cpu.cc_regfile_reads 28092 # number of cc regfile reads 790system.cpu.cc_regfile_writes 3277 # number of cc regfile writes 791system.cpu.misc_regfile_reads 3176 # number of misc regfile reads 792system.cpu.misc_regfile_writes 24 # number of misc regfile writes 793system.cpu.dcache.tags.replacements 0 # number of replacements 794system.cpu.dcache.tags.tagsinuse 87.050512 # Cycle average of tags in use 795system.cpu.dcache.tags.total_refs 2159 # Total number of references to valid blocks. 796system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 797system.cpu.dcache.tags.avg_refs 14.687075 # Average number of references to valid blocks. 798system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 799system.cpu.dcache.tags.occ_blocks::cpu.data 87.050512 # Average occupied blocks per requestor 800system.cpu.dcache.tags.occ_percent::cpu.data 0.021253 # Average percentage of cache occupancy 801system.cpu.dcache.tags.occ_percent::total 0.021253 # Average percentage of cache occupancy 802system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 803system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 804system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 805system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 806system.cpu.dcache.tags.tag_accesses 5463 # Number of tag accesses 807system.cpu.dcache.tags.data_accesses 5463 # Number of data accesses 808system.cpu.dcache.ReadReq_hits::cpu.data 1539 # number of ReadReq hits 809system.cpu.dcache.ReadReq_hits::total 1539 # number of ReadReq hits 810system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits 811system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits 812system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 813system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 814system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 815system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 816system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits 817system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits 818system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits 819system.cpu.dcache.overall_hits::total 2137 # number of overall hits 820system.cpu.dcache.ReadReq_misses::cpu.data 182 # number of ReadReq misses 821system.cpu.dcache.ReadReq_misses::total 182 # number of ReadReq misses 822system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses 823system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses 824system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 825system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 826system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses 827system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses 828system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses 829system.cpu.dcache.overall_misses::total 497 # number of overall misses 830system.cpu.dcache.ReadReq_miss_latency::cpu.data 10876493 # number of ReadReq miss cycles 831system.cpu.dcache.ReadReq_miss_latency::total 10876493 # number of ReadReq miss cycles 832system.cpu.dcache.WriteReq_miss_latency::cpu.data 22731000 # number of WriteReq miss cycles 833system.cpu.dcache.WriteReq_miss_latency::total 22731000 # number of WriteReq miss cycles 834system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles 835system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles 836system.cpu.dcache.demand_miss_latency::cpu.data 33607493 # number of demand (read+write) miss cycles 837system.cpu.dcache.demand_miss_latency::total 33607493 # number of demand (read+write) miss cycles 838system.cpu.dcache.overall_miss_latency::cpu.data 33607493 # number of overall miss cycles 839system.cpu.dcache.overall_miss_latency::total 33607493 # number of overall miss cycles 840system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) 841system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) 842system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 843system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 844system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 845system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 846system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 847system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 848system.cpu.dcache.demand_accesses::cpu.data 2634 # number of demand (read+write) accesses 849system.cpu.dcache.demand_accesses::total 2634 # number of demand (read+write) accesses 850system.cpu.dcache.overall_accesses::cpu.data 2634 # number of overall (read+write) accesses 851system.cpu.dcache.overall_accesses::total 2634 # number of overall (read+write) accesses 852system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.105752 # miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_miss_rate::total 0.105752 # miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses 856system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 857system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 858system.cpu.dcache.demand_miss_rate::cpu.data 0.188686 # miss rate for demand accesses 859system.cpu.dcache.demand_miss_rate::total 0.188686 # miss rate for demand accesses 860system.cpu.dcache.overall_miss_rate::cpu.data 0.188686 # miss rate for overall accesses 861system.cpu.dcache.overall_miss_rate::total 0.188686 # miss rate for overall accesses 862system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59760.950549 # average ReadReq miss latency 863system.cpu.dcache.ReadReq_avg_miss_latency::total 59760.950549 # average ReadReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72161.904762 # average WriteReq miss latency 865system.cpu.dcache.WriteReq_avg_miss_latency::total 72161.904762 # average WriteReq miss latency 866system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency 867system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 67620.710262 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 67620.710262 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 874system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed 880system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 881system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 882system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits 883system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits 884system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 885system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6879255 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 6879255 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10269755 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 10269755 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10269755 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 10269755 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.061011 # mshr miss rate for ReadReq accesses 907system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.061011 # mshr miss rate for ReadReq accesses 908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 909system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for demand accesses 911system.cpu.dcache.demand_mshr_miss_rate::total 0.055809 # mshr miss rate for demand accesses 912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for overall accesses 913system.cpu.dcache.overall_mshr_miss_rate::total 0.055809 # mshr miss rate for overall accesses 914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65516.714286 # average ReadReq mshr miss latency 915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65516.714286 # average ReadReq mshr miss latency 916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency 917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency 918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency 919system.cpu.dcache.demand_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency 920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency 921system.cpu.dcache.overall_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency 922system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 923system.cpu.icache.tags.replacements 1 # number of replacements 924system.cpu.icache.tags.tagsinuse 149.166565 # Cycle average of tags in use 925system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. 926system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. 927system.cpu.icache.tags.avg_refs 5.505119 # Average number of references to valid blocks. 928system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 929system.cpu.icache.tags.occ_blocks::cpu.inst 149.166565 # Average occupied blocks per requestor 930system.cpu.icache.tags.occ_percent::cpu.inst 0.072835 # Average percentage of cache occupancy 931system.cpu.icache.tags.occ_percent::total 0.072835 # Average percentage of cache occupancy 932system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 933system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 934system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 935system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 936system.cpu.icache.tags.tag_accesses 4307 # Number of tag accesses 937system.cpu.icache.tags.data_accesses 4307 # Number of data accesses 938system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits 939system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits 940system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits 941system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits 942system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits 943system.cpu.icache.overall_hits::total 1613 # number of overall hits 944system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses 945system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses 946system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses 947system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses 948system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses 949system.cpu.icache.overall_misses::total 394 # number of overall misses 950system.cpu.icache.ReadReq_miss_latency::cpu.inst 28003250 # number of ReadReq miss cycles 951system.cpu.icache.ReadReq_miss_latency::total 28003250 # number of ReadReq miss cycles 952system.cpu.icache.demand_miss_latency::cpu.inst 28003250 # number of demand (read+write) miss cycles 953system.cpu.icache.demand_miss_latency::total 28003250 # number of demand (read+write) miss cycles 954system.cpu.icache.overall_miss_latency::cpu.inst 28003250 # number of overall miss cycles 955system.cpu.icache.overall_miss_latency::total 28003250 # number of overall miss cycles 956system.cpu.icache.ReadReq_accesses::cpu.inst 2007 # number of ReadReq accesses(hits+misses) 957system.cpu.icache.ReadReq_accesses::total 2007 # number of ReadReq accesses(hits+misses) 958system.cpu.icache.demand_accesses::cpu.inst 2007 # number of demand (read+write) accesses 959system.cpu.icache.demand_accesses::total 2007 # number of demand (read+write) accesses 960system.cpu.icache.overall_accesses::cpu.inst 2007 # number of overall (read+write) accesses 961system.cpu.icache.overall_accesses::total 2007 # number of overall (read+write) accesses 962system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196313 # miss rate for ReadReq accesses 963system.cpu.icache.ReadReq_miss_rate::total 0.196313 # miss rate for ReadReq accesses 964system.cpu.icache.demand_miss_rate::cpu.inst 0.196313 # miss rate for demand accesses 965system.cpu.icache.demand_miss_rate::total 0.196313 # miss rate for demand accesses 966system.cpu.icache.overall_miss_rate::cpu.inst 0.196313 # miss rate for overall accesses 967system.cpu.icache.overall_miss_rate::total 0.196313 # miss rate for overall accesses 968system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71074.238579 # average ReadReq miss latency 969system.cpu.icache.ReadReq_avg_miss_latency::total 71074.238579 # average ReadReq miss latency 970system.cpu.icache.demand_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency 971system.cpu.icache.demand_avg_miss_latency::total 71074.238579 # average overall miss latency 972system.cpu.icache.overall_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency 973system.cpu.icache.overall_avg_miss_latency::total 71074.238579 # average overall miss latency 974system.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked 975system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 976system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 977system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 978system.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 # average number of cycles each access was blocked 979system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 980system.cpu.icache.fast_writes 0 # number of fast writes performed 981system.cpu.icache.cache_copies 0 # number of cache copies performed 982system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits 983system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits 984system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits 985system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits 986system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits 987system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits 988system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses 989system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses 990system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 991system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses 992system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 993system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses 994system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22179000 # number of ReadReq MSHR miss cycles 995system.cpu.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles 996system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22179000 # number of demand (read+write) MSHR miss cycles 997system.cpu.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles 998system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22179000 # number of overall MSHR miss cycles 999system.cpu.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles 1000system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for ReadReq accesses 1001system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145989 # mshr miss rate for ReadReq accesses 1002system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for demand accesses 1003system.cpu.icache.demand_mshr_miss_rate::total 0.145989 # mshr miss rate for demand accesses 1004system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for overall accesses 1005system.cpu.icache.overall_mshr_miss_rate::total 0.145989 # mshr miss rate for overall accesses 1006system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75696.245734 # average ReadReq mshr miss latency 1007system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75696.245734 # average ReadReq mshr miss latency 1008system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency 1009system.cpu.icache.demand_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency 1010system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency 1011system.cpu.icache.overall_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency 1012system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1013system.cpu.l2cache.tags.replacements 0 # number of replacements 1014system.cpu.l2cache.tags.tagsinuse 186.073007 # Cycle average of tags in use 1015system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 1016system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. 1017system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. 1018system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1019system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.074126 # Average occupied blocks per requestor 1020system.cpu.l2cache.tags.occ_blocks::cpu.data 45.998881 # Average occupied blocks per requestor 1021system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004275 # Average percentage of cache occupancy 1022system.cpu.l2cache.tags.occ_percent::cpu.data 0.001404 # Average percentage of cache occupancy 1023system.cpu.l2cache.tags.occ_percent::total 0.005678 # Average percentage of cache occupancy 1024system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 1025system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 1026system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id 1027system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id 1028system.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses 1029system.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses 1030system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 1031system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits 1032system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 1033system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 1034system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits 1035system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 1036system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 1037system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits 1038system.cpu.l2cache.overall_hits::total 39 # number of overall hits 1039system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses 1040system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses 1041system.cpu.l2cache.ReadReq_misses::total 359 # number of ReadReq misses 1042system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 1043system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 1044system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 1045system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 1046system.cpu.l2cache.demand_misses::total 401 # number of demand (read+write) misses 1047system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 1048system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 1049system.cpu.l2cache.overall_misses::total 401 # number of overall misses 1050system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21706000 # number of ReadReq miss cycles 1051system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6539250 # number of ReadReq miss cycles 1052system.cpu.l2cache.ReadReq_miss_latency::total 28245250 # number of ReadReq miss cycles 1053system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3346500 # number of ReadExReq miss cycles 1054system.cpu.l2cache.ReadExReq_miss_latency::total 3346500 # number of ReadExReq miss cycles 1055system.cpu.l2cache.demand_miss_latency::cpu.inst 21706000 # number of demand (read+write) miss cycles 1056system.cpu.l2cache.demand_miss_latency::cpu.data 9885750 # number of demand (read+write) miss cycles 1057system.cpu.l2cache.demand_miss_latency::total 31591750 # number of demand (read+write) miss cycles 1058system.cpu.l2cache.overall_miss_latency::cpu.inst 21706000 # number of overall miss cycles 1059system.cpu.l2cache.overall_miss_latency::cpu.data 9885750 # number of overall miss cycles 1060system.cpu.l2cache.overall_miss_latency::total 31591750 # number of overall miss cycles 1061system.cpu.l2cache.ReadReq_accesses::cpu.inst 293 # number of ReadReq accesses(hits+misses) 1062system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 1063system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) 1064system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 1065system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 1066system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses 1067system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 1068system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses 1069system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses 1070system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 1071system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses 1072system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.941980 # miss rate for ReadReq accesses 1073system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.790476 # miss rate for ReadReq accesses 1074system.cpu.l2cache.ReadReq_miss_rate::total 0.902010 # miss rate for ReadReq accesses 1075system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1076system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1077system.cpu.l2cache.demand_miss_rate::cpu.inst 0.941980 # miss rate for demand accesses 1078system.cpu.l2cache.demand_miss_rate::cpu.data 0.850340 # miss rate for demand accesses 1079system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses 1080system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941980 # miss rate for overall accesses 1081system.cpu.l2cache.overall_miss_rate::cpu.data 0.850340 # miss rate for overall accesses 1082system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses 1083system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78644.927536 # average ReadReq miss latency 1084system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78786.144578 # average ReadReq miss latency 1085system.cpu.l2cache.ReadReq_avg_miss_latency::total 78677.576602 # average ReadReq miss latency 1086system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency 1087system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency 1088system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency 1089system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79086 # average overall miss latency 1090system.cpu.l2cache.demand_avg_miss_latency::total 78782.418953 # average overall miss latency 1091system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency 1092system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79086 # average overall miss latency 1093system.cpu.l2cache.overall_avg_miss_latency::total 78782.418953 # average overall miss latency 1094system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1095system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1096system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1097system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1098system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1099system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1100system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1101system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1102system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 1103system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 1104system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1105system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 1106system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 1107system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 1108system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 1109system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses 1110system.cpu.l2cache.ReadReq_mshr_misses::total 354 # number of ReadReq MSHR misses 1111system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 1112system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 1113system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 1114system.cpu.l2cache.demand_mshr_misses::cpu.data 120 # number of demand (read+write) MSHR misses 1115system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses 1116system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 1117system.cpu.l2cache.overall_mshr_misses::cpu.data 120 # number of overall MSHR misses 1118system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses 1119system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18264000 # number of ReadReq MSHR miss cycles 1120system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5236000 # number of ReadReq MSHR miss cycles 1121system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23500000 # number of ReadReq MSHR miss cycles 1122system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824500 # number of ReadExReq MSHR miss cycles 1123system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824500 # number of ReadExReq MSHR miss cycles 1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18264000 # number of demand (read+write) MSHR miss cycles 1125system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8060500 # number of demand (read+write) MSHR miss cycles 1126system.cpu.l2cache.demand_mshr_miss_latency::total 26324500 # number of demand (read+write) MSHR miss cycles 1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18264000 # number of overall MSHR miss cycles 1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8060500 # number of overall MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::total 26324500 # number of overall MSHR miss cycles 1130system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for ReadReq accesses 1131system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.742857 # mshr miss rate for ReadReq accesses 1132system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889447 # mshr miss rate for ReadReq accesses 1133system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1135system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for demand accesses 1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for demand accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses 1138system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for overall accesses 1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for overall accesses 1140system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses 1141system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66173.913043 # average ReadReq mshr miss latency 1142system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67128.205128 # average ReadReq mshr miss latency 1143system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66384.180791 # average ReadReq mshr miss latency 1144system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67250 # average ReadExReq mshr miss latency 1145system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67250 # average ReadExReq mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency 1147system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency 1148system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency 1152system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1153system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 1157system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1164system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram	12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7680 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25344 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 120 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 396 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1015289114 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 441430049 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1456719163 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1015289114 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1015289114 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1015289114 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 441430049 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1456719163 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 396 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 90 # Per bank write bursts 45system.physmem.perBankRdBursts::1 45 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 43 # Per bank write bursts 48system.physmem.perBankRdBursts::4 18 # Per bank write bursts 49system.physmem.perBankRdBursts::5 32 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 8 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 9 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 17318000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 396 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 410.033898 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 279.539573 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 339.305882 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 9 15.25% 15.25% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 16 27.12% 42.37% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 13.56% 55.93% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 9 15.25% 71.19% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 2 3.39% 74.58% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.39% 77.97% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation 203system.physmem.totQLat 3886750 # Total ticks spent queuing 204system.physmem.totMemAccLat 11311750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 9815.03 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 28565.03 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1456.72 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1456.72 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.38 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 331 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 43732.32 # Average gap between requests 224system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10748205 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 71250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 14332005 # Total energy per rank (pJ) 233system.physmem_0.averagePower 905.226907 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 62750 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 15263500 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 741000 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 465000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 12744465 # Total energy per rank (pJ) 247system.physmem_1.averagePower 804.955945 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 732000 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 14594250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 2567 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1598 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2080 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 778 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 37.403846 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 334 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 270system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 271system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 272system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 273system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 274system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 275system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 276system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 277system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 278system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 279system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 280system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 281system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 282system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 283system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 284system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 285system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 286system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 287system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 288system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 289system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 290system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 291system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 292system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 293system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 296system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 299system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 300system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 301system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 302system.cpu.checker.dtb.read_hits 0 # DTB read hits 303system.cpu.checker.dtb.read_misses 0 # DTB read misses 304system.cpu.checker.dtb.write_hits 0 # DTB write hits 305system.cpu.checker.dtb.write_misses 0 # DTB write misses 306system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 307system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 308system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 309system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 310system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 311system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 312system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 313system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 314system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 315system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 316system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 317system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 318system.cpu.checker.dtb.hits 0 # DTB hits 319system.cpu.checker.dtb.misses 0 # DTB misses 320system.cpu.checker.dtb.accesses 0 # DTB accesses 321system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 322system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 325system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 326system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 327system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 328system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 329system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 330system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 331system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 332system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 333system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 334system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 335system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 336system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 337system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 338system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 339system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 340system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 341system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 342system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 343system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 344system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 345system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 346system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 347system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 348system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 349system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 350system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 351system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 354system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 357system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 358system.cpu.checker.itb.inst_hits 0 # ITB inst hits 359system.cpu.checker.itb.inst_misses 0 # ITB inst misses 360system.cpu.checker.itb.read_hits 0 # DTB read hits 361system.cpu.checker.itb.read_misses 0 # DTB read misses 362system.cpu.checker.itb.write_hits 0 # DTB write hits 363system.cpu.checker.itb.write_misses 0 # DTB write misses 364system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 365system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 366system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 367system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 368system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 369system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 370system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 371system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 372system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.checker.itb.read_accesses 0 # DTB read accesses 374system.cpu.checker.itb.write_accesses 0 # DTB write accesses 375system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.checker.itb.hits 0 # DTB hits 377system.cpu.checker.itb.misses 0 # DTB misses 378system.cpu.checker.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 13 # Number of system calls 380system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 381system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 384system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 391system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 392system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 393system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 394system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 395system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 396system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 397system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 398system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 399system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 402system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 407system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 408system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 409system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 410system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 411system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 412system.cpu.dtb.walker.walks 0 # Table walker walks requested 413system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 420system.cpu.dtb.inst_hits 0 # ITB inst hits 421system.cpu.dtb.inst_misses 0 # ITB inst misses 422system.cpu.dtb.read_hits 0 # DTB read hits 423system.cpu.dtb.read_misses 0 # DTB read misses 424system.cpu.dtb.write_hits 0 # DTB write hits 425system.cpu.dtb.write_misses 0 # DTB write misses 426system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 427system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 428system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 429system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 430system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 431system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 432system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 433system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 435system.cpu.dtb.read_accesses 0 # DTB read accesses 436system.cpu.dtb.write_accesses 0 # DTB write accesses 437system.cpu.dtb.inst_accesses 0 # ITB inst accesses 438system.cpu.dtb.hits 0 # DTB hits 439system.cpu.dtb.misses 0 # DTB misses 440system.cpu.dtb.accesses 0 # DTB accesses 441system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 450system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 451system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 452system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 453system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 454system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 455system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 456system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 457system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 459system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 460system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 461system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 462system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 464system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 465system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 466system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 467system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 468system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 469system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 470system.cpu.itb.walker.walks 0 # Table walker walks requested 471system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 472system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 474system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 475system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 478system.cpu.itb.inst_hits 0 # ITB inst hits 479system.cpu.itb.inst_misses 0 # ITB inst misses 480system.cpu.itb.read_hits 0 # DTB read hits 481system.cpu.itb.read_misses 0 # DTB read misses 482system.cpu.itb.write_hits 0 # DTB write hits 483system.cpu.itb.write_misses 0 # DTB write misses 484system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 485system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 486system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 488system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 489system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 490system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 491system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 493system.cpu.itb.read_accesses 0 # DTB read accesses 494system.cpu.itb.write_accesses 0 # DTB write accesses 495system.cpu.itb.inst_accesses 0 # ITB inst accesses 496system.cpu.itb.hits 0 # DTB hits 497system.cpu.itb.misses 0 # DTB misses 498system.cpu.itb.accesses 0 # DTB accesses 499system.cpu.numCycles 34797 # number of cpu cycles simulated 500system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 501system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 502system.cpu.fetch.icacheStallCycles 7703 # Number of cycles fetch is stalled on an Icache miss 503system.cpu.fetch.Insts 12168 # Number of instructions fetch has processed 504system.cpu.fetch.Branches 2567 # Number of branches that fetch encountered 505system.cpu.fetch.predictedBranches 1112 # Number of branches that fetch has predicted taken 506system.cpu.fetch.Cycles 4777 # Number of cycles fetch has run and was not squashing or blocked 507system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing 508system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 509system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps 510system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 511system.cpu.fetch.CacheLines 2007 # Number of cache lines fetched 512system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed 513system.cpu.fetch.rateDist::samples 13242 # Number of instructions fetched each cycle (Total) 514system.cpu.fetch.rateDist::mean 1.084202 # Number of instructions fetched each cycle (Total) 515system.cpu.fetch.rateDist::stdev 2.460827 # Number of instructions fetched each cycle (Total) 516system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 517system.cpu.fetch.rateDist::0 10620 80.20% 80.20% # Number of instructions fetched each cycle (Total) 518system.cpu.fetch.rateDist::1 274 2.07% 82.27% # Number of instructions fetched each cycle (Total) 519system.cpu.fetch.rateDist::2 209 1.58% 83.85% # Number of instructions fetched each cycle (Total) 520system.cpu.fetch.rateDist::3 222 1.68% 85.52% # Number of instructions fetched each cycle (Total) 521system.cpu.fetch.rateDist::4 233 1.76% 87.28% # Number of instructions fetched each cycle (Total) 522system.cpu.fetch.rateDist::5 323 2.44% 89.72% # Number of instructions fetched each cycle (Total) 523system.cpu.fetch.rateDist::6 137 1.03% 90.76% # Number of instructions fetched each cycle (Total) 524system.cpu.fetch.rateDist::7 162 1.22% 91.98% # Number of instructions fetched each cycle (Total) 525system.cpu.fetch.rateDist::8 1062 8.02% 100.00% # Number of instructions fetched each cycle (Total) 526system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 527system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 528system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 529system.cpu.fetch.rateDist::total 13242 # Number of instructions fetched each cycle (Total) 530system.cpu.fetch.branchRate 0.073771 # Number of branch fetches per cycle 531system.cpu.fetch.rate 0.349685 # Number of inst fetches per cycle 532system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle 533system.cpu.decode.BlockedCycles 4330 # Number of cycles decode is blocked 534system.cpu.decode.RunCycles 2103 # Number of cycles decode is running 535system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking 536system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing 537system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 538system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction 539system.cpu.decode.DecodedInsts 11850 # Number of instructions handled by decode 540system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode 541system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing 542system.cpu.rename.IdleCycles 6554 # Number of cycles rename is idle 543system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking 544system.cpu.rename.serializeStallCycles 2396 # count of cycles rename stalled for serializing inst 545system.cpu.rename.RunCycles 2012 # Number of cycles rename is running 546system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking 547system.cpu.rename.RenamedInsts 11194 # Number of instructions processed by rename 548system.cpu.rename.IQFullEvents 171 # Number of times rename has blocked due to IQ full 549system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full 550system.cpu.rename.SQFullEvents 1066 # Number of times rename has blocked due to SQ full 551system.cpu.rename.RenamedOperands 11323 # Number of destination operands rename has renamed 552system.cpu.rename.RenameLookups 51655 # Number of register rename lookups that rename has made 553system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups 554system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups 555system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 556system.cpu.rename.UndoneMaps 5829 # Number of HB maps that are undone due to squashing 557system.cpu.rename.serializingInsts 42 # count of serializing insts renamed 558system.cpu.rename.tempSerializingInsts 36 # count of temporary serializing insts renamed 559system.cpu.rename.skidInsts 409 # count of insts added to the skid buffer 560system.cpu.memDep0.insertedLoads 2284 # Number of loads inserted to the mem dependence unit. 561system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit. 562system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. 563system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. 564system.cpu.iq.iqInstsAdded 10118 # Number of instructions added to the IQ (excludes non-spec) 565system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ 566system.cpu.iq.iqInstsIssued 8189 # Number of instructions issued 567system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued 568system.cpu.iq.iqSquashedInstsExamined 4786 # Number of squashed instructions iterated over during squash; mainly for profiling 569system.cpu.iq.iqSquashedOperandsExamined 12366 # Number of squashed operands that are examined and possibly removed from graph 570system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed 571system.cpu.iq.issued_per_cycle::samples 13242 # Number of insts issued each cycle 572system.cpu.iq.issued_per_cycle::mean 0.618411 # Number of insts issued each cycle 573system.cpu.iq.issued_per_cycle::stdev 1.365218 # Number of insts issued each cycle 574system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 575system.cpu.iq.issued_per_cycle::0 10034 75.77% 75.77% # Number of insts issued each cycle 576system.cpu.iq.issued_per_cycle::1 1166 8.81% 84.58% # Number of insts issued each cycle 577system.cpu.iq.issued_per_cycle::2 746 5.63% 90.21% # Number of insts issued each cycle 578system.cpu.iq.issued_per_cycle::3 448 3.38% 93.60% # Number of insts issued each cycle 579system.cpu.iq.issued_per_cycle::4 359 2.71% 96.31% # Number of insts issued each cycle 580system.cpu.iq.issued_per_cycle::5 279 2.11% 98.41% # Number of insts issued each cycle 581system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle 582system.cpu.iq.issued_per_cycle::7 62 0.47% 99.87% # Number of insts issued each cycle 583system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle 584system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 585system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 586system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 587system.cpu.iq.issued_per_cycle::total 13242 # Number of insts issued each cycle 588system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 589system.cpu.iq.fu_full::IntAlu 9 5.20% 5.20% # attempts to use FU when none available 590system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available 591system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available 592system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available 593system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available 594system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available 595system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available 596system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available 597system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available 598system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available 599system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available 600system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available 601system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available 602system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available 603system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available 604system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available 605system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available 606system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available 607system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available 608system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available 609system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available 610system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available 611system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available 612system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available 613system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available 614system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available 615system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available 616system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available 617system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available 618system.cpu.iq.fu_full::MemRead 84 48.55% 53.76% # attempts to use FU when none available 619system.cpu.iq.fu_full::MemWrite 80 46.24% 100.00% # attempts to use FU when none available 620system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 621system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 622system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 623system.cpu.iq.FU_type_0::IntAlu 4931 60.21% 60.21% # Type of FU issued 624system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.29% # Type of FU issued 625system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.29% # Type of FU issued 626system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.29% # Type of FU issued 627system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.29% # Type of FU issued 628system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.29% # Type of FU issued 629system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.29% # Type of FU issued 630system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.29% # Type of FU issued 631system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.29% # Type of FU issued 632system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.29% # Type of FU issued 633system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.29% # Type of FU issued 634system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.29% # Type of FU issued 635system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.29% # Type of FU issued 636system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.29% # Type of FU issued 637system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.29% # Type of FU issued 638system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.29% # Type of FU issued 639system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.29% # Type of FU issued 640system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.29% # Type of FU issued 641system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.29% # Type of FU issued 642system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.29% # Type of FU issued 643system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.29% # Type of FU issued 644system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.29% # Type of FU issued 645system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.29% # Type of FU issued 646system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.29% # Type of FU issued 647system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.29% # Type of FU issued 648system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.32% # Type of FU issued 649system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued 650system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.32% # Type of FU issued 651system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued 652system.cpu.iq.FU_type_0::MemRead 1952 23.84% 84.16% # Type of FU issued 653system.cpu.iq.FU_type_0::MemWrite 1297 15.84% 100.00% # Type of FU issued 654system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 655system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 656system.cpu.iq.FU_type_0::total 8189 # Type of FU issued 657system.cpu.iq.rate 0.235336 # Inst issue rate 658system.cpu.iq.fu_busy_cnt 173 # FU busy when requested 659system.cpu.iq.fu_busy_rate 0.021126 # FU busy rate (busy events/executed inst) 660system.cpu.iq.int_inst_queue_reads 29748 # Number of integer instruction queue reads 661system.cpu.iq.int_inst_queue_writes 14841 # Number of integer instruction queue writes 662system.cpu.iq.int_inst_queue_wakeup_accesses 7422 # Number of integer instruction queue wakeup accesses 663system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads 664system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes 665system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses 666system.cpu.iq.int_alu_accesses 8319 # Number of integer alu accesses 667system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 668system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores 669system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 670system.cpu.iew.lsq.thread0.squashedLoads 1257 # Number of loads squashed 671system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 672system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 673system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed 674system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 675system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 676system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled 677system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 678system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 679system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing 680system.cpu.iew.iewBlockCycles 662 # Number of cycles IEW is blocking 681system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking 682system.cpu.iew.iewDispatchedInsts 10173 # Number of instructions dispatched to IQ 683system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch 684system.cpu.iew.iewDispLoadInsts 2284 # Number of dispatched load instructions 685system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions 686system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions 687system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall 688system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall 689system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 690system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly 691system.cpu.iew.predictedNotTakenIncorrect 233 # Number of branches that were predicted not taken incorrectly 692system.cpu.iew.branchMispredicts 344 # Number of branch mispredicts detected at execute 693system.cpu.iew.iewExecutedInsts 7858 # Number of executed instructions 694system.cpu.iew.iewExecLoadInsts 1841 # Number of load instructions executed 695system.cpu.iew.iewExecSquashedInsts 331 # Number of squashed instructions skipped in execute 696system.cpu.iew.exec_swp 0 # number of swp insts executed 697system.cpu.iew.exec_nop 9 # number of nop insts executed 698system.cpu.iew.exec_refs 3070 # number of memory reference insts executed 699system.cpu.iew.exec_branches 1431 # Number of branches executed 700system.cpu.iew.exec_stores 1229 # Number of stores executed 701system.cpu.iew.exec_rate 0.225824 # Inst execution rate 702system.cpu.iew.wb_sent 7567 # cumulative count of insts sent to commit 703system.cpu.iew.wb_count 7454 # cumulative count of insts written-back 704system.cpu.iew.wb_producers 3520 # num instructions producing a value 705system.cpu.iew.wb_consumers 6887 # num instructions consuming a value 706system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 707system.cpu.iew.wb_rate 0.214214 # insts written-back per cycle 708system.cpu.iew.wb_fanout 0.511108 # average fanout of values written-back 709system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 710system.cpu.commit.commitSquashedInsts 4794 # The number of squashed insts skipped by commit 711system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 712system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted 713system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle 714system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle 715system.cpu.commit.committed_per_cycle::stdev 1.280415 # Number of insts commited each cycle 716system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 717system.cpu.commit.committed_per_cycle::0 10350 83.44% 83.44% # Number of insts commited each cycle 718system.cpu.commit.committed_per_cycle::1 890 7.18% 90.62% # Number of insts commited each cycle 719system.cpu.commit.committed_per_cycle::2 420 3.39% 94.00% # Number of insts commited each cycle 720system.cpu.commit.committed_per_cycle::3 213 1.72% 95.72% # Number of insts commited each cycle 721system.cpu.commit.committed_per_cycle::4 118 0.95% 96.67% # Number of insts commited each cycle 722system.cpu.commit.committed_per_cycle::5 211 1.70% 98.37% # Number of insts commited each cycle 723system.cpu.commit.committed_per_cycle::6 49 0.40% 98.77% # Number of insts commited each cycle 724system.cpu.commit.committed_per_cycle::7 36 0.29% 99.06% # Number of insts commited each cycle 725system.cpu.commit.committed_per_cycle::8 117 0.94% 100.00% # Number of insts commited each cycle 726system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 727system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 728system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 729system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle 730system.cpu.commit.committedInsts 4592 # Number of instructions committed 731system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 732system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 733system.cpu.commit.refs 1965 # Number of memory references committed 734system.cpu.commit.loads 1027 # Number of loads committed 735system.cpu.commit.membars 12 # Number of memory barriers committed 736system.cpu.commit.branches 1008 # Number of branches committed 737system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 738system.cpu.commit.int_insts 4624 # Number of committed integer instructions. 739system.cpu.commit.function_calls 82 # Number of function calls committed. 740system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 741system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 742system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 743system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 744system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 745system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 746system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 747system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 748system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 749system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 750system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 751system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 752system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 753system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 754system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 755system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 756system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 757system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 758system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 759system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 760system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 761system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 762system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 763system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 764system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 765system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 766system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 767system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 768system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 769system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 770system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 771system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 772system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 773system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 774system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 775system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 776system.cpu.rob.rob_reads 22302 # The number of ROB reads 777system.cpu.rob.rob_writes 21197 # The number of ROB writes 778system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself 779system.cpu.idleCycles 21555 # Total number of cycles that the CPU has spent unscheduled due to idling 780system.cpu.committedInsts 4592 # Number of Instructions Simulated 781system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 782system.cpu.cpi 7.577744 # CPI: Cycles Per Instruction 783system.cpu.cpi_total 7.577744 # CPI: Total CPI of All Threads 784system.cpu.ipc 0.131965 # IPC: Instructions Per Cycle 785system.cpu.ipc_total 0.131965 # IPC: Total IPC of All Threads 786system.cpu.int_regfile_reads 7744 # number of integer regfile reads 787system.cpu.int_regfile_writes 4257 # number of integer regfile writes 788system.cpu.fp_regfile_reads 32 # number of floating regfile reads 789system.cpu.cc_regfile_reads 28092 # number of cc regfile reads 790system.cpu.cc_regfile_writes 3277 # number of cc regfile writes 791system.cpu.misc_regfile_reads 3176 # number of misc regfile reads 792system.cpu.misc_regfile_writes 24 # number of misc regfile writes 793system.cpu.dcache.tags.replacements 0 # number of replacements 794system.cpu.dcache.tags.tagsinuse 87.050512 # Cycle average of tags in use 795system.cpu.dcache.tags.total_refs 2159 # Total number of references to valid blocks. 796system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 797system.cpu.dcache.tags.avg_refs 14.687075 # Average number of references to valid blocks. 798system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 799system.cpu.dcache.tags.occ_blocks::cpu.data 87.050512 # Average occupied blocks per requestor 800system.cpu.dcache.tags.occ_percent::cpu.data 0.021253 # Average percentage of cache occupancy 801system.cpu.dcache.tags.occ_percent::total 0.021253 # Average percentage of cache occupancy 802system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 803system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 804system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 805system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 806system.cpu.dcache.tags.tag_accesses 5463 # Number of tag accesses 807system.cpu.dcache.tags.data_accesses 5463 # Number of data accesses 808system.cpu.dcache.ReadReq_hits::cpu.data 1539 # number of ReadReq hits 809system.cpu.dcache.ReadReq_hits::total 1539 # number of ReadReq hits 810system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits 811system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits 812system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 813system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 814system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 815system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 816system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits 817system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits 818system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits 819system.cpu.dcache.overall_hits::total 2137 # number of overall hits 820system.cpu.dcache.ReadReq_misses::cpu.data 182 # number of ReadReq misses 821system.cpu.dcache.ReadReq_misses::total 182 # number of ReadReq misses 822system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses 823system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses 824system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 825system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 826system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses 827system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses 828system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses 829system.cpu.dcache.overall_misses::total 497 # number of overall misses 830system.cpu.dcache.ReadReq_miss_latency::cpu.data 10876493 # number of ReadReq miss cycles 831system.cpu.dcache.ReadReq_miss_latency::total 10876493 # number of ReadReq miss cycles 832system.cpu.dcache.WriteReq_miss_latency::cpu.data 22731000 # number of WriteReq miss cycles 833system.cpu.dcache.WriteReq_miss_latency::total 22731000 # number of WriteReq miss cycles 834system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles 835system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles 836system.cpu.dcache.demand_miss_latency::cpu.data 33607493 # number of demand (read+write) miss cycles 837system.cpu.dcache.demand_miss_latency::total 33607493 # number of demand (read+write) miss cycles 838system.cpu.dcache.overall_miss_latency::cpu.data 33607493 # number of overall miss cycles 839system.cpu.dcache.overall_miss_latency::total 33607493 # number of overall miss cycles 840system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) 841system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) 842system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 843system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 844system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 845system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 846system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 847system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 848system.cpu.dcache.demand_accesses::cpu.data 2634 # number of demand (read+write) accesses 849system.cpu.dcache.demand_accesses::total 2634 # number of demand (read+write) accesses 850system.cpu.dcache.overall_accesses::cpu.data 2634 # number of overall (read+write) accesses 851system.cpu.dcache.overall_accesses::total 2634 # number of overall (read+write) accesses 852system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.105752 # miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_miss_rate::total 0.105752 # miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses 856system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 857system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 858system.cpu.dcache.demand_miss_rate::cpu.data 0.188686 # miss rate for demand accesses 859system.cpu.dcache.demand_miss_rate::total 0.188686 # miss rate for demand accesses 860system.cpu.dcache.overall_miss_rate::cpu.data 0.188686 # miss rate for overall accesses 861system.cpu.dcache.overall_miss_rate::total 0.188686 # miss rate for overall accesses 862system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59760.950549 # average ReadReq miss latency 863system.cpu.dcache.ReadReq_avg_miss_latency::total 59760.950549 # average ReadReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72161.904762 # average WriteReq miss latency 865system.cpu.dcache.WriteReq_avg_miss_latency::total 72161.904762 # average WriteReq miss latency 866system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency 867system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 67620.710262 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 67620.710262 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 874system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed 880system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 881system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 882system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits 883system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits 884system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 885system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6879255 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 6879255 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10269755 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 10269755 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10269755 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 10269755 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.061011 # mshr miss rate for ReadReq accesses 907system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.061011 # mshr miss rate for ReadReq accesses 908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 909system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for demand accesses 911system.cpu.dcache.demand_mshr_miss_rate::total 0.055809 # mshr miss rate for demand accesses 912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for overall accesses 913system.cpu.dcache.overall_mshr_miss_rate::total 0.055809 # mshr miss rate for overall accesses 914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65516.714286 # average ReadReq mshr miss latency 915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65516.714286 # average ReadReq mshr miss latency 916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency 917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency 918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency 919system.cpu.dcache.demand_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency 920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency 921system.cpu.dcache.overall_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency 922system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 923system.cpu.icache.tags.replacements 1 # number of replacements 924system.cpu.icache.tags.tagsinuse 149.166565 # Cycle average of tags in use 925system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. 926system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. 927system.cpu.icache.tags.avg_refs 5.505119 # Average number of references to valid blocks. 928system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 929system.cpu.icache.tags.occ_blocks::cpu.inst 149.166565 # Average occupied blocks per requestor 930system.cpu.icache.tags.occ_percent::cpu.inst 0.072835 # Average percentage of cache occupancy 931system.cpu.icache.tags.occ_percent::total 0.072835 # Average percentage of cache occupancy 932system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 933system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 934system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 935system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 936system.cpu.icache.tags.tag_accesses 4307 # Number of tag accesses 937system.cpu.icache.tags.data_accesses 4307 # Number of data accesses 938system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits 939system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits 940system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits 941system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits 942system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits 943system.cpu.icache.overall_hits::total 1613 # number of overall hits 944system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses 945system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses 946system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses 947system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses 948system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses 949system.cpu.icache.overall_misses::total 394 # number of overall misses 950system.cpu.icache.ReadReq_miss_latency::cpu.inst 28003250 # number of ReadReq miss cycles 951system.cpu.icache.ReadReq_miss_latency::total 28003250 # number of ReadReq miss cycles 952system.cpu.icache.demand_miss_latency::cpu.inst 28003250 # number of demand (read+write) miss cycles 953system.cpu.icache.demand_miss_latency::total 28003250 # number of demand (read+write) miss cycles 954system.cpu.icache.overall_miss_latency::cpu.inst 28003250 # number of overall miss cycles 955system.cpu.icache.overall_miss_latency::total 28003250 # number of overall miss cycles 956system.cpu.icache.ReadReq_accesses::cpu.inst 2007 # number of ReadReq accesses(hits+misses) 957system.cpu.icache.ReadReq_accesses::total 2007 # number of ReadReq accesses(hits+misses) 958system.cpu.icache.demand_accesses::cpu.inst 2007 # number of demand (read+write) accesses 959system.cpu.icache.demand_accesses::total 2007 # number of demand (read+write) accesses 960system.cpu.icache.overall_accesses::cpu.inst 2007 # number of overall (read+write) accesses 961system.cpu.icache.overall_accesses::total 2007 # number of overall (read+write) accesses 962system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196313 # miss rate for ReadReq accesses 963system.cpu.icache.ReadReq_miss_rate::total 0.196313 # miss rate for ReadReq accesses 964system.cpu.icache.demand_miss_rate::cpu.inst 0.196313 # miss rate for demand accesses 965system.cpu.icache.demand_miss_rate::total 0.196313 # miss rate for demand accesses 966system.cpu.icache.overall_miss_rate::cpu.inst 0.196313 # miss rate for overall accesses 967system.cpu.icache.overall_miss_rate::total 0.196313 # miss rate for overall accesses 968system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71074.238579 # average ReadReq miss latency 969system.cpu.icache.ReadReq_avg_miss_latency::total 71074.238579 # average ReadReq miss latency 970system.cpu.icache.demand_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency 971system.cpu.icache.demand_avg_miss_latency::total 71074.238579 # average overall miss latency 972system.cpu.icache.overall_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency 973system.cpu.icache.overall_avg_miss_latency::total 71074.238579 # average overall miss latency 974system.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked 975system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 976system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 977system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 978system.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 # average number of cycles each access was blocked 979system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 980system.cpu.icache.fast_writes 0 # number of fast writes performed 981system.cpu.icache.cache_copies 0 # number of cache copies performed 982system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits 983system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits 984system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits 985system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits 986system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits 987system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits 988system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses 989system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses 990system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 991system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses 992system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 993system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses 994system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22179000 # number of ReadReq MSHR miss cycles 995system.cpu.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles 996system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22179000 # number of demand (read+write) MSHR miss cycles 997system.cpu.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles 998system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22179000 # number of overall MSHR miss cycles 999system.cpu.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles 1000system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for ReadReq accesses 1001system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145989 # mshr miss rate for ReadReq accesses 1002system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for demand accesses 1003system.cpu.icache.demand_mshr_miss_rate::total 0.145989 # mshr miss rate for demand accesses 1004system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for overall accesses 1005system.cpu.icache.overall_mshr_miss_rate::total 0.145989 # mshr miss rate for overall accesses 1006system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75696.245734 # average ReadReq mshr miss latency 1007system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75696.245734 # average ReadReq mshr miss latency 1008system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency 1009system.cpu.icache.demand_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency 1010system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency 1011system.cpu.icache.overall_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency 1012system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1013system.cpu.l2cache.tags.replacements 0 # number of replacements 1014system.cpu.l2cache.tags.tagsinuse 186.073007 # Cycle average of tags in use 1015system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 1016system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. 1017system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. 1018system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1019system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.074126 # Average occupied blocks per requestor 1020system.cpu.l2cache.tags.occ_blocks::cpu.data 45.998881 # Average occupied blocks per requestor 1021system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004275 # Average percentage of cache occupancy 1022system.cpu.l2cache.tags.occ_percent::cpu.data 0.001404 # Average percentage of cache occupancy 1023system.cpu.l2cache.tags.occ_percent::total 0.005678 # Average percentage of cache occupancy 1024system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 1025system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 1026system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id 1027system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id 1028system.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses 1029system.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses 1030system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 1031system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits 1032system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 1033system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 1034system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits 1035system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 1036system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 1037system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits 1038system.cpu.l2cache.overall_hits::total 39 # number of overall hits 1039system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses 1040system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses 1041system.cpu.l2cache.ReadReq_misses::total 359 # number of ReadReq misses 1042system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 1043system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 1044system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 1045system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 1046system.cpu.l2cache.demand_misses::total 401 # number of demand (read+write) misses 1047system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 1048system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 1049system.cpu.l2cache.overall_misses::total 401 # number of overall misses 1050system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21706000 # number of ReadReq miss cycles 1051system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6539250 # number of ReadReq miss cycles 1052system.cpu.l2cache.ReadReq_miss_latency::total 28245250 # number of ReadReq miss cycles 1053system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3346500 # number of ReadExReq miss cycles 1054system.cpu.l2cache.ReadExReq_miss_latency::total 3346500 # number of ReadExReq miss cycles 1055system.cpu.l2cache.demand_miss_latency::cpu.inst 21706000 # number of demand (read+write) miss cycles 1056system.cpu.l2cache.demand_miss_latency::cpu.data 9885750 # number of demand (read+write) miss cycles 1057system.cpu.l2cache.demand_miss_latency::total 31591750 # number of demand (read+write) miss cycles 1058system.cpu.l2cache.overall_miss_latency::cpu.inst 21706000 # number of overall miss cycles 1059system.cpu.l2cache.overall_miss_latency::cpu.data 9885750 # number of overall miss cycles 1060system.cpu.l2cache.overall_miss_latency::total 31591750 # number of overall miss cycles 1061system.cpu.l2cache.ReadReq_accesses::cpu.inst 293 # number of ReadReq accesses(hits+misses) 1062system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 1063system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) 1064system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 1065system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 1066system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses 1067system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 1068system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses 1069system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses 1070system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 1071system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses 1072system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.941980 # miss rate for ReadReq accesses 1073system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.790476 # miss rate for ReadReq accesses 1074system.cpu.l2cache.ReadReq_miss_rate::total 0.902010 # miss rate for ReadReq accesses 1075system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1076system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1077system.cpu.l2cache.demand_miss_rate::cpu.inst 0.941980 # miss rate for demand accesses 1078system.cpu.l2cache.demand_miss_rate::cpu.data 0.850340 # miss rate for demand accesses 1079system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses 1080system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941980 # miss rate for overall accesses 1081system.cpu.l2cache.overall_miss_rate::cpu.data 0.850340 # miss rate for overall accesses 1082system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses 1083system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78644.927536 # average ReadReq miss latency 1084system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78786.144578 # average ReadReq miss latency 1085system.cpu.l2cache.ReadReq_avg_miss_latency::total 78677.576602 # average ReadReq miss latency 1086system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency 1087system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency 1088system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency 1089system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79086 # average overall miss latency 1090system.cpu.l2cache.demand_avg_miss_latency::total 78782.418953 # average overall miss latency 1091system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency 1092system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79086 # average overall miss latency 1093system.cpu.l2cache.overall_avg_miss_latency::total 78782.418953 # average overall miss latency 1094system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1095system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1096system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1097system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1098system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1099system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1100system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1101system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1102system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 1103system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 1104system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1105system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 1106system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 1107system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 1108system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 1109system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses 1110system.cpu.l2cache.ReadReq_mshr_misses::total 354 # number of ReadReq MSHR misses 1111system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 1112system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 1113system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 1114system.cpu.l2cache.demand_mshr_misses::cpu.data 120 # number of demand (read+write) MSHR misses 1115system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses 1116system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 1117system.cpu.l2cache.overall_mshr_misses::cpu.data 120 # number of overall MSHR misses 1118system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses 1119system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18264000 # number of ReadReq MSHR miss cycles 1120system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5236000 # number of ReadReq MSHR miss cycles 1121system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23500000 # number of ReadReq MSHR miss cycles 1122system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824500 # number of ReadExReq MSHR miss cycles 1123system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824500 # number of ReadExReq MSHR miss cycles 1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18264000 # number of demand (read+write) MSHR miss cycles 1125system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8060500 # number of demand (read+write) MSHR miss cycles 1126system.cpu.l2cache.demand_mshr_miss_latency::total 26324500 # number of demand (read+write) MSHR miss cycles 1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18264000 # number of overall MSHR miss cycles 1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8060500 # number of overall MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::total 26324500 # number of overall MSHR miss cycles 1130system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for ReadReq accesses 1131system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.742857 # mshr miss rate for ReadReq accesses 1132system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889447 # mshr miss rate for ReadReq accesses 1133system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1135system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for demand accesses 1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for demand accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses 1138system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for overall accesses 1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for overall accesses 1140system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses 1141system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66173.913043 # average ReadReq mshr miss latency 1142system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67128.205128 # average ReadReq mshr miss latency 1143system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66384.180791 # average ReadReq mshr miss latency 1144system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67250 # average ReadExReq mshr miss latency 1145system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67250 # average ReadExReq mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency 1147system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency 1148system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency 1152system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1153system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 1157system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1164system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
1165system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram	1165system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
1166system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram	1166system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1169system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::5 440 100.00% 100.00% # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram	1169system.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1175system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	1171system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1176system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram	1172system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1178system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram 1179system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) 1180system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 1181system.cpu.toL2Bus.respLayer0.occupancy 493000 # Layer occupancy (ticks) 1182system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 1183system.cpu.toL2Bus.respLayer1.occupancy 239245 # Layer occupancy (ticks) 1184system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 1185system.membus.trans_dist::ReadReq 354 # Transaction distribution 1186system.membus.trans_dist::ReadResp 354 # Transaction distribution 1187system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1188system.membus.trans_dist::ReadExResp 42 # Transaction distribution 1189system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) 1190system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) 1191system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) 1192system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) 1193system.membus.snoops 0 # Total snoops (count) 1194system.membus.snoop_fanout::samples 396 # Request fanout histogram 1195system.membus.snoop_fanout::mean 0 # Request fanout histogram 1196system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1197system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1198system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram 1199system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1200system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1201system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1202system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1203system.membus.snoop_fanout::total 396 # Request fanout histogram 1204system.membus.reqLayer0.occupancy 497000 # Layer occupancy (ticks) 1205system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 1206system.membus.respLayer1.occupancy 2092000 # Layer occupancy (ticks) 1207system.membus.respLayer1.utilization 12.0 # Layer utilization (%) 1208 1209---------- End Simulation Statistics ----------	1174system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram 1175system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) 1176system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 1177system.cpu.toL2Bus.respLayer0.occupancy 493000 # Layer occupancy (ticks) 1178system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 1179system.cpu.toL2Bus.respLayer1.occupancy 239245 # Layer occupancy (ticks) 1180system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 1181system.membus.trans_dist::ReadReq 354 # Transaction distribution 1182system.membus.trans_dist::ReadResp 354 # Transaction distribution 1183system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1184system.membus.trans_dist::ReadExResp 42 # Transaction distribution 1185system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) 1186system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) 1187system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) 1188system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) 1189system.membus.snoops 0 # Total snoops (count) 1190system.membus.snoop_fanout::samples 396 # Request fanout histogram 1191system.membus.snoop_fanout::mean 0 # Request fanout histogram 1192system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1193system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1194system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram 1195system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1196system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1197system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1198system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1199system.membus.snoop_fanout::total 396 # Request fanout histogram 1200system.membus.reqLayer0.occupancy 497000 # Layer occupancy (ticks) 1201system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 1202system.membus.respLayer1.occupancy 2092000 # Layer occupancy (ticks) 1203system.membus.respLayer1.utilization 12.0 # Layer utilization (%) 1204 1205---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000017 # Number of seconds simulated
4sim_ticks 17398000 # Number of ticks simulated
5final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 32773 # Simulator instruction rate (inst/s)
8host_op_rate 38377 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 124135140 # Simulator tick rate (ticks/s)
10host_mem_usage 303432 # Number of bytes of host memory used
11host_seconds 0.14 # Real time elapsed on the host

7host_inst_rate 57922 # Simulator instruction rate (inst/s)
8host_op_rate 67825 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 219380871 # Simulator tick rate (ticks/s)
10host_mem_usage 310080 # Number of bytes of host memory used
11host_seconds 0.08 # Real time elapsed on the host

12sim_insts 4592 # Number of instructions simulated
13sim_ops 5378 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7680 # Number of bytes read from this memory
18system.physmem.bytes_read::total 25344 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 120 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 396 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 1015289114 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 441430049 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1456719163 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 1015289114 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 1015289114 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 1015289114 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 441430049 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1456719163 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 396 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 90 # Per bank write bursts
45system.physmem.perBankRdBursts::1 45 # Per bank write bursts
46system.physmem.perBankRdBursts::2 20 # Per bank write bursts
47system.physmem.perBankRdBursts::3 43 # Per bank write bursts
48system.physmem.perBankRdBursts::4 18 # Per bank write bursts
49system.physmem.perBankRdBursts::5 32 # Per bank write bursts
50system.physmem.perBankRdBursts::6 35 # Per bank write bursts
51system.physmem.perBankRdBursts::7 10 # Per bank write bursts
52system.physmem.perBankRdBursts::8 4 # Per bank write bursts
53system.physmem.perBankRdBursts::9 8 # Per bank write bursts
54system.physmem.perBankRdBursts::10 28 # Per bank write bursts
55system.physmem.perBankRdBursts::11 42 # Per bank write bursts
56system.physmem.perBankRdBursts::12 9 # Per bank write bursts
57system.physmem.perBankRdBursts::13 6 # Per bank write bursts
58system.physmem.perBankRdBursts::14 0 # Per bank write bursts
59system.physmem.perBankRdBursts::15 6 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 17318000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 396 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 410.033898 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 279.539573 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 339.305882 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 9 15.25% 15.25% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 16 27.12% 42.37% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 8 13.56% 55.93% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 9 15.25% 71.19% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 2 3.39% 74.58% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 2 3.39% 77.97% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation
203system.physmem.totQLat 3886750 # Total ticks spent queuing
204system.physmem.totMemAccLat 11311750 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 9815.03 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 28565.03 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 1456.72 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 1456.72 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 11.38 # Data bus utilization in percentage
215system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 331 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 43732.32 # Average gap between requests
224system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
230system.physmem_0.actBackEnergy 10748205 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 71250 # Energy for precharge background per rank (pJ)
232system.physmem_0.totalEnergy 14332005 # Total energy per rank (pJ)
233system.physmem_0.averagePower 905.226907 # Core power per rank (mW)
234system.physmem_0.memoryStateTime::IDLE 62750 # Time in different power states
235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237system.physmem_0.memoryStateTime::ACT 15263500 # Time in different power states
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 741000 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 465000 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 12744465 # Total energy per rank (pJ)
247system.physmem_1.averagePower 804.955945 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 732000 # Time in different power states
249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 14594250 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253system.cpu.branchPred.lookups 2567 # Number of BP lookups
254system.cpu.branchPred.condPredicted 1598 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 2080 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 778 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 37.403846 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 334 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
262system.cpu_clk_domain.clock 500 # Clock period in ticks
263system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
264system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
265system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
266system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
267system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
268system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
270system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
271system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
272system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
273system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
274system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
275system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
276system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
277system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
278system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
279system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
280system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
281system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
282system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
283system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
284system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
285system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
286system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
287system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
288system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
289system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
290system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
291system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
292system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested
293system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
294system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
295system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
296system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
297system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
298system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
299system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
300system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
301system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
302system.cpu.checker.dtb.read_hits 0 # DTB read hits
303system.cpu.checker.dtb.read_misses 0 # DTB read misses
304system.cpu.checker.dtb.write_hits 0 # DTB write hits
305system.cpu.checker.dtb.write_misses 0 # DTB write misses
306system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
307system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
308system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
309system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
310system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
311system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
312system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
313system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
314system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
315system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
316system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
317system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
318system.cpu.checker.dtb.hits 0 # DTB hits
319system.cpu.checker.dtb.misses 0 # DTB misses
320system.cpu.checker.dtb.accesses 0 # DTB accesses
321system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
322system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
323system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
324system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
325system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
326system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
327system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
328system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
329system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
330system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
331system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
332system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
333system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
334system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
335system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
336system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
337system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
338system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
339system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
340system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
341system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
342system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
343system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
344system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
345system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
346system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
347system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
348system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
349system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
350system.cpu.checker.itb.walker.walks 0 # Table walker walks requested
351system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
352system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
353system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
354system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
355system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
356system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
357system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
358system.cpu.checker.itb.inst_hits 0 # ITB inst hits
359system.cpu.checker.itb.inst_misses 0 # ITB inst misses
360system.cpu.checker.itb.read_hits 0 # DTB read hits
361system.cpu.checker.itb.read_misses 0 # DTB read misses
362system.cpu.checker.itb.write_hits 0 # DTB write hits
363system.cpu.checker.itb.write_misses 0 # DTB write misses
364system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
365system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
366system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
367system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
368system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB
369system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
370system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
371system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
372system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
373system.cpu.checker.itb.read_accesses 0 # DTB read accesses
374system.cpu.checker.itb.write_accesses 0 # DTB write accesses
375system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
376system.cpu.checker.itb.hits 0 # DTB hits
377system.cpu.checker.itb.misses 0 # DTB misses
378system.cpu.checker.itb.accesses 0 # DTB accesses
379system.cpu.workload.num_syscalls 13 # Number of system calls
380system.cpu.checker.numCycles 5391 # number of cpu cycles simulated
381system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
382system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
383system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
384system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
385system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
386system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
387system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
388system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
389system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
390system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
391system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
392system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
393system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
394system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
395system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
396system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
397system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
398system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
399system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
400system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
401system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
402system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
403system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
404system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
405system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
406system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
407system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
408system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
409system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
410system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
411system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
412system.cpu.dtb.walker.walks 0 # Table walker walks requested
413system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
414system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
415system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
416system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
417system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
418system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
419system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
420system.cpu.dtb.inst_hits 0 # ITB inst hits
421system.cpu.dtb.inst_misses 0 # ITB inst misses
422system.cpu.dtb.read_hits 0 # DTB read hits
423system.cpu.dtb.read_misses 0 # DTB read misses
424system.cpu.dtb.write_hits 0 # DTB write hits
425system.cpu.dtb.write_misses 0 # DTB write misses
426system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
427system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
428system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
429system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
430system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
431system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
432system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
433system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
434system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
435system.cpu.dtb.read_accesses 0 # DTB read accesses
436system.cpu.dtb.write_accesses 0 # DTB write accesses
437system.cpu.dtb.inst_accesses 0 # ITB inst accesses
438system.cpu.dtb.hits 0 # DTB hits
439system.cpu.dtb.misses 0 # DTB misses
440system.cpu.dtb.accesses 0 # DTB accesses
441system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
449system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
450system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
451system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
452system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
453system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
454system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
455system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
456system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
457system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
458system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
459system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
460system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
461system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
462system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
463system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
464system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
465system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
466system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
467system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
468system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
469system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
470system.cpu.itb.walker.walks 0 # Table walker walks requested
471system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
472system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
473system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
474system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
475system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
476system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
477system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
478system.cpu.itb.inst_hits 0 # ITB inst hits
479system.cpu.itb.inst_misses 0 # ITB inst misses
480system.cpu.itb.read_hits 0 # DTB read hits
481system.cpu.itb.read_misses 0 # DTB read misses
482system.cpu.itb.write_hits 0 # DTB write hits
483system.cpu.itb.write_misses 0 # DTB write misses
484system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
485system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
486system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
487system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
488system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
489system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
490system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
491system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
492system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
493system.cpu.itb.read_accesses 0 # DTB read accesses
494system.cpu.itb.write_accesses 0 # DTB write accesses
495system.cpu.itb.inst_accesses 0 # ITB inst accesses
496system.cpu.itb.hits 0 # DTB hits
497system.cpu.itb.misses 0 # DTB misses
498system.cpu.itb.accesses 0 # DTB accesses
499system.cpu.numCycles 34797 # number of cpu cycles simulated
500system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
501system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
502system.cpu.fetch.icacheStallCycles 7703 # Number of cycles fetch is stalled on an Icache miss
503system.cpu.fetch.Insts 12168 # Number of instructions fetch has processed
504system.cpu.fetch.Branches 2567 # Number of branches that fetch encountered
505system.cpu.fetch.predictedBranches 1112 # Number of branches that fetch has predicted taken
506system.cpu.fetch.Cycles 4777 # Number of cycles fetch has run and was not squashing or blocked
507system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing
508system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
509system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps
510system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR
511system.cpu.fetch.CacheLines 2007 # Number of cache lines fetched
512system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed
513system.cpu.fetch.rateDist::samples 13242 # Number of instructions fetched each cycle (Total)
514system.cpu.fetch.rateDist::mean 1.084202 # Number of instructions fetched each cycle (Total)
515system.cpu.fetch.rateDist::stdev 2.460827 # Number of instructions fetched each cycle (Total)
516system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
517system.cpu.fetch.rateDist::0 10620 80.20% 80.20% # Number of instructions fetched each cycle (Total)
518system.cpu.fetch.rateDist::1 274 2.07% 82.27% # Number of instructions fetched each cycle (Total)
519system.cpu.fetch.rateDist::2 209 1.58% 83.85% # Number of instructions fetched each cycle (Total)
520system.cpu.fetch.rateDist::3 222 1.68% 85.52% # Number of instructions fetched each cycle (Total)
521system.cpu.fetch.rateDist::4 233 1.76% 87.28% # Number of instructions fetched each cycle (Total)
522system.cpu.fetch.rateDist::5 323 2.44% 89.72% # Number of instructions fetched each cycle (Total)
523system.cpu.fetch.rateDist::6 137 1.03% 90.76% # Number of instructions fetched each cycle (Total)
524system.cpu.fetch.rateDist::7 162 1.22% 91.98% # Number of instructions fetched each cycle (Total)
525system.cpu.fetch.rateDist::8 1062 8.02% 100.00% # Number of instructions fetched each cycle (Total)
526system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
527system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
528system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
529system.cpu.fetch.rateDist::total 13242 # Number of instructions fetched each cycle (Total)
530system.cpu.fetch.branchRate 0.073771 # Number of branch fetches per cycle
531system.cpu.fetch.rate 0.349685 # Number of inst fetches per cycle
532system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle
533system.cpu.decode.BlockedCycles 4330 # Number of cycles decode is blocked
534system.cpu.decode.RunCycles 2103 # Number of cycles decode is running
535system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking
536system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing
537system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch
538system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
539system.cpu.decode.DecodedInsts 11850 # Number of instructions handled by decode
540system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode
541system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing
542system.cpu.rename.IdleCycles 6554 # Number of cycles rename is idle
543system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking
544system.cpu.rename.serializeStallCycles 2396 # count of cycles rename stalled for serializing inst
545system.cpu.rename.RunCycles 2012 # Number of cycles rename is running
546system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking
547system.cpu.rename.RenamedInsts 11194 # Number of instructions processed by rename
548system.cpu.rename.IQFullEvents 171 # Number of times rename has blocked due to IQ full
549system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full
550system.cpu.rename.SQFullEvents 1066 # Number of times rename has blocked due to SQ full
551system.cpu.rename.RenamedOperands 11323 # Number of destination operands rename has renamed
552system.cpu.rename.RenameLookups 51655 # Number of register rename lookups that rename has made
553system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups
554system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups
555system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
556system.cpu.rename.UndoneMaps 5829 # Number of HB maps that are undone due to squashing
557system.cpu.rename.serializingInsts 42 # count of serializing insts renamed
558system.cpu.rename.tempSerializingInsts 36 # count of temporary serializing insts renamed
559system.cpu.rename.skidInsts 409 # count of insts added to the skid buffer
560system.cpu.memDep0.insertedLoads 2284 # Number of loads inserted to the mem dependence unit.
561system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit.
562system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads.
563system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores.
564system.cpu.iq.iqInstsAdded 10118 # Number of instructions added to the IQ (excludes non-spec)
565system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
566system.cpu.iq.iqInstsIssued 8189 # Number of instructions issued
567system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
568system.cpu.iq.iqSquashedInstsExamined 4786 # Number of squashed instructions iterated over during squash; mainly for profiling
569system.cpu.iq.iqSquashedOperandsExamined 12366 # Number of squashed operands that are examined and possibly removed from graph
570system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
571system.cpu.iq.issued_per_cycle::samples 13242 # Number of insts issued each cycle
572system.cpu.iq.issued_per_cycle::mean 0.618411 # Number of insts issued each cycle
573system.cpu.iq.issued_per_cycle::stdev 1.365218 # Number of insts issued each cycle
574system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
575system.cpu.iq.issued_per_cycle::0 10034 75.77% 75.77% # Number of insts issued each cycle
576system.cpu.iq.issued_per_cycle::1 1166 8.81% 84.58% # Number of insts issued each cycle
577system.cpu.iq.issued_per_cycle::2 746 5.63% 90.21% # Number of insts issued each cycle
578system.cpu.iq.issued_per_cycle::3 448 3.38% 93.60% # Number of insts issued each cycle
579system.cpu.iq.issued_per_cycle::4 359 2.71% 96.31% # Number of insts issued each cycle
580system.cpu.iq.issued_per_cycle::5 279 2.11% 98.41% # Number of insts issued each cycle
581system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle
582system.cpu.iq.issued_per_cycle::7 62 0.47% 99.87% # Number of insts issued each cycle
583system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle
584system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
585system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
586system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
587system.cpu.iq.issued_per_cycle::total 13242 # Number of insts issued each cycle
588system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
589system.cpu.iq.fu_full::IntAlu 9 5.20% 5.20% # attempts to use FU when none available
590system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available
591system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available
592system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available
593system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available
594system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available
595system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available
596system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available
597system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available
598system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available
599system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available
600system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available
601system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available
602system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available
603system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available
604system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available
605system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available
606system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available
607system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available
608system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available
609system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available
610system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available
611system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available
612system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available
613system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available
614system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available
615system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available
616system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available
617system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available
618system.cpu.iq.fu_full::MemRead 84 48.55% 53.76% # attempts to use FU when none available
619system.cpu.iq.fu_full::MemWrite 80 46.24% 100.00% # attempts to use FU when none available
620system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
621system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
622system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
623system.cpu.iq.FU_type_0::IntAlu 4931 60.21% 60.21% # Type of FU issued
624system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.29% # Type of FU issued
625system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.29% # Type of FU issued
626system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.29% # Type of FU issued
627system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.29% # Type of FU issued
628system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.29% # Type of FU issued
629system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.29% # Type of FU issued
630system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.29% # Type of FU issued
631system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.29% # Type of FU issued
632system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.29% # Type of FU issued
633system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.29% # Type of FU issued
634system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.29% # Type of FU issued
635system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.29% # Type of FU issued
636system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.29% # Type of FU issued
637system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.29% # Type of FU issued
638system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.29% # Type of FU issued
639system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.29% # Type of FU issued
640system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.29% # Type of FU issued
641system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.29% # Type of FU issued
642system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.29% # Type of FU issued
643system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.29% # Type of FU issued
644system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.29% # Type of FU issued
645system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.29% # Type of FU issued
646system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.29% # Type of FU issued
647system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.29% # Type of FU issued
648system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.32% # Type of FU issued
649system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued
650system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.32% # Type of FU issued
651system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued
652system.cpu.iq.FU_type_0::MemRead 1952 23.84% 84.16% # Type of FU issued
653system.cpu.iq.FU_type_0::MemWrite 1297 15.84% 100.00% # Type of FU issued
654system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
655system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
656system.cpu.iq.FU_type_0::total 8189 # Type of FU issued
657system.cpu.iq.rate 0.235336 # Inst issue rate
658system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
659system.cpu.iq.fu_busy_rate 0.021126 # FU busy rate (busy events/executed inst)
660system.cpu.iq.int_inst_queue_reads 29748 # Number of integer instruction queue reads
661system.cpu.iq.int_inst_queue_writes 14841 # Number of integer instruction queue writes
662system.cpu.iq.int_inst_queue_wakeup_accesses 7422 # Number of integer instruction queue wakeup accesses
663system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads
664system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes
665system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses
666system.cpu.iq.int_alu_accesses 8319 # Number of integer alu accesses
667system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses
668system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores
669system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
670system.cpu.iew.lsq.thread0.squashedLoads 1257 # Number of loads squashed
671system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
672system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
673system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed
674system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
675system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
676system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled
677system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked
678system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
679system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing
680system.cpu.iew.iewBlockCycles 662 # Number of cycles IEW is blocking
681system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking
682system.cpu.iew.iewDispatchedInsts 10173 # Number of instructions dispatched to IQ
683system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch
684system.cpu.iew.iewDispLoadInsts 2284 # Number of dispatched load instructions
685system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions
686system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
687system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
688system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
689system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
690system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly
691system.cpu.iew.predictedNotTakenIncorrect 233 # Number of branches that were predicted not taken incorrectly
692system.cpu.iew.branchMispredicts 344 # Number of branch mispredicts detected at execute
693system.cpu.iew.iewExecutedInsts 7858 # Number of executed instructions
694system.cpu.iew.iewExecLoadInsts 1841 # Number of load instructions executed
695system.cpu.iew.iewExecSquashedInsts 331 # Number of squashed instructions skipped in execute
696system.cpu.iew.exec_swp 0 # number of swp insts executed
697system.cpu.iew.exec_nop 9 # number of nop insts executed
698system.cpu.iew.exec_refs 3070 # number of memory reference insts executed
699system.cpu.iew.exec_branches 1431 # Number of branches executed
700system.cpu.iew.exec_stores 1229 # Number of stores executed
701system.cpu.iew.exec_rate 0.225824 # Inst execution rate
702system.cpu.iew.wb_sent 7567 # cumulative count of insts sent to commit
703system.cpu.iew.wb_count 7454 # cumulative count of insts written-back
704system.cpu.iew.wb_producers 3520 # num instructions producing a value
705system.cpu.iew.wb_consumers 6887 # num instructions consuming a value
706system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
707system.cpu.iew.wb_rate 0.214214 # insts written-back per cycle
708system.cpu.iew.wb_fanout 0.511108 # average fanout of values written-back
709system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
710system.cpu.commit.commitSquashedInsts 4794 # The number of squashed insts skipped by commit
711system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
712system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted
713system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle
714system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle
715system.cpu.commit.committed_per_cycle::stdev 1.280415 # Number of insts commited each cycle
716system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
717system.cpu.commit.committed_per_cycle::0 10350 83.44% 83.44% # Number of insts commited each cycle
718system.cpu.commit.committed_per_cycle::1 890 7.18% 90.62% # Number of insts commited each cycle
719system.cpu.commit.committed_per_cycle::2 420 3.39% 94.00% # Number of insts commited each cycle
720system.cpu.commit.committed_per_cycle::3 213 1.72% 95.72% # Number of insts commited each cycle
721system.cpu.commit.committed_per_cycle::4 118 0.95% 96.67% # Number of insts commited each cycle
722system.cpu.commit.committed_per_cycle::5 211 1.70% 98.37% # Number of insts commited each cycle
723system.cpu.commit.committed_per_cycle::6 49 0.40% 98.77% # Number of insts commited each cycle
724system.cpu.commit.committed_per_cycle::7 36 0.29% 99.06% # Number of insts commited each cycle
725system.cpu.commit.committed_per_cycle::8 117 0.94% 100.00% # Number of insts commited each cycle
726system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
727system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
728system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
729system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle
730system.cpu.commit.committedInsts 4592 # Number of instructions committed
731system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
732system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
733system.cpu.commit.refs 1965 # Number of memory references committed
734system.cpu.commit.loads 1027 # Number of loads committed
735system.cpu.commit.membars 12 # Number of memory barriers committed
736system.cpu.commit.branches 1008 # Number of branches committed
737system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
738system.cpu.commit.int_insts 4624 # Number of committed integer instructions.
739system.cpu.commit.function_calls 82 # Number of function calls committed.
740system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
741system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction
742system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction
743system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction
744system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction
745system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction
746system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction
747system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction
748system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction
749system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction
750system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction
751system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction
752system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction
753system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction
754system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction
755system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction
756system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction
757system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction
758system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction
759system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction
760system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction
761system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction
762system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction
763system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction
764system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction
765system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction
766system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction
767system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction
768system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
769system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
770system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction
771system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction
772system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
773system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
774system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
775system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
776system.cpu.rob.rob_reads 22302 # The number of ROB reads
777system.cpu.rob.rob_writes 21197 # The number of ROB writes
778system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself
779system.cpu.idleCycles 21555 # Total number of cycles that the CPU has spent unscheduled due to idling
780system.cpu.committedInsts 4592 # Number of Instructions Simulated
781system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
782system.cpu.cpi 7.577744 # CPI: Cycles Per Instruction
783system.cpu.cpi_total 7.577744 # CPI: Total CPI of All Threads
784system.cpu.ipc 0.131965 # IPC: Instructions Per Cycle
785system.cpu.ipc_total 0.131965 # IPC: Total IPC of All Threads
786system.cpu.int_regfile_reads 7744 # number of integer regfile reads
787system.cpu.int_regfile_writes 4257 # number of integer regfile writes
788system.cpu.fp_regfile_reads 32 # number of floating regfile reads
789system.cpu.cc_regfile_reads 28092 # number of cc regfile reads
790system.cpu.cc_regfile_writes 3277 # number of cc regfile writes
791system.cpu.misc_regfile_reads 3176 # number of misc regfile reads
792system.cpu.misc_regfile_writes 24 # number of misc regfile writes
793system.cpu.dcache.tags.replacements 0 # number of replacements
794system.cpu.dcache.tags.tagsinuse 87.050512 # Cycle average of tags in use
795system.cpu.dcache.tags.total_refs 2159 # Total number of references to valid blocks.
796system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
797system.cpu.dcache.tags.avg_refs 14.687075 # Average number of references to valid blocks.
798system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
799system.cpu.dcache.tags.occ_blocks::cpu.data 87.050512 # Average occupied blocks per requestor
800system.cpu.dcache.tags.occ_percent::cpu.data 0.021253 # Average percentage of cache occupancy
801system.cpu.dcache.tags.occ_percent::total 0.021253 # Average percentage of cache occupancy
802system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
803system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
804system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
805system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id
806system.cpu.dcache.tags.tag_accesses 5463 # Number of tag accesses
807system.cpu.dcache.tags.data_accesses 5463 # Number of data accesses
808system.cpu.dcache.ReadReq_hits::cpu.data 1539 # number of ReadReq hits
809system.cpu.dcache.ReadReq_hits::total 1539 # number of ReadReq hits
810system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits
811system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits
812system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
813system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
814system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
815system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
816system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits
817system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits
818system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits
819system.cpu.dcache.overall_hits::total 2137 # number of overall hits
820system.cpu.dcache.ReadReq_misses::cpu.data 182 # number of ReadReq misses
821system.cpu.dcache.ReadReq_misses::total 182 # number of ReadReq misses
822system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses
823system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses
824system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
825system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
826system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses
827system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses
828system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses
829system.cpu.dcache.overall_misses::total 497 # number of overall misses
830system.cpu.dcache.ReadReq_miss_latency::cpu.data 10876493 # number of ReadReq miss cycles
831system.cpu.dcache.ReadReq_miss_latency::total 10876493 # number of ReadReq miss cycles
832system.cpu.dcache.WriteReq_miss_latency::cpu.data 22731000 # number of WriteReq miss cycles
833system.cpu.dcache.WriteReq_miss_latency::total 22731000 # number of WriteReq miss cycles
834system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles
835system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles
836system.cpu.dcache.demand_miss_latency::cpu.data 33607493 # number of demand (read+write) miss cycles
837system.cpu.dcache.demand_miss_latency::total 33607493 # number of demand (read+write) miss cycles
838system.cpu.dcache.overall_miss_latency::cpu.data 33607493 # number of overall miss cycles
839system.cpu.dcache.overall_miss_latency::total 33607493 # number of overall miss cycles
840system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses)
841system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses)
842system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
843system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
844system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
845system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
846system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
847system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
848system.cpu.dcache.demand_accesses::cpu.data 2634 # number of demand (read+write) accesses
849system.cpu.dcache.demand_accesses::total 2634 # number of demand (read+write) accesses
850system.cpu.dcache.overall_accesses::cpu.data 2634 # number of overall (read+write) accesses
851system.cpu.dcache.overall_accesses::total 2634 # number of overall (read+write) accesses
852system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.105752 # miss rate for ReadReq accesses
853system.cpu.dcache.ReadReq_miss_rate::total 0.105752 # miss rate for ReadReq accesses
854system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses
855system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses
856system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
857system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
858system.cpu.dcache.demand_miss_rate::cpu.data 0.188686 # miss rate for demand accesses
859system.cpu.dcache.demand_miss_rate::total 0.188686 # miss rate for demand accesses
860system.cpu.dcache.overall_miss_rate::cpu.data 0.188686 # miss rate for overall accesses
861system.cpu.dcache.overall_miss_rate::total 0.188686 # miss rate for overall accesses
862system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59760.950549 # average ReadReq miss latency
863system.cpu.dcache.ReadReq_avg_miss_latency::total 59760.950549 # average ReadReq miss latency
864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72161.904762 # average WriteReq miss latency
865system.cpu.dcache.WriteReq_avg_miss_latency::total 72161.904762 # average WriteReq miss latency
866system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency
867system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency
868system.cpu.dcache.demand_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency
869system.cpu.dcache.demand_avg_miss_latency::total 67620.710262 # average overall miss latency
870system.cpu.dcache.overall_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency
871system.cpu.dcache.overall_avg_miss_latency::total 67620.710262 # average overall miss latency
872system.cpu.dcache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked
873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
874system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
876system.cpu.dcache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked
877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
878system.cpu.dcache.fast_writes 0 # number of fast writes performed
879system.cpu.dcache.cache_copies 0 # number of cache copies performed
880system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits
881system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
882system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits
883system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits
884system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
885system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
886system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits
887system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits
888system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits
889system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits
890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses
891system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
893system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
894system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
895system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
896system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
897system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6879255 # number of ReadReq MSHR miss cycles
899system.cpu.dcache.ReadReq_mshr_miss_latency::total 6879255 # number of ReadReq MSHR miss cycles
900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles
901system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles
902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10269755 # number of demand (read+write) MSHR miss cycles
903system.cpu.dcache.demand_mshr_miss_latency::total 10269755 # number of demand (read+write) MSHR miss cycles
904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10269755 # number of overall MSHR miss cycles
905system.cpu.dcache.overall_mshr_miss_latency::total 10269755 # number of overall MSHR miss cycles
906system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.061011 # mshr miss rate for ReadReq accesses
907system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.061011 # mshr miss rate for ReadReq accesses
908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
909system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for demand accesses
911system.cpu.dcache.demand_mshr_miss_rate::total 0.055809 # mshr miss rate for demand accesses
912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for overall accesses
913system.cpu.dcache.overall_mshr_miss_rate::total 0.055809 # mshr miss rate for overall accesses
914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65516.714286 # average ReadReq mshr miss latency
915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65516.714286 # average ReadReq mshr miss latency
916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency
917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency
918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency
919system.cpu.dcache.demand_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency
920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency
921system.cpu.dcache.overall_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency
922system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
923system.cpu.icache.tags.replacements 1 # number of replacements
924system.cpu.icache.tags.tagsinuse 149.166565 # Cycle average of tags in use
925system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks.
926system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks.
927system.cpu.icache.tags.avg_refs 5.505119 # Average number of references to valid blocks.
928system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
929system.cpu.icache.tags.occ_blocks::cpu.inst 149.166565 # Average occupied blocks per requestor
930system.cpu.icache.tags.occ_percent::cpu.inst 0.072835 # Average percentage of cache occupancy
931system.cpu.icache.tags.occ_percent::total 0.072835 # Average percentage of cache occupancy
932system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
933system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
934system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
935system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id
936system.cpu.icache.tags.tag_accesses 4307 # Number of tag accesses
937system.cpu.icache.tags.data_accesses 4307 # Number of data accesses
938system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits
939system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits
940system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits
941system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits
942system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits
943system.cpu.icache.overall_hits::total 1613 # number of overall hits
944system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses
945system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses
946system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses
947system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses
948system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses
949system.cpu.icache.overall_misses::total 394 # number of overall misses
950system.cpu.icache.ReadReq_miss_latency::cpu.inst 28003250 # number of ReadReq miss cycles
951system.cpu.icache.ReadReq_miss_latency::total 28003250 # number of ReadReq miss cycles
952system.cpu.icache.demand_miss_latency::cpu.inst 28003250 # number of demand (read+write) miss cycles
953system.cpu.icache.demand_miss_latency::total 28003250 # number of demand (read+write) miss cycles
954system.cpu.icache.overall_miss_latency::cpu.inst 28003250 # number of overall miss cycles
955system.cpu.icache.overall_miss_latency::total 28003250 # number of overall miss cycles
956system.cpu.icache.ReadReq_accesses::cpu.inst 2007 # number of ReadReq accesses(hits+misses)
957system.cpu.icache.ReadReq_accesses::total 2007 # number of ReadReq accesses(hits+misses)
958system.cpu.icache.demand_accesses::cpu.inst 2007 # number of demand (read+write) accesses
959system.cpu.icache.demand_accesses::total 2007 # number of demand (read+write) accesses
960system.cpu.icache.overall_accesses::cpu.inst 2007 # number of overall (read+write) accesses
961system.cpu.icache.overall_accesses::total 2007 # number of overall (read+write) accesses
962system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196313 # miss rate for ReadReq accesses
963system.cpu.icache.ReadReq_miss_rate::total 0.196313 # miss rate for ReadReq accesses
964system.cpu.icache.demand_miss_rate::cpu.inst 0.196313 # miss rate for demand accesses
965system.cpu.icache.demand_miss_rate::total 0.196313 # miss rate for demand accesses
966system.cpu.icache.overall_miss_rate::cpu.inst 0.196313 # miss rate for overall accesses
967system.cpu.icache.overall_miss_rate::total 0.196313 # miss rate for overall accesses
968system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71074.238579 # average ReadReq miss latency
969system.cpu.icache.ReadReq_avg_miss_latency::total 71074.238579 # average ReadReq miss latency
970system.cpu.icache.demand_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency
971system.cpu.icache.demand_avg_miss_latency::total 71074.238579 # average overall miss latency
972system.cpu.icache.overall_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency
973system.cpu.icache.overall_avg_miss_latency::total 71074.238579 # average overall miss latency
974system.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked
975system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
976system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
977system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
978system.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 # average number of cycles each access was blocked
979system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
980system.cpu.icache.fast_writes 0 # number of fast writes performed
981system.cpu.icache.cache_copies 0 # number of cache copies performed
982system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits
983system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
984system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits
985system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits
986system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits
987system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits
988system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses
989system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses
990system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
991system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses
992system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
993system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses
994system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22179000 # number of ReadReq MSHR miss cycles
995system.cpu.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles
996system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22179000 # number of demand (read+write) MSHR miss cycles
997system.cpu.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles
998system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22179000 # number of overall MSHR miss cycles
999system.cpu.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles
1000system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for ReadReq accesses
1001system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145989 # mshr miss rate for ReadReq accesses
1002system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for demand accesses
1003system.cpu.icache.demand_mshr_miss_rate::total 0.145989 # mshr miss rate for demand accesses
1004system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for overall accesses
1005system.cpu.icache.overall_mshr_miss_rate::total 0.145989 # mshr miss rate for overall accesses
1006system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75696.245734 # average ReadReq mshr miss latency
1007system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75696.245734 # average ReadReq mshr miss latency
1008system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency
1009system.cpu.icache.demand_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency
1010system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency
1011system.cpu.icache.overall_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency
1012system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1013system.cpu.l2cache.tags.replacements 0 # number of replacements
1014system.cpu.l2cache.tags.tagsinuse 186.073007 # Cycle average of tags in use
1015system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
1016system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks.
1017system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks.
1018system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1019system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.074126 # Average occupied blocks per requestor
1020system.cpu.l2cache.tags.occ_blocks::cpu.data 45.998881 # Average occupied blocks per requestor
1021system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004275 # Average percentage of cache occupancy
1022system.cpu.l2cache.tags.occ_percent::cpu.data 0.001404 # Average percentage of cache occupancy
1023system.cpu.l2cache.tags.occ_percent::total 0.005678 # Average percentage of cache occupancy
1024system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
1025system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
1026system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
1027system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id
1028system.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses
1029system.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses
1030system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits
1031system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits
1032system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
1033system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
1034system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits
1035system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
1036system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
1037system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits
1038system.cpu.l2cache.overall_hits::total 39 # number of overall hits
1039system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses
1040system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses
1041system.cpu.l2cache.ReadReq_misses::total 359 # number of ReadReq misses
1042system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
1043system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
1044system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
1045system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses
1046system.cpu.l2cache.demand_misses::total 401 # number of demand (read+write) misses
1047system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
1048system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
1049system.cpu.l2cache.overall_misses::total 401 # number of overall misses
1050system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21706000 # number of ReadReq miss cycles
1051system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6539250 # number of ReadReq miss cycles
1052system.cpu.l2cache.ReadReq_miss_latency::total 28245250 # number of ReadReq miss cycles
1053system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3346500 # number of ReadExReq miss cycles
1054system.cpu.l2cache.ReadExReq_miss_latency::total 3346500 # number of ReadExReq miss cycles
1055system.cpu.l2cache.demand_miss_latency::cpu.inst 21706000 # number of demand (read+write) miss cycles
1056system.cpu.l2cache.demand_miss_latency::cpu.data 9885750 # number of demand (read+write) miss cycles
1057system.cpu.l2cache.demand_miss_latency::total 31591750 # number of demand (read+write) miss cycles
1058system.cpu.l2cache.overall_miss_latency::cpu.inst 21706000 # number of overall miss cycles
1059system.cpu.l2cache.overall_miss_latency::cpu.data 9885750 # number of overall miss cycles
1060system.cpu.l2cache.overall_miss_latency::total 31591750 # number of overall miss cycles
1061system.cpu.l2cache.ReadReq_accesses::cpu.inst 293 # number of ReadReq accesses(hits+misses)
1062system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses)
1063system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
1064system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
1065system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
1066system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses
1067system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
1068system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses
1069system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses
1070system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
1071system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses
1072system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.941980 # miss rate for ReadReq accesses
1073system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.790476 # miss rate for ReadReq accesses
1074system.cpu.l2cache.ReadReq_miss_rate::total 0.902010 # miss rate for ReadReq accesses
1075system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
1076system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
1077system.cpu.l2cache.demand_miss_rate::cpu.inst 0.941980 # miss rate for demand accesses
1078system.cpu.l2cache.demand_miss_rate::cpu.data 0.850340 # miss rate for demand accesses
1079system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses
1080system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941980 # miss rate for overall accesses
1081system.cpu.l2cache.overall_miss_rate::cpu.data 0.850340 # miss rate for overall accesses
1082system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses
1083system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78644.927536 # average ReadReq miss latency
1084system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78786.144578 # average ReadReq miss latency
1085system.cpu.l2cache.ReadReq_avg_miss_latency::total 78677.576602 # average ReadReq miss latency
1086system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency
1087system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency
1088system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency
1089system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79086 # average overall miss latency
1090system.cpu.l2cache.demand_avg_miss_latency::total 78782.418953 # average overall miss latency
1091system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency
1092system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79086 # average overall miss latency
1093system.cpu.l2cache.overall_avg_miss_latency::total 78782.418953 # average overall miss latency
1094system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1095system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1096system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1097system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1098system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1099system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1100system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1101system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1102system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
1103system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
1104system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
1105system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
1106system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
1107system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
1108system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses
1109system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses
1110system.cpu.l2cache.ReadReq_mshr_misses::total 354 # number of ReadReq MSHR misses
1111system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
1112system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
1113system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
1114system.cpu.l2cache.demand_mshr_misses::cpu.data 120 # number of demand (read+write) MSHR misses
1115system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses
1116system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
1117system.cpu.l2cache.overall_mshr_misses::cpu.data 120 # number of overall MSHR misses
1118system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses
1119system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18264000 # number of ReadReq MSHR miss cycles
1120system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5236000 # number of ReadReq MSHR miss cycles
1121system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23500000 # number of ReadReq MSHR miss cycles
1122system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824500 # number of ReadExReq MSHR miss cycles
1123system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824500 # number of ReadExReq MSHR miss cycles
1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18264000 # number of demand (read+write) MSHR miss cycles
1125system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8060500 # number of demand (read+write) MSHR miss cycles
1126system.cpu.l2cache.demand_mshr_miss_latency::total 26324500 # number of demand (read+write) MSHR miss cycles
1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18264000 # number of overall MSHR miss cycles
1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8060500 # number of overall MSHR miss cycles
1129system.cpu.l2cache.overall_mshr_miss_latency::total 26324500 # number of overall MSHR miss cycles
1130system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for ReadReq accesses
1131system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.742857 # mshr miss rate for ReadReq accesses
1132system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889447 # mshr miss rate for ReadReq accesses
1133system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
1135system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for demand accesses
1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for demand accesses
1137system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses
1138system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for overall accesses
1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for overall accesses
1140system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses
1141system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66173.913043 # average ReadReq mshr miss latency
1142system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67128.205128 # average ReadReq mshr miss latency
1143system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66384.180791 # average ReadReq mshr miss latency
1144system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67250 # average ReadExReq mshr miss latency
1145system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67250 # average ReadExReq mshr miss latency
1146system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency
1147system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency
1148system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency
1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency
1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency
1151system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency
1152system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1153system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution
1154system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
1155system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
1156system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
1157system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes)
1158system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
1159system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes)
1160system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
1161system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
1162system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
1163system.cpu.toL2Bus.snoops 0 # Total snoops (count)
1164system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram

1165system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram

1165system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram

1166system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
1167system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1168system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1169system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1170system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1171system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1172system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1173system.cpu.toL2Bus.snoop_fanout::5 440 100.00% 100.00% # Request fanout histogram
1174system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram

1169system.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram
1170system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram

1175system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1171system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1176system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1177system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram

1172system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1173system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram