Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt

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stats.txt (10220:9eab5efc02e8)	stats.txt (10229:aae7735450a9)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16955000 # Number of ticks simulated 5final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 43189 # Simulator instruction rate (inst/s) 8host_op_rate 53887 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 159459409 # Simulator tick rate (ticks/s) 10host_mem_usage 309444 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 392 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 392 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 86 # Per bank write bursts 45system.physmem.perBankRdBursts::1 46 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 42 # Per bank write bursts 48system.physmem.perBankRdBursts::4 17 # Per bank write bursts 49system.physmem.perBankRdBursts::5 34 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 7 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 9 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 16897500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 392 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation 203system.physmem.totQLat 3795000 # Total ticks spent queuing 204system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.56 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 326 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 43105.87 # Average gap between requests 224system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15324750 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 1475906812 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 351 # Transaction distribution 232system.membus.trans_dist::ReadResp 350 # Transaction distribution 233system.membus.trans_dist::ReadExReq 41 # Transaction distribution 234system.membus.trans_dist::ReadExResp 41 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 25024 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 241system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 243system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 21.5 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 2481 # Number of BP lookups 247system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 697 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 252system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 255system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 256system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 257system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 258system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 259system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 260system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 261system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 262system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 263system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 264system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 265system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 266system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 267system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 268system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 269system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 270system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 271system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 272system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 273system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 274system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 275system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 276system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 277system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 278system.cpu.checker.dtb.read_hits 0 # DTB read hits 279system.cpu.checker.dtb.read_misses 0 # DTB read misses 280system.cpu.checker.dtb.write_hits 0 # DTB write hits 281system.cpu.checker.dtb.write_misses 0 # DTB write misses 282system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 283system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 284system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 285system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 286system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 287system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 288system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 289system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 290system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 291system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 292system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 293system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 294system.cpu.checker.dtb.hits 0 # DTB hits 295system.cpu.checker.dtb.misses 0 # DTB misses 296system.cpu.checker.dtb.accesses 0 # DTB accesses 297system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 298system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 299system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 300system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 301system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 302system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 303system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 304system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 305system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 306system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 307system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 308system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 309system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 310system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 311system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 312system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 313system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 314system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 315system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 316system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 317system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 318system.cpu.checker.itb.inst_hits 0 # ITB inst hits 319system.cpu.checker.itb.inst_misses 0 # ITB inst misses 320system.cpu.checker.itb.read_hits 0 # DTB read hits 321system.cpu.checker.itb.read_misses 0 # DTB read misses 322system.cpu.checker.itb.write_hits 0 # DTB write hits 323system.cpu.checker.itb.write_misses 0 # DTB write misses 324system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 325system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 326system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 327system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 328system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 329system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 330system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 331system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.checker.itb.read_accesses 0 # DTB read accesses 334system.cpu.checker.itb.write_accesses 0 # DTB write accesses 335system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 336system.cpu.checker.itb.hits 0 # DTB hits 337system.cpu.checker.itb.misses 0 # DTB misses 338system.cpu.checker.itb.accesses 0 # DTB accesses 339system.cpu.workload.num_syscalls 13 # Number of system calls 340system.cpu.checker.numCycles 5742 # number of cpu cycles simulated 341system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 342system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 343system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 344system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 345system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 346system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 347system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 348system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 349system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 350system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 351system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 352system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 353system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 354system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 355system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 356system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 357system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 358system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 359system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 360system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 361system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 362system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 363system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 364system.cpu.dtb.inst_hits 0 # ITB inst hits 365system.cpu.dtb.inst_misses 0 # ITB inst misses 366system.cpu.dtb.read_hits 0 # DTB read hits 367system.cpu.dtb.read_misses 0 # DTB read misses 368system.cpu.dtb.write_hits 0 # DTB write hits 369system.cpu.dtb.write_misses 0 # DTB write misses 370system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 371system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 372system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 373system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 374system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 375system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 376system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 377system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 378system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 379system.cpu.dtb.read_accesses 0 # DTB read accesses 380system.cpu.dtb.write_accesses 0 # DTB write accesses 381system.cpu.dtb.inst_accesses 0 # ITB inst accesses 382system.cpu.dtb.hits 0 # DTB hits 383system.cpu.dtb.misses 0 # DTB misses 384system.cpu.dtb.accesses 0 # DTB accesses 385system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 386system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 387system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 388system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 389system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 390system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 391system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 392system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 393system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 394system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 395system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 396system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 397system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 398system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 399system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 401system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 402system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 403system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 404system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 405system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 406system.cpu.itb.inst_hits 0 # ITB inst hits 407system.cpu.itb.inst_misses 0 # ITB inst misses 408system.cpu.itb.read_hits 0 # DTB read hits 409system.cpu.itb.read_misses 0 # DTB read misses 410system.cpu.itb.write_hits 0 # DTB write hits 411system.cpu.itb.write_misses 0 # DTB write misses 412system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 413system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 414system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 415system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 416system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 417system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 418system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 419system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 420system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 421system.cpu.itb.read_accesses 0 # DTB read accesses 422system.cpu.itb.write_accesses 0 # DTB write accesses 423system.cpu.itb.inst_accesses 0 # ITB inst accesses 424system.cpu.itb.hits 0 # DTB hits 425system.cpu.itb.misses 0 # DTB misses 426system.cpu.itb.accesses 0 # DTB accesses 427system.cpu.numCycles 33911 # number of cpu cycles simulated 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 430system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss 431system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed 432system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered 433system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 434system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked 435system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 436system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked 437system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 438system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 439system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle 457system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle 458system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle 459system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked 460system.cpu.decode.RunCycles 2426 # Number of cycles decode is running 461system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 462system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 463system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 464system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 465system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode 466system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 467system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 468system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle 469system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking 470system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst 471system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 472system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 473system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 474system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 475system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 476system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 477system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed 478system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made 479system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 480system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 481system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 482system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 483system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 484system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 485system.cpu.rename.skidInsts 666 # count of insts added to the skid buffer 486system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 487system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 488system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 489system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 490system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 491system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 492system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 493system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 494system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling 495system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph 496system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 497system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle 514system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 515system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available 516system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available 517system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 544system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available 545system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available 546system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 547system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 548system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 549system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued 550system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued 551system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued 552system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 578system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued 579system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued 580system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 581system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 582system.cpu.iq.FU_type_0::total 8921 # Type of FU issued 583system.cpu.iq.rate 0.263071 # Inst issue rate 584system.cpu.iq.fu_busy_cnt 224 # FU busy when requested 585system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) 586system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads 587system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes 588system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses 589system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 590system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 591system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 592system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses 593system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 594system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 595system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 596system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed 597system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 598system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 599system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed 600system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 601system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 602system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 603system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 604system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 605system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 606system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 607system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 608system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ 609system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch 610system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 611system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions 612system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 613system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 614system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 615system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 616system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 617system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 618system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 619system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions 620system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed 621system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute 622system.cpu.iew.exec_swp 0 # number of swp insts executed 623system.cpu.iew.exec_nop 0 # number of nop insts executed 624system.cpu.iew.exec_refs 3300 # number of memory reference insts executed 625system.cpu.iew.exec_branches 1437 # Number of branches executed 626system.cpu.iew.exec_stores 1160 # Number of stores executed 627system.cpu.iew.exec_rate 0.251364 # Inst execution rate 628system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit 629system.cpu.iew.wb_count 8068 # cumulative count of insts written-back 630system.cpu.iew.wb_producers 3883 # num instructions producing a value 631system.cpu.iew.wb_consumers 7789 # num instructions consuming a value 632system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 633system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle 634system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back 635system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 636system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit 637system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 638system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 639system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle 656system.cpu.commit.committedInsts 4591 # Number of instructions committed 657system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 658system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 659system.cpu.commit.refs 2138 # Number of memory references committed 660system.cpu.commit.loads 1200 # Number of loads committed 661system.cpu.commit.membars 12 # Number of memory barriers committed 662system.cpu.commit.branches 1007 # Number of branches committed 663system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 664system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 665system.cpu.commit.function_calls 82 # Number of function calls committed. 666system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 667system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction 668system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction 669system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction 670system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction 671system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction 696system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction 697system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction 698system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 699system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 700system.cpu.commit.op_class_0::total 5729 # Class of committed instruction 701system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 702system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 703system.cpu.rob.rob_reads 23248 # The number of ROB reads 704system.cpu.rob.rob_writes 23415 # The number of ROB writes 705system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself 706system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling 707system.cpu.committedInsts 4591 # Number of Instructions Simulated 708system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16955000 # Number of ticks simulated 5final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 43189 # Simulator instruction rate (inst/s) 8host_op_rate 53887 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 159459409 # Simulator tick rate (ticks/s) 10host_mem_usage 309444 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 392 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 392 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 86 # Per bank write bursts 45system.physmem.perBankRdBursts::1 46 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 42 # Per bank write bursts 48system.physmem.perBankRdBursts::4 17 # Per bank write bursts 49system.physmem.perBankRdBursts::5 34 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 7 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 9 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 16897500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 392 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation 203system.physmem.totQLat 3795000 # Total ticks spent queuing 204system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.56 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 326 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 43105.87 # Average gap between requests 224system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15324750 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 1475906812 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 351 # Transaction distribution 232system.membus.trans_dist::ReadResp 350 # Transaction distribution 233system.membus.trans_dist::ReadExReq 41 # Transaction distribution 234system.membus.trans_dist::ReadExResp 41 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 25024 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 241system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 243system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 21.5 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 2481 # Number of BP lookups 247system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 697 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 252system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 255system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 256system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 257system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 258system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 259system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 260system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 261system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 262system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 263system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 264system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 265system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 266system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 267system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 268system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 269system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 270system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 271system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 272system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 273system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 274system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 275system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 276system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 277system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 278system.cpu.checker.dtb.read_hits 0 # DTB read hits 279system.cpu.checker.dtb.read_misses 0 # DTB read misses 280system.cpu.checker.dtb.write_hits 0 # DTB write hits 281system.cpu.checker.dtb.write_misses 0 # DTB write misses 282system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 283system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 284system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 285system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 286system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 287system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 288system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 289system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 290system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 291system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 292system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 293system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 294system.cpu.checker.dtb.hits 0 # DTB hits 295system.cpu.checker.dtb.misses 0 # DTB misses 296system.cpu.checker.dtb.accesses 0 # DTB accesses 297system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 298system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 299system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 300system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 301system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 302system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 303system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 304system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 305system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 306system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 307system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 308system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 309system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 310system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 311system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 312system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 313system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 314system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 315system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 316system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 317system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 318system.cpu.checker.itb.inst_hits 0 # ITB inst hits 319system.cpu.checker.itb.inst_misses 0 # ITB inst misses 320system.cpu.checker.itb.read_hits 0 # DTB read hits 321system.cpu.checker.itb.read_misses 0 # DTB read misses 322system.cpu.checker.itb.write_hits 0 # DTB write hits 323system.cpu.checker.itb.write_misses 0 # DTB write misses 324system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 325system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 326system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 327system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 328system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 329system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 330system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 331system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.checker.itb.read_accesses 0 # DTB read accesses 334system.cpu.checker.itb.write_accesses 0 # DTB write accesses 335system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 336system.cpu.checker.itb.hits 0 # DTB hits 337system.cpu.checker.itb.misses 0 # DTB misses 338system.cpu.checker.itb.accesses 0 # DTB accesses 339system.cpu.workload.num_syscalls 13 # Number of system calls 340system.cpu.checker.numCycles 5742 # number of cpu cycles simulated 341system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 342system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 343system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 344system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 345system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 346system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 347system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 348system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 349system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 350system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 351system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 352system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 353system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 354system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 355system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 356system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 357system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 358system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 359system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 360system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 361system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 362system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 363system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 364system.cpu.dtb.inst_hits 0 # ITB inst hits 365system.cpu.dtb.inst_misses 0 # ITB inst misses 366system.cpu.dtb.read_hits 0 # DTB read hits 367system.cpu.dtb.read_misses 0 # DTB read misses 368system.cpu.dtb.write_hits 0 # DTB write hits 369system.cpu.dtb.write_misses 0 # DTB write misses 370system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 371system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 372system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 373system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 374system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 375system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 376system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 377system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 378system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 379system.cpu.dtb.read_accesses 0 # DTB read accesses 380system.cpu.dtb.write_accesses 0 # DTB write accesses 381system.cpu.dtb.inst_accesses 0 # ITB inst accesses 382system.cpu.dtb.hits 0 # DTB hits 383system.cpu.dtb.misses 0 # DTB misses 384system.cpu.dtb.accesses 0 # DTB accesses 385system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 386system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 387system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 388system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 389system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 390system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 391system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 392system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 393system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 394system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 395system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 396system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 397system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 398system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 399system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 401system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 402system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 403system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 404system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 405system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 406system.cpu.itb.inst_hits 0 # ITB inst hits 407system.cpu.itb.inst_misses 0 # ITB inst misses 408system.cpu.itb.read_hits 0 # DTB read hits 409system.cpu.itb.read_misses 0 # DTB read misses 410system.cpu.itb.write_hits 0 # DTB write hits 411system.cpu.itb.write_misses 0 # DTB write misses 412system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 413system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 414system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 415system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 416system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 417system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 418system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 419system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 420system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 421system.cpu.itb.read_accesses 0 # DTB read accesses 422system.cpu.itb.write_accesses 0 # DTB write accesses 423system.cpu.itb.inst_accesses 0 # ITB inst accesses 424system.cpu.itb.hits 0 # DTB hits 425system.cpu.itb.misses 0 # DTB misses 426system.cpu.itb.accesses 0 # DTB accesses 427system.cpu.numCycles 33911 # number of cpu cycles simulated 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 430system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss 431system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed 432system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered 433system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 434system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked 435system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 436system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked 437system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 438system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 439system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle 457system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle 458system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle 459system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked 460system.cpu.decode.RunCycles 2426 # Number of cycles decode is running 461system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 462system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 463system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 464system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 465system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode 466system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 467system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 468system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle 469system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking 470system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst 471system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 472system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 473system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 474system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 475system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 476system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 477system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed 478system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made 479system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 480system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 481system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 482system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 483system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 484system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 485system.cpu.rename.skidInsts 666 # count of insts added to the skid buffer 486system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 487system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 488system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 489system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 490system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 491system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 492system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 493system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 494system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling 495system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph 496system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 497system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle 514system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 515system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available 516system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available 517system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 544system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available 545system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available 546system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 547system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 548system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 549system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued 550system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued 551system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued 552system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 578system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued 579system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued 580system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 581system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 582system.cpu.iq.FU_type_0::total 8921 # Type of FU issued 583system.cpu.iq.rate 0.263071 # Inst issue rate 584system.cpu.iq.fu_busy_cnt 224 # FU busy when requested 585system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) 586system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads 587system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes 588system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses 589system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 590system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 591system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 592system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses 593system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 594system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 595system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 596system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed 597system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 598system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 599system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed 600system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 601system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 602system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 603system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 604system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 605system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 606system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 607system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 608system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ 609system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch 610system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 611system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions 612system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 613system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 614system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 615system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 616system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 617system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 618system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 619system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions 620system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed 621system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute 622system.cpu.iew.exec_swp 0 # number of swp insts executed 623system.cpu.iew.exec_nop 0 # number of nop insts executed 624system.cpu.iew.exec_refs 3300 # number of memory reference insts executed 625system.cpu.iew.exec_branches 1437 # Number of branches executed 626system.cpu.iew.exec_stores 1160 # Number of stores executed 627system.cpu.iew.exec_rate 0.251364 # Inst execution rate 628system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit 629system.cpu.iew.wb_count 8068 # cumulative count of insts written-back 630system.cpu.iew.wb_producers 3883 # num instructions producing a value 631system.cpu.iew.wb_consumers 7789 # num instructions consuming a value 632system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 633system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle 634system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back 635system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 636system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit 637system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 638system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 639system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle 656system.cpu.commit.committedInsts 4591 # Number of instructions committed 657system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 658system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 659system.cpu.commit.refs 2138 # Number of memory references committed 660system.cpu.commit.loads 1200 # Number of loads committed 661system.cpu.commit.membars 12 # Number of memory barriers committed 662system.cpu.commit.branches 1007 # Number of branches committed 663system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 664system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 665system.cpu.commit.function_calls 82 # Number of function calls committed. 666system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 667system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction 668system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction 669system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction 670system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction 671system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction 696system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction 697system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction 698system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 699system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 700system.cpu.commit.op_class_0::total 5729 # Class of committed instruction 701system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 702system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 703system.cpu.rob.rob_reads 23248 # The number of ROB reads 704system.cpu.rob.rob_writes 23415 # The number of ROB writes 705system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself 706system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling 707system.cpu.committedInsts 4591 # Number of Instructions Simulated 708system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
709system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
710system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction 711system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads 712system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle 713system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads 714system.cpu.int_regfile_reads 39214 # number of integer regfile reads 715system.cpu.int_regfile_writes 7985 # number of integer regfile writes 716system.cpu.fp_regfile_reads 16 # number of floating regfile reads 717system.cpu.misc_regfile_reads 3239 # number of misc regfile reads 718system.cpu.misc_regfile_writes 24 # number of misc regfile writes 719system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) 720system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 721system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 722system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 723system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 724system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 725system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 726system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) 727system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) 728system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 729system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) 730system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) 731system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 732system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 733system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 734system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) 735system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 736system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) 737system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 738system.cpu.icache.tags.replacements 4 # number of replacements 739system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use 740system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. 741system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 742system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. 743system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 744system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor 745system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy 746system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy 747system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id 748system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 749system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 750system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id 751system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses 752system.cpu.icache.tags.data_accesses 4184 # Number of data accesses 753system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits 754system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits 755system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits 756system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits 757system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits 758system.cpu.icache.overall_hits::total 1584 # number of overall hits 759system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses 760system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses 761system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 762system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses 763system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses 764system.cpu.icache.overall_misses::total 363 # number of overall misses 765system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles 766system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles 767system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles 768system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles 769system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles 770system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles 771system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 772system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 773system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 774system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 775system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 776system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 777system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses 778system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses 779system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses 780system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses 781system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses 782system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses 783system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency 784system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency 785system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency 786system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency 787system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency 788system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency 789system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked 790system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 791system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 792system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 793system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 794system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 795system.cpu.icache.fast_writes 0 # number of fast writes performed 796system.cpu.icache.cache_copies 0 # number of cache copies performed 797system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 798system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 799system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 800system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 801system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 802system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 803system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 804system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 805system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 806system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 807system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 808system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 809system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles 810system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles 811system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles 812system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles 813system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles 814system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles 815system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses 816system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses 817system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses 818system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses 819system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses 820system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses 821system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency 822system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency 823system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency 824system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency 825system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency 826system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency 827system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 828system.cpu.l2cache.tags.replacements 0 # number of replacements 829system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use 830system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 831system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 832system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. 833system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 834system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor 835system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor 836system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy 837system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy 838system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy 839system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 840system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 841system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 842system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id 843system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses 844system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses 845system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 846system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 847system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 848system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 849system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 850system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 851system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 852system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 853system.cpu.l2cache.overall_hits::total 40 # number of overall hits 854system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 855system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 856system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 857system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 858system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 859system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 860system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 861system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 862system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 863system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 864system.cpu.l2cache.overall_misses::total 397 # number of overall misses 865system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles 866system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles 867system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles 868system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles 869system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles 870system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles 873system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles 874system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles 875system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles 876system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) 877system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 878system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) 879system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 880system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 881system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses 882system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 883system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses 884system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses 885system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 886system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses 887system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses 888system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 889system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses 890system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 891system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 892system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses 893system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 894system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses 895system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses 896system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 897system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency 899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency 900system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency 901system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency 902system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency 903system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency 904system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency 905system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency 906system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency 907system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency 908system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency 909system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 910system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 911system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 912system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 913system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 914system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 915system.cpu.l2cache.fast_writes 0 # number of fast writes performed 916system.cpu.l2cache.cache_copies 0 # number of cache copies performed 917system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 918system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 919system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 920system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 921system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 922system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 923system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 924system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 925system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 926system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 927system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 928system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 929system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 930system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 931system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 932system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 933system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 934system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles 935system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles 936system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles 937system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles 938system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles 939system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles 940system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles 941system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles 942system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles 943system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles 944system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles 945system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses 946system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 947system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses 948system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 949system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 950system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses 951system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 952system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses 953system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses 954system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 955system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses 956system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency 957system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency 958system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency 959system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency 960system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency 961system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency 962system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency 963system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency 964system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency 965system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency 966system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency 967system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 968system.cpu.dcache.tags.replacements 0 # number of replacements 969system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use 970system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 971system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 972system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. 973system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 974system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor 975system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy 976system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy 977system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 978system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 979system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 980system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 981system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses 982system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses 983system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 984system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 985system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 986system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 987system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 988system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 989system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 990system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 991system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 992system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 993system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 994system.cpu.dcache.overall_hits::total 2373 # number of overall hits 995system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses 996system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses 997system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 998system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 999system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 1000system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 1001system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 1002system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 1003system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 1004system.cpu.dcache.overall_misses::total 496 # number of overall misses 1005system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles 1006system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles 1007system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles 1008system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles 1009system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 1010system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 1011system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles 1012system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles 1013system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles 1014system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles 1015system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 1016system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 1017system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 1018system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 1019system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 1020system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 1021system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 1022system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 1023system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 1024system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 1025system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 1026system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 1027system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses 1028system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses 1029system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 1030system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 1031system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 1032system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 1033system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 1034system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses 1035system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 1036system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses 1037system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency 1038system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency 1039system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency 1040system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency 1041system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 1042system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 1043system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency 1044system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency 1045system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency 1046system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency 1047system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 1048system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1049system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 1050system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1051system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 1052system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1053system.cpu.dcache.fast_writes 0 # number of fast writes performed 1054system.cpu.dcache.cache_copies 0 # number of cache copies performed 1055system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 1056system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 1057system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 1058system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 1059system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1060system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 1061system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits 1062system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits 1063system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits 1064system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits 1065system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 1066system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 1067system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 1068system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 1069system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 1070system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 1071system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 1072system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 1073system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles 1074system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles 1075system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles 1076system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles 1077system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles 1078system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles 1079system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles 1080system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles 1081system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 1082system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 1083system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 1084system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 1085system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 1086system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 1087system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 1088system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 1089system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency 1090system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency 1091system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency 1092system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency 1093system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency 1094system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency 1095system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency 1096system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency 1097system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1098 1099---------- End Simulation Statistics ----------	709system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction 710system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads 711system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle 712system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads 713system.cpu.int_regfile_reads 39214 # number of integer regfile reads 714system.cpu.int_regfile_writes 7985 # number of integer regfile writes 715system.cpu.fp_regfile_reads 16 # number of floating regfile reads 716system.cpu.misc_regfile_reads 3239 # number of misc regfile reads 717system.cpu.misc_regfile_writes 24 # number of misc regfile writes 718system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) 719system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 720system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 721system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 722system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 723system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 724system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 725system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) 726system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) 727system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 728system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) 729system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) 730system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 731system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 732system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 733system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) 734system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 735system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) 736system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 737system.cpu.icache.tags.replacements 4 # number of replacements 738system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use 739system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. 740system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 741system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. 742system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 743system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor 744system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy 745system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy 746system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id 747system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 748system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 749system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id 750system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses 751system.cpu.icache.tags.data_accesses 4184 # Number of data accesses 752system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits 753system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits 754system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits 755system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits 756system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits 757system.cpu.icache.overall_hits::total 1584 # number of overall hits 758system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses 759system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses 760system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 761system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses 762system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses 763system.cpu.icache.overall_misses::total 363 # number of overall misses 764system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles 765system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles 766system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles 767system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles 768system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles 769system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles 770system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 771system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 772system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 773system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 774system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 775system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 776system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses 777system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses 778system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses 779system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses 780system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses 781system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses 782system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency 783system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency 784system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency 785system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency 786system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency 787system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency 788system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked 789system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 790system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 791system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 792system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 793system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 794system.cpu.icache.fast_writes 0 # number of fast writes performed 795system.cpu.icache.cache_copies 0 # number of cache copies performed 796system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 797system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 798system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 799system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 800system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 801system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 802system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 803system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 804system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 805system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 806system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 807system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 808system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles 809system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles 810system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles 811system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles 812system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles 813system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles 814system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses 815system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses 816system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses 817system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses 818system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses 819system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses 820system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency 821system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency 822system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency 823system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency 824system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency 825system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency 826system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 827system.cpu.l2cache.tags.replacements 0 # number of replacements 828system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use 829system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 830system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 831system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. 832system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 833system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor 834system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor 835system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy 836system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy 837system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy 838system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 839system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 840system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 841system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id 842system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses 843system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses 844system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 845system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 846system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 847system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 848system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 849system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 850system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 851system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 852system.cpu.l2cache.overall_hits::total 40 # number of overall hits 853system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 854system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 855system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 856system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 857system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 858system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 859system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 860system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 861system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 862system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 863system.cpu.l2cache.overall_misses::total 397 # number of overall misses 864system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles 865system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles 866system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles 867system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles 868system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles 869system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles 870system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles 871system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles 872system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles 873system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles 874system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles 875system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) 876system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 877system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) 878system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 879system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 880system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses 881system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 882system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses 883system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses 884system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 885system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses 886system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses 887system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 888system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses 889system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 890system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 891system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses 892system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 893system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses 894system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses 895system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 896system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses 897system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency 899system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency 900system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency 901system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency 902system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency 903system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency 904system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency 905system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency 906system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency 907system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency 908system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 909system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 910system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 911system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 912system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 913system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 914system.cpu.l2cache.fast_writes 0 # number of fast writes performed 915system.cpu.l2cache.cache_copies 0 # number of cache copies performed 916system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 917system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 918system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 919system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 920system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 921system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 922system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 923system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 924system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 925system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 926system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 927system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 928system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 929system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 930system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 931system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 932system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 933system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles 934system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles 935system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles 936system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles 937system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles 938system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles 939system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles 940system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles 941system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles 942system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles 943system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles 944system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses 945system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 946system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses 947system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 948system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 949system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses 950system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 951system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses 952system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses 953system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 954system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses 955system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency 956system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency 957system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency 958system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency 959system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency 960system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency 961system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency 962system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency 963system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency 964system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency 965system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency 966system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 967system.cpu.dcache.tags.replacements 0 # number of replacements 968system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use 969system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 970system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 971system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. 972system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 973system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor 974system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy 975system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy 976system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 977system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 978system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 979system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 980system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses 981system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses 982system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 983system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 984system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 985system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 986system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 987system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 988system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 989system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 990system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 991system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 992system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 993system.cpu.dcache.overall_hits::total 2373 # number of overall hits 994system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses 995system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses 996system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 997system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 998system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 999system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 1000system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 1001system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 1002system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 1003system.cpu.dcache.overall_misses::total 496 # number of overall misses 1004system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles 1005system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles 1006system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles 1007system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles 1008system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 1009system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 1010system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles 1011system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles 1012system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles 1013system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles 1014system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 1015system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 1016system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 1017system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 1018system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 1019system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 1020system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 1021system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 1022system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 1023system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 1024system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 1025system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 1026system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses 1027system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses 1028system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 1029system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 1030system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 1031system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 1032system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 1033system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses 1034system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 1035system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses 1036system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency 1037system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency 1038system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency 1039system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency 1040system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 1041system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 1042system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency 1043system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency 1044system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency 1045system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency 1046system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 1047system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1048system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 1049system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1050system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 1051system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1052system.cpu.dcache.fast_writes 0 # number of fast writes performed 1053system.cpu.dcache.cache_copies 0 # number of cache copies performed 1054system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 1055system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 1056system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 1057system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 1058system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1059system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 1060system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits 1061system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits 1062system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits 1063system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits 1064system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 1065system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 1066system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 1067system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 1068system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 1069system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 1070system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 1071system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 1072system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles 1073system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles 1074system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles 1075system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles 1076system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles 1077system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles 1078system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles 1079system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles 1080system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 1081system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 1082system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 1083system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 1084system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 1085system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 1086system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 1087system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 1088system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency 1089system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency 1090system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency 1091system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency 1092system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency 1093system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency 1094system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency 1095system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency 1096system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1097 1098---------- End Simulation Statistics ----------