1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000010 # Number of seconds simulated
4sim_ticks 10303500 # Number of ticks simulated
5final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 20985 # Simulator instruction rate (inst/s)
8host_op_rate 26178 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 46991642 # Simulator tick rate (ticks/s)
10host_mem_usage 229632 # Number of bytes of host memory used
11host_seconds 0.22 # Real time elapsed on the host
12sim_insts 4600 # Number of instructions simulated
13sim_ops 5739 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 25664 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 401 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
24system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
25system.cpu.checker.dtb.read_hits 0 # DTB read hits
26system.cpu.checker.dtb.read_misses 0 # DTB read misses
27system.cpu.checker.dtb.write_hits 0 # DTB write hits
28system.cpu.checker.dtb.write_misses 0 # DTB write misses
29system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
30system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 374 unchanged lines hidden (view full) ---
405system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles
406system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses)
407system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses)
408system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses
409system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses
410system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses
411system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses
412system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses
413system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses
414system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses
415system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency
416system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
417system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
418system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
419system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
420system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
421system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
422system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
423system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
424system.cpu.icache.fast_writes 0 # number of fast writes performed
425system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
437system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses
438system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles
439system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles
440system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles
441system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles
442system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles
443system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles
444system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses
445system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses
446system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses
447system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency
448system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
449system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
450system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
451system.cpu.dcache.replacements 0 # number of replacements
452system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use
453system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks.
454system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
455system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks.
456system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
457system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
497system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
498system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
499system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
500system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses
501system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses
502system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses
503system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses
504system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses
505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses
506system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
507system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses
508system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses
509system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency
510system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency
511system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency
512system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
513system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
514system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
515system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
516system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
517system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
518system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
519system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
520system.cpu.dcache.fast_writes 0 # number of fast writes performed
521system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 19 unchanged lines hidden (view full) ---
541system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles
542system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles
543system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles
544system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles
545system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles
546system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles
547system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles
548system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses
549system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
550system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses
551system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses
552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency
553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency
554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
555system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
556system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
557system.cpu.l2cache.replacements 0 # number of replacements
558system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use
559system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
560system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
561system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks.
562system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
563system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor
--- 40 unchanged lines hidden (view full) ---
604system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses
605system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses
606system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses
607system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses
608system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses
609system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses
610system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses
611system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses
612system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
613system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses
614system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses
615system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses
616system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses
617system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency
618system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency
619system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency
620system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
621system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
622system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
623system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
624system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
625system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
626system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
627system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
628system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
629system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
630system.cpu.l2cache.fast_writes 0 # number of fast writes performed
631system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 22 unchanged lines hidden (view full) ---
654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles
655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles
656system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles
657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles
658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles
659system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles
660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses
661system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses
662system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
663system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses
664system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses
665system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses
666system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses
667system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency
668system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency
669system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency
670system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
671system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
672system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
673system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
674system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
675
676---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000010 # Number of seconds simulated
4sim_ticks 10303500 # Number of ticks simulated
5final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 20985 # Simulator instruction rate (inst/s)
8host_op_rate 26178 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 46991642 # Simulator tick rate (ticks/s)
10host_mem_usage 229632 # Number of bytes of host memory used
11host_seconds 0.22 # Real time elapsed on the host
12sim_insts 4600 # Number of instructions simulated
13sim_ops 5739 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 25664 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 401 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
24system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
25system.cpu.checker.dtb.read_hits 0 # DTB read hits
26system.cpu.checker.dtb.read_misses 0 # DTB read misses
27system.cpu.checker.dtb.write_hits 0 # DTB write hits
28system.cpu.checker.dtb.write_misses 0 # DTB write misses
29system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
30system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 374 unchanged lines hidden (view full) ---
405system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles
406system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses)
407system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses)
408system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses
409system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses
410system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses
411system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses
412system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses
413system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses
414system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses
415system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency
416system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
417system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
418system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
419system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
420system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
421system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
422system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
423system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
424system.cpu.icache.fast_writes 0 # number of fast writes performed
425system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
437system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses
438system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles
439system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles
440system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles
441system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles
442system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles
443system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles
444system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses
445system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses
446system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses
447system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency
448system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
449system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
450system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
451system.cpu.dcache.replacements 0 # number of replacements
452system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use
453system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks.
454system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
455system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks.
456system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
457system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
497system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
498system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
499system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
500system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses
501system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses
502system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses
503system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses
504system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses
505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses
506system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
507system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses
508system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses
509system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency
510system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency
511system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency
512system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
513system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
514system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
515system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
516system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
517system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
518system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
519system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
520system.cpu.dcache.fast_writes 0 # number of fast writes performed
521system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 19 unchanged lines hidden (view full) ---
541system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles
542system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles
543system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles
544system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles
545system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles
546system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles
547system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles
548system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses
549system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
550system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses
551system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses
552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency
553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency
554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
555system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
556system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
557system.cpu.l2cache.replacements 0 # number of replacements
558system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use
559system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
560system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
561system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks.
562system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
563system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor
--- 40 unchanged lines hidden (view full) ---
604system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses
605system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses
606system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses
607system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses
608system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses
609system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses
610system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses
611system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses
612system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
613system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses
614system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses
615system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses
616system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses
617system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency
618system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency
619system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency
620system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
621system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
622system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
623system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
624system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
625system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
626system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
627system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
628system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
629system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
630system.cpu.l2cache.fast_writes 0 # number of fast writes performed
631system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 22 unchanged lines hidden (view full) ---
654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles
655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles
656system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles
657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles
658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles
659system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles
660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses
661system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses
662system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
663system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses
664system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses
665system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses
666system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses
667system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency
668system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency
669system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency
670system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
671system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
672system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
673system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
674system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
675
676---------- End Simulation Statistics ----------