1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000017 # Number of seconds simulated
4sim_ticks 16981000 # Number of ticks simulated
5final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 35724 # Simulator instruction rate (inst/s)
8host_op_rate 44574 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 132106037 # Simulator tick rate (ticks/s)
10host_mem_usage 247896 # Number of bytes of host memory used
11host_seconds 0.13 # Real time elapsed on the host
12sim_insts 4591 # Number of instructions simulated
13sim_ops 5729 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory

--- 202 unchanged lines hidden (view full) ---

222system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted
223system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
224system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups
225system.cpu.branchPred.BTBHits 697 # Number of BTB hits
226system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
227system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage
228system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target.
229system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
230system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
231system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
232system.cpu.checker.dtb.read_hits 0 # DTB read hits
233system.cpu.checker.dtb.read_misses 0 # DTB read misses
234system.cpu.checker.dtb.write_hits 0 # DTB write hits
235system.cpu.checker.dtb.write_misses 0 # DTB write misses
236system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
237system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

243system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
244system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
245system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
246system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
247system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
248system.cpu.checker.dtb.hits 0 # DTB hits
249system.cpu.checker.dtb.misses 0 # DTB misses
250system.cpu.checker.dtb.accesses 0 # DTB accesses
251system.cpu.checker.itb.inst_hits 0 # ITB inst hits
252system.cpu.checker.itb.inst_misses 0 # ITB inst misses
253system.cpu.checker.itb.read_hits 0 # DTB read hits
254system.cpu.checker.itb.read_misses 0 # DTB read misses
255system.cpu.checker.itb.write_hits 0 # DTB write hits
256system.cpu.checker.itb.write_misses 0 # DTB write misses
257system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
258system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 9 unchanged lines hidden (view full) ---

268system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
269system.cpu.checker.itb.hits 0 # DTB hits
270system.cpu.checker.itb.misses 0 # DTB misses
271system.cpu.checker.itb.accesses 0 # DTB accesses
272system.cpu.workload.num_syscalls 13 # Number of system calls
273system.cpu.checker.numCycles 5742 # number of cpu cycles simulated
274system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
275system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
276system.cpu.dtb.inst_hits 0 # ITB inst hits
277system.cpu.dtb.inst_misses 0 # ITB inst misses
278system.cpu.dtb.read_hits 0 # DTB read hits
279system.cpu.dtb.read_misses 0 # DTB read misses
280system.cpu.dtb.write_hits 0 # DTB write hits
281system.cpu.dtb.write_misses 0 # DTB write misses
282system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
283system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

289system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
290system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
291system.cpu.dtb.read_accesses 0 # DTB read accesses
292system.cpu.dtb.write_accesses 0 # DTB write accesses
293system.cpu.dtb.inst_accesses 0 # ITB inst accesses
294system.cpu.dtb.hits 0 # DTB hits
295system.cpu.dtb.misses 0 # DTB misses
296system.cpu.dtb.accesses 0 # DTB accesses
297system.cpu.itb.inst_hits 0 # ITB inst hits
298system.cpu.itb.inst_misses 0 # ITB inst misses
299system.cpu.itb.read_hits 0 # DTB read hits
300system.cpu.itb.read_misses 0 # DTB read misses
301system.cpu.itb.write_hits 0 # DTB write hits
302system.cpu.itb.write_misses 0 # DTB write misses
303system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
304system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 56 unchanged lines hidden (view full) ---

361system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst
362system.cpu.rename.RunCycles 2227 # Number of cycles rename is running
363system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
364system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename
365system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
366system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
367system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full
368system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed
369system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made
370system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups
371system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups
372system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
373system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing
374system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
375system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
376system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer
377system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit.
378system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit.
379system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
380system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores.
381system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec)
382system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
383system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued
384system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
385system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
386system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph
387system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
388system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle
389system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle
390system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle
391system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
392system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle
393system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle

--- 170 unchanged lines hidden (view full) ---

565system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
566system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction
567system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads
568system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle
569system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads
570system.cpu.int_regfile_reads 39210 # number of integer regfile reads
571system.cpu.int_regfile_writes 7985 # number of integer regfile writes
572system.cpu.fp_regfile_reads 16 # number of floating regfile reads
573system.cpu.misc_regfile_reads 2977 # number of misc regfile reads
574system.cpu.misc_regfile_writes 24 # number of misc regfile writes
575system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s)
576system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution
577system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution
578system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
579system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
580system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes)
581system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)

--- 374 unchanged lines hidden ---