| config.ini (9096:8971a998190a) | config.ini (9265:8fe936e937bd) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a |
| 13clock=1 |
|
| 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= --- 69 unchanged lines hidden (view full) --- 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 | 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= --- 69 unchanged lines hidden (view full) --- 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 |
| 98phase=0 | |
| 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 --- 17 unchanged lines hidden (view full) --- 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.checker] 128type=O3Checker 129children=dtb itb tracer 130checker=Null 131clock=1 | 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 --- 17 unchanged lines hidden (view full) --- 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.checker] 128type=O3Checker 129children=dtb itb tracer 130checker=Null 131clock=1 |
| 132cpu_id=-1 | 132cpu_id=0 |
| 133defer_registration=false 134do_checkpoint_insts=true 135do_quiesce=true 136do_statistics_insts=true 137dtb=system.cpu.checker.dtb 138exitOnError=false 139function_trace=false 140function_trace_start=0 141interrupts=Null 142itb=system.cpu.checker.itb 143max_insts_all_threads=0 144max_insts_any_thread=0 145max_loads_all_threads=0 146max_loads_any_thread=0 147numThreads=1 | 133defer_registration=false 134do_checkpoint_insts=true 135do_quiesce=true 136do_statistics_insts=true 137dtb=system.cpu.checker.dtb 138exitOnError=false 139function_trace=false 140function_trace_start=0 141interrupts=Null 142itb=system.cpu.checker.itb 143max_insts_all_threads=0 144max_insts_any_thread=0 145max_loads_all_threads=0 146max_loads_any_thread=0 147numThreads=1 |
| 148phase=0 | |
| 149profile=0 150progress_interval=0 151system=system 152tracer=system.cpu.checker.tracer 153updateOnError=true 154warnOnlyOnLoadError=true 155workload=system.cpu.workload 156 157[system.cpu.checker.dtb] 158type=ArmTLB 159children=walker 160size=64 161walker=system.cpu.checker.dtb.walker 162 163[system.cpu.checker.dtb.walker] 164type=ArmTableWalker | 148profile=0 149progress_interval=0 150system=system 151tracer=system.cpu.checker.tracer 152updateOnError=true 153warnOnlyOnLoadError=true 154workload=system.cpu.workload 155 156[system.cpu.checker.dtb] 157type=ArmTLB 158children=walker 159size=64 160walker=system.cpu.checker.dtb.walker 161 162[system.cpu.checker.dtb.walker] 163type=ArmTableWalker |
| 165max_backoff=100000 166min_backoff=0 | 164clock=1 165num_squash_per_cycle=2 |
| 167sys=system 168port=system.cpu.toL2Bus.slave[5] 169 170[system.cpu.checker.itb] 171type=ArmTLB 172children=walker 173size=64 174walker=system.cpu.checker.itb.walker 175 176[system.cpu.checker.itb.walker] 177type=ArmTableWalker | 166sys=system 167port=system.cpu.toL2Bus.slave[5] 168 169[system.cpu.checker.itb] 170type=ArmTLB 171children=walker 172size=64 173walker=system.cpu.checker.itb.walker 174 175[system.cpu.checker.itb.walker] 176type=ArmTableWalker |
| 178max_backoff=100000 179min_backoff=0 | 177clock=1 178num_squash_per_cycle=2 |
| 180sys=system 181port=system.cpu.toL2Bus.slave[4] 182 183[system.cpu.checker.tracer] 184type=ExeTracer 185 186[system.cpu.dcache] 187type=BaseCache 188addr_ranges=0:18446744073709551615 189assoc=2 190block_size=64 | 179sys=system 180port=system.cpu.toL2Bus.slave[4] 181 182[system.cpu.checker.tracer] 183type=ExeTracer 184 185[system.cpu.dcache] 186type=BaseCache 187addr_ranges=0:18446744073709551615 188assoc=2 189block_size=64 |
| 190clock=1 |
|
| 191forward_snoops=true 192hash_delay=1 | 191forward_snoops=true 192hash_delay=1 |
| 193hit_latency=1000 |
|
| 193is_top_level=true | 194is_top_level=true |
| 194latency=1000 | |
| 195max_miss_count=0 196mshrs=10 197prefetch_on_access=false 198prefetcher=Null 199prioritizeRequests=false 200repl=Null | 195max_miss_count=0 196mshrs=10 197prefetch_on_access=false 198prefetcher=Null 199prioritizeRequests=false 200repl=Null |
| 201response_latency=1000 |
|
| 201size=262144 202subblock_size=0 203system=system 204tgts_per_mshr=20 205trace_addr=0 206two_queue=false 207write_buffers=8 208cpu_side=system.cpu.dcache_port 209mem_side=system.cpu.toL2Bus.slave[1] 210 211[system.cpu.dtb] 212type=ArmTLB 213children=walker 214size=64 215walker=system.cpu.dtb.walker 216 217[system.cpu.dtb.walker] 218type=ArmTableWalker | 202size=262144 203subblock_size=0 204system=system 205tgts_per_mshr=20 206trace_addr=0 207two_queue=false 208write_buffers=8 209cpu_side=system.cpu.dcache_port 210mem_side=system.cpu.toL2Bus.slave[1] 211 212[system.cpu.dtb] 213type=ArmTLB 214children=walker 215size=64 216walker=system.cpu.dtb.walker 217 218[system.cpu.dtb.walker] 219type=ArmTableWalker |
| 219max_backoff=100000 220min_backoff=0 | 220clock=1 221num_squash_per_cycle=2 |
| 221sys=system 222port=system.cpu.toL2Bus.slave[3] 223 224[system.cpu.fuPool] 225type=FUPool 226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 227FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 228 --- 255 unchanged lines hidden (view full) --- 484opClass=IprAccess 485opLat=3 486 487[system.cpu.icache] 488type=BaseCache 489addr_ranges=0:18446744073709551615 490assoc=2 491block_size=64 | 222sys=system 223port=system.cpu.toL2Bus.slave[3] 224 225[system.cpu.fuPool] 226type=FUPool 227children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 228FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 229 --- 255 unchanged lines hidden (view full) --- 485opClass=IprAccess 486opLat=3 487 488[system.cpu.icache] 489type=BaseCache 490addr_ranges=0:18446744073709551615 491assoc=2 492block_size=64 |
| 493clock=1 |
|
| 492forward_snoops=true 493hash_delay=1 | 494forward_snoops=true 495hash_delay=1 |
| 496hit_latency=1000 |
|
| 494is_top_level=true | 497is_top_level=true |
| 495latency=1000 | |
| 496max_miss_count=0 497mshrs=10 498prefetch_on_access=false 499prefetcher=Null 500prioritizeRequests=false 501repl=Null | 498max_miss_count=0 499mshrs=10 500prefetch_on_access=false 501prefetcher=Null 502prioritizeRequests=false 503repl=Null |
| 504response_latency=1000 |
|
| 502size=131072 503subblock_size=0 504system=system 505tgts_per_mshr=20 506trace_addr=0 507two_queue=false 508write_buffers=8 509cpu_side=system.cpu.icache_port --- 5 unchanged lines hidden (view full) --- 515[system.cpu.itb] 516type=ArmTLB 517children=walker 518size=64 519walker=system.cpu.itb.walker 520 521[system.cpu.itb.walker] 522type=ArmTableWalker | 505size=131072 506subblock_size=0 507system=system 508tgts_per_mshr=20 509trace_addr=0 510two_queue=false 511write_buffers=8 512cpu_side=system.cpu.icache_port --- 5 unchanged lines hidden (view full) --- 518[system.cpu.itb] 519type=ArmTLB 520children=walker 521size=64 522walker=system.cpu.itb.walker 523 524[system.cpu.itb.walker] 525type=ArmTableWalker |
| 523max_backoff=100000 524min_backoff=0 | 526clock=1 527num_squash_per_cycle=2 |
| 525sys=system 526port=system.cpu.toL2Bus.slave[2] 527 528[system.cpu.l2cache] 529type=BaseCache 530addr_ranges=0:18446744073709551615 531assoc=2 532block_size=64 | 528sys=system 529port=system.cpu.toL2Bus.slave[2] 530 531[system.cpu.l2cache] 532type=BaseCache 533addr_ranges=0:18446744073709551615 534assoc=2 535block_size=64 |
| 536clock=1 |
|
| 533forward_snoops=true 534hash_delay=1 | 537forward_snoops=true 538hash_delay=1 |
| 539hit_latency=1000 |
|
| 535is_top_level=false | 540is_top_level=false |
| 536latency=1000 | |
| 537max_miss_count=0 538mshrs=10 539prefetch_on_access=false 540prefetcher=Null 541prioritizeRequests=false 542repl=Null | 541max_miss_count=0 542mshrs=10 543prefetch_on_access=false 544prefetcher=Null 545prioritizeRequests=false 546repl=Null |
| 547response_latency=1000 |
|
| 543size=2097152 544subblock_size=0 545system=system 546tgts_per_mshr=5 547trace_addr=0 548two_queue=false 549write_buffers=8 550cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 566[system.cpu.workload] 567type=LiveProcess 568cmd=hello 569cwd= 570egid=100 571env= 572errout=cerr 573euid=100 | 548size=2097152 549subblock_size=0 550system=system 551tgts_per_mshr=5 552trace_addr=0 553two_queue=false 554write_buffers=8 555cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 571[system.cpu.workload] 572type=LiveProcess 573cmd=hello 574cwd= 575egid=100 576env= 577errout=cerr 578euid=100 |
| 574executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello | 579executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello |
| 575gid=100 576input=cin 577max_stack_size=67108864 578output=cout 579pid=100 580ppid=99 581simpoint=0 582system=system 583uid=100 584 585[system.membus] 586type=CoherentBus 587block_size=64 588clock=1000 589header_cycles=1 590use_default_range=false 591width=8 | 580gid=100 581input=cin 582max_stack_size=67108864 583output=cout 584pid=100 585ppid=99 586simpoint=0 587system=system 588uid=100 589 590[system.membus] 591type=CoherentBus 592block_size=64 593clock=1000 594header_cycles=1 595use_default_range=false 596width=8 |
| 592master=system.physmem.port[0] | 597master=system.physmem.port |
| 593slave=system.system_port system.cpu.l2cache.mem_side 594 595[system.physmem] 596type=SimpleMemory | 598slave=system.system_port system.cpu.l2cache.mem_side 599 600[system.physmem] 601type=SimpleMemory |
| 602bandwidth=73.000000 603clock=1 |
|
| 597conf_table_reported=false | 604conf_table_reported=false |
| 598file= | |
| 599in_addr_map=true 600latency=30000 601latency_var=0 602null=false 603range=0:134217727 604zero=false 605port=system.membus.master[0] 606 | 605in_addr_map=true 606latency=30000 607latency_var=0 608null=false 609range=0:134217727 610zero=false 611port=system.membus.master[0] 612 |