| config.ini (11589:af2f7fef4875) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 338 unchanged lines hidden (view full) --- 347 348[system.cpu.checker.tracer] 349type=ExeTracer 350eventq_index=0 351 352[system.cpu.dcache] 353type=Cache 354children=tags | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 338 unchanged lines hidden (view full) --- 347 348[system.cpu.checker.tracer] 349type=ExeTracer 350eventq_index=0 351 352[system.cpu.dcache] 353type=Cache 354children=tags |
| 355addr_ranges=0:18446744073709551615 | 355addr_ranges=0:18446744073709551615:0:0:0:0 |
| 356assoc=2 357clk_domain=system.cpu_clk_domain 358clusivity=mostly_incl 359default_p_state=UNDEFINED 360demand_mshr_reserve=1 361eventq_index=0 362hit_latency=2 363is_read_only=false --- 387 unchanged lines hidden (view full) --- 751eventq_index=0 752opClass=IprAccess 753opLat=3 754pipelined=false 755 756[system.cpu.icache] 757type=Cache 758children=tags | 356assoc=2 357clk_domain=system.cpu_clk_domain 358clusivity=mostly_incl 359default_p_state=UNDEFINED 360demand_mshr_reserve=1 361eventq_index=0 362hit_latency=2 363is_read_only=false --- 387 unchanged lines hidden (view full) --- 751eventq_index=0 752opClass=IprAccess 753opLat=3 754pipelined=false 755 756[system.cpu.icache] 757type=Cache 758children=tags |
| 759addr_ranges=0:18446744073709551615 | 759addr_ranges=0:18446744073709551615:0:0:0:0 |
| 760assoc=2 761clk_domain=system.cpu_clk_domain 762clusivity=mostly_incl 763default_p_state=UNDEFINED 764demand_mshr_reserve=1 765eventq_index=0 766hit_latency=2 767is_read_only=true --- 115 unchanged lines hidden (view full) --- 883p_state_clk_gate_min=1000 884power_model=Null 885sys=system 886port=system.cpu.toL2Bus.slave[2] 887 888[system.cpu.l2cache] 889type=Cache 890children=tags | 760assoc=2 761clk_domain=system.cpu_clk_domain 762clusivity=mostly_incl 763default_p_state=UNDEFINED 764demand_mshr_reserve=1 765eventq_index=0 766hit_latency=2 767is_read_only=true --- 115 unchanged lines hidden (view full) --- 883p_state_clk_gate_min=1000 884power_model=Null 885sys=system 886port=system.cpu.toL2Bus.slave[2] 887 888[system.cpu.l2cache] 889type=Cache 890children=tags |
| 891addr_ranges=0:18446744073709551615 | 891addr_ranges=0:18446744073709551615:0:0:0:0 |
| 892assoc=8 893clk_domain=system.cpu_clk_domain 894clusivity=mostly_incl 895default_p_state=UNDEFINED 896demand_mshr_reserve=1 897eventq_index=0 898hit_latency=20 899is_read_only=false --- 100 unchanged lines hidden (view full) --- 1000domains= 1001enable=false 1002eventq_index=0 1003sys_clk_domain=system.clk_domain 1004transition_latency=100000000 1005 1006[system.membus] 1007type=CoherentXBar | 892assoc=8 893clk_domain=system.cpu_clk_domain 894clusivity=mostly_incl 895default_p_state=UNDEFINED 896demand_mshr_reserve=1 897eventq_index=0 898hit_latency=20 899is_read_only=false --- 100 unchanged lines hidden (view full) --- 1000domains= 1001enable=false 1002eventq_index=0 1003sys_clk_domain=system.clk_domain 1004transition_latency=100000000 1005 1006[system.membus] 1007type=CoherentXBar |
| 1008children=snoop_filter |
|
| 1008clk_domain=system.clk_domain 1009default_p_state=UNDEFINED 1010eventq_index=0 1011forward_latency=4 1012frontend_latency=3 1013p_state_clk_gate_bins=20 1014p_state_clk_gate_max=1000000000000 1015p_state_clk_gate_min=1000 1016point_of_coherency=true 1017power_model=Null 1018response_latency=2 | 1009clk_domain=system.clk_domain 1010default_p_state=UNDEFINED 1011eventq_index=0 1012forward_latency=4 1013frontend_latency=3 1014p_state_clk_gate_bins=20 1015p_state_clk_gate_max=1000000000000 1016p_state_clk_gate_min=1000 1017point_of_coherency=true 1018power_model=Null 1019response_latency=2 |
| 1019snoop_filter=Null | 1020snoop_filter=system.membus.snoop_filter |
| 1020snoop_response_latency=4 1021system=system 1022use_default_range=false 1023width=16 1024master=system.physmem.port 1025slave=system.system_port system.cpu.l2cache.mem_side 1026 | 1021snoop_response_latency=4 1022system=system 1023use_default_range=false 1024width=16 1025master=system.physmem.port 1026slave=system.system_port system.cpu.l2cache.mem_side 1027 |
| 1028[system.membus.snoop_filter] 1029type=SnoopFilter 1030eventq_index=0 1031lookup_latency=1 1032max_capacity=8388608 1033system=system 1034 |
|
| 1027[system.physmem] 1028type=DRAMCtrl | 1035[system.physmem] 1036type=DRAMCtrl |
| 1029IDD0=0.075000 | 1037IDD0=0.055000 |
| 1030IDD02=0.000000 | 1038IDD02=0.000000 |
| 1031IDD2N=0.050000 | 1039IDD2N=0.032000 |
| 1032IDD2N2=0.000000 1033IDD2P0=0.000000 1034IDD2P02=0.000000 | 1040IDD2N2=0.000000 1041IDD2P0=0.000000 1042IDD2P02=0.000000 |
| 1035IDD2P1=0.000000 | 1043IDD2P1=0.032000 |
| 1036IDD2P12=0.000000 | 1044IDD2P12=0.000000 |
| 1037IDD3N=0.057000 | 1045IDD3N=0.038000 |
| 1038IDD3N2=0.000000 1039IDD3P0=0.000000 1040IDD3P02=0.000000 | 1046IDD3N2=0.000000 1047IDD3P0=0.000000 1048IDD3P02=0.000000 |
| 1041IDD3P1=0.000000 | 1049IDD3P1=0.038000 |
| 1042IDD3P12=0.000000 | 1050IDD3P12=0.000000 |
| 1043IDD4R=0.187000 | 1051IDD4R=0.157000 |
| 1044IDD4R2=0.000000 | 1052IDD4R2=0.000000 |
| 1045IDD4W=0.165000 | 1053IDD4W=0.125000 |
| 1046IDD4W2=0.000000 | 1054IDD4W2=0.000000 |
| 1047IDD5=0.220000 | 1055IDD5=0.235000 |
| 1048IDD52=0.000000 | 1056IDD52=0.000000 |
| 1049IDD6=0.000000 | 1057IDD6=0.020000 |
| 1050IDD62=0.000000 1051VDD=1.500000 1052VDD2=0.000000 1053activation_limit=4 1054addr_mapping=RoRaBaCoCh 1055bank_groups_per_rank=0 1056banks_per_rank=8 1057burst_length=8 1058channels=1 1059clk_domain=system.clk_domain 1060conf_table_reported=true 1061default_p_state=UNDEFINED 1062device_bus_width=8 1063device_rowbuffer_size=1024 1064device_size=536870912 1065devices_per_rank=8 1066dll=true 1067eventq_index=0 1068in_addr_map=true | 1058IDD62=0.000000 1059VDD=1.500000 1060VDD2=0.000000 1061activation_limit=4 1062addr_mapping=RoRaBaCoCh 1063bank_groups_per_rank=0 1064banks_per_rank=8 1065burst_length=8 1066channels=1 1067clk_domain=system.clk_domain 1068conf_table_reported=true 1069default_p_state=UNDEFINED 1070device_bus_width=8 1071device_rowbuffer_size=1024 1072device_size=536870912 1073devices_per_rank=8 1074dll=true 1075eventq_index=0 1076in_addr_map=true |
| 1077kvm_map=true |
|
| 1069max_accesses_per_row=16 1070mem_sched_policy=frfcfs 1071min_writes_per_switch=16 1072null=false 1073p_state_clk_gate_bins=20 1074p_state_clk_gate_max=1000000000000 1075p_state_clk_gate_min=1000 1076page_policy=open_adaptive 1077power_model=Null | 1078max_accesses_per_row=16 1079mem_sched_policy=frfcfs 1080min_writes_per_switch=16 1081null=false 1082p_state_clk_gate_bins=20 1083p_state_clk_gate_max=1000000000000 1084p_state_clk_gate_min=1000 1085page_policy=open_adaptive 1086power_model=Null |
| 1078range=0:134217727 | 1087range=0:134217727:0:0:0:0 |
| 1079ranks_per_channel=2 1080read_buffer_size=32 1081static_backend_latency=10000 1082static_frontend_latency=10000 1083tBURST=5000 1084tCCD_L=0 1085tCK=1250 1086tCL=13750 --- 5 unchanged lines hidden (view full) --- 1092tRP=13750 1093tRRD=6000 1094tRRD_L=0 1095tRTP=7500 1096tRTW=2500 1097tWR=15000 1098tWTR=7500 1099tXAW=30000 | 1088ranks_per_channel=2 1089read_buffer_size=32 1090static_backend_latency=10000 1091static_frontend_latency=10000 1092tBURST=5000 1093tCCD_L=0 1094tCK=1250 1095tCL=13750 --- 5 unchanged lines hidden (view full) --- 1101tRP=13750 1102tRRD=6000 1103tRRD_L=0 1104tRTP=7500 1105tRTW=2500 1106tWR=15000 1107tWTR=7500 1108tXAW=30000 |
| 1100tXP=0 | 1109tXP=6000 |
| 1101tXPDLL=0 | 1110tXPDLL=0 |
| 1102tXS=0 | 1111tXS=270000 |
| 1103tXSDLL=0 1104write_buffer_size=64 1105write_high_thresh_perc=85 1106write_low_thresh_perc=50 1107port=system.membus.master[0] 1108 1109[system.voltage_domain] 1110type=VoltageDomain 1111eventq_index=0 1112voltage=1.000000 1113 | 1112tXSDLL=0 1113write_buffer_size=64 1114write_high_thresh_perc=85 1115write_low_thresh_perc=50 1116port=system.membus.master[0] 1117 1118[system.voltage_domain] 1119type=VoltageDomain 1120eventq_index=0 1121voltage=1.000000 1122 |