| config.ini (10451:3a87241adfb8) | config.ini (10736:4433fb00fa7d) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem |
| 26mmap_using_noreserve=false |
|
| 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 --- 152 unchanged lines hidden (view full) --- 186warnOnlyOnLoadError=true 187workload=system.cpu.workload 188 189[system.cpu.checker.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb | 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 --- 152 unchanged lines hidden (view full) --- 187warnOnlyOnLoadError=true 188workload=system.cpu.workload 189 190[system.cpu.checker.dstage2_mmu] 191type=ArmStage2MMU 192children=stage2_tlb 193eventq_index=0 194stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb |
| 195sys=system |
|
| 194tlb=system.cpu.checker.dtb 195 196[system.cpu.checker.dstage2_mmu.stage2_tlb] 197type=ArmTLB 198children=walker 199eventq_index=0 200is_stage2=true 201size=32 202walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 203 204[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 205type=ArmTableWalker 206clk_domain=system.cpu_clk_domain 207eventq_index=0 208is_stage2=true 209num_squash_per_cycle=2 210sys=system | 196tlb=system.cpu.checker.dtb 197 198[system.cpu.checker.dstage2_mmu.stage2_tlb] 199type=ArmTLB 200children=walker 201eventq_index=0 202is_stage2=true 203size=32 204walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 205 206[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 207type=ArmTableWalker 208clk_domain=system.cpu_clk_domain 209eventq_index=0 210is_stage2=true 211num_squash_per_cycle=2 212sys=system |
| 211port=system.cpu.toL2Bus.slave[9] | |
| 212 213[system.cpu.checker.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.checker.dtb.walker 220 221[system.cpu.checker.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system | 213 214[system.cpu.checker.dtb] 215type=ArmTLB 216children=walker 217eventq_index=0 218is_stage2=false 219size=64 220walker=system.cpu.checker.dtb.walker 221 222[system.cpu.checker.dtb.walker] 223type=ArmTableWalker 224clk_domain=system.cpu_clk_domain 225eventq_index=0 226is_stage2=false 227num_squash_per_cycle=2 228sys=system |
| 228port=system.cpu.toL2Bus.slave[7] | 229port=system.cpu.toL2Bus.slave[5] |
| 229 230[system.cpu.checker.isa] 231type=ArmISA 232eventq_index=0 233fpsid=1090793632 234id_aa64afr0_el1=0 235id_aa64afr1_el1=0 236id_aa64dfr0_el1=1052678 --- 12 unchanged lines hidden (view full) --- 249id_isar5=0 250id_mmfr0=270536963 251id_mmfr1=0 252id_mmfr2=19070976 253id_mmfr3=34611729 254id_pfr0=49 255id_pfr1=4113 256midr=1091551472 | 230 231[system.cpu.checker.isa] 232type=ArmISA 233eventq_index=0 234fpsid=1090793632 235id_aa64afr0_el1=0 236id_aa64afr1_el1=0 237id_aa64dfr0_el1=1052678 --- 12 unchanged lines hidden (view full) --- 250id_isar5=0 251id_mmfr0=270536963 252id_mmfr1=0 253id_mmfr2=19070976 254id_mmfr3=34611729 255id_pfr0=49 256id_pfr1=4113 257midr=1091551472 |
| 258pmu=Null |
|
| 257system=system 258 259[system.cpu.checker.istage2_mmu] 260type=ArmStage2MMU 261children=stage2_tlb 262eventq_index=0 263stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb | 259system=system 260 261[system.cpu.checker.istage2_mmu] 262type=ArmStage2MMU 263children=stage2_tlb 264eventq_index=0 265stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb |
| 266sys=system |
|
| 264tlb=system.cpu.checker.itb 265 266[system.cpu.checker.istage2_mmu.stage2_tlb] 267type=ArmTLB 268children=walker 269eventq_index=0 270is_stage2=true 271size=32 272walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 273 274[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 275type=ArmTableWalker 276clk_domain=system.cpu_clk_domain 277eventq_index=0 278is_stage2=true 279num_squash_per_cycle=2 280sys=system | 267tlb=system.cpu.checker.itb 268 269[system.cpu.checker.istage2_mmu.stage2_tlb] 270type=ArmTLB 271children=walker 272eventq_index=0 273is_stage2=true 274size=32 275walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 276 277[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 278type=ArmTableWalker 279clk_domain=system.cpu_clk_domain 280eventq_index=0 281is_stage2=true 282num_squash_per_cycle=2 283sys=system |
| 281port=system.cpu.toL2Bus.slave[8] | |
| 282 283[system.cpu.checker.itb] 284type=ArmTLB 285children=walker 286eventq_index=0 287is_stage2=false 288size=64 289walker=system.cpu.checker.itb.walker 290 291[system.cpu.checker.itb.walker] 292type=ArmTableWalker 293clk_domain=system.cpu_clk_domain 294eventq_index=0 295is_stage2=false 296num_squash_per_cycle=2 297sys=system | 284 285[system.cpu.checker.itb] 286type=ArmTLB 287children=walker 288eventq_index=0 289is_stage2=false 290size=64 291walker=system.cpu.checker.itb.walker 292 293[system.cpu.checker.itb.walker] 294type=ArmTableWalker 295clk_domain=system.cpu_clk_domain 296eventq_index=0 297is_stage2=false 298num_squash_per_cycle=2 299sys=system |
| 298port=system.cpu.toL2Bus.slave[6] | 300port=system.cpu.toL2Bus.slave[4] |
| 299 300[system.cpu.checker.tracer] 301type=ExeTracer 302eventq_index=0 303 304[system.cpu.dcache] 305type=BaseCache 306children=tags 307addr_ranges=0:18446744073709551615 308assoc=2 309clk_domain=system.cpu_clk_domain | 301 302[system.cpu.checker.tracer] 303type=ExeTracer 304eventq_index=0 305 306[system.cpu.dcache] 307type=BaseCache 308children=tags 309addr_ranges=0:18446744073709551615 310assoc=2 311clk_domain=system.cpu_clk_domain |
| 312demand_mshr_reserve=1 |
|
| 310eventq_index=0 311forward_snoops=true 312hit_latency=2 313is_top_level=true 314max_miss_count=0 315mshrs=4 316prefetch_on_access=false 317prefetcher=Null --- 18 unchanged lines hidden (view full) --- 336sequential_access=false 337size=262144 338 339[system.cpu.dstage2_mmu] 340type=ArmStage2MMU 341children=stage2_tlb 342eventq_index=0 343stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb | 313eventq_index=0 314forward_snoops=true 315hit_latency=2 316is_top_level=true 317max_miss_count=0 318mshrs=4 319prefetch_on_access=false 320prefetcher=Null --- 18 unchanged lines hidden (view full) --- 339sequential_access=false 340size=262144 341 342[system.cpu.dstage2_mmu] 343type=ArmStage2MMU 344children=stage2_tlb 345eventq_index=0 346stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| 347sys=system |
|
| 344tlb=system.cpu.dtb 345 346[system.cpu.dstage2_mmu.stage2_tlb] 347type=ArmTLB 348children=walker 349eventq_index=0 350is_stage2=true 351size=32 352walker=system.cpu.dstage2_mmu.stage2_tlb.walker 353 354[system.cpu.dstage2_mmu.stage2_tlb.walker] 355type=ArmTableWalker 356clk_domain=system.cpu_clk_domain 357eventq_index=0 358is_stage2=true 359num_squash_per_cycle=2 360sys=system | 348tlb=system.cpu.dtb 349 350[system.cpu.dstage2_mmu.stage2_tlb] 351type=ArmTLB 352children=walker 353eventq_index=0 354is_stage2=true 355size=32 356walker=system.cpu.dstage2_mmu.stage2_tlb.walker 357 358[system.cpu.dstage2_mmu.stage2_tlb.walker] 359type=ArmTableWalker 360clk_domain=system.cpu_clk_domain 361eventq_index=0 362is_stage2=true 363num_squash_per_cycle=2 364sys=system |
| 361port=system.cpu.toL2Bus.slave[5] | |
| 362 363[system.cpu.dtb] 364type=ArmTLB 365children=walker 366eventq_index=0 367is_stage2=false 368size=64 369walker=system.cpu.dtb.walker --- 315 unchanged lines hidden (view full) --- 685opLat=3 686 687[system.cpu.icache] 688type=BaseCache 689children=tags 690addr_ranges=0:18446744073709551615 691assoc=2 692clk_domain=system.cpu_clk_domain | 365 366[system.cpu.dtb] 367type=ArmTLB 368children=walker 369eventq_index=0 370is_stage2=false 371size=64 372walker=system.cpu.dtb.walker --- 315 unchanged lines hidden (view full) --- 688opLat=3 689 690[system.cpu.icache] 691type=BaseCache 692children=tags 693addr_ranges=0:18446744073709551615 694assoc=2 695clk_domain=system.cpu_clk_domain |
| 696demand_mshr_reserve=1 |
|
| 693eventq_index=0 694forward_snoops=true 695hit_latency=2 696is_top_level=true 697max_miss_count=0 698mshrs=4 699prefetch_on_access=false 700prefetcher=Null --- 44 unchanged lines hidden (view full) --- 745id_isar5=0 746id_mmfr0=270536963 747id_mmfr1=0 748id_mmfr2=19070976 749id_mmfr3=34611729 750id_pfr0=49 751id_pfr1=4113 752midr=1091551472 | 697eventq_index=0 698forward_snoops=true 699hit_latency=2 700is_top_level=true 701max_miss_count=0 702mshrs=4 703prefetch_on_access=false 704prefetcher=Null --- 44 unchanged lines hidden (view full) --- 749id_isar5=0 750id_mmfr0=270536963 751id_mmfr1=0 752id_mmfr2=19070976 753id_mmfr3=34611729 754id_pfr0=49 755id_pfr1=4113 756midr=1091551472 |
| 757pmu=Null |
|
| 753system=system 754 755[system.cpu.istage2_mmu] 756type=ArmStage2MMU 757children=stage2_tlb 758eventq_index=0 759stage2_tlb=system.cpu.istage2_mmu.stage2_tlb | 758system=system 759 760[system.cpu.istage2_mmu] 761type=ArmStage2MMU 762children=stage2_tlb 763eventq_index=0 764stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| 765sys=system |
|
| 760tlb=system.cpu.itb 761 762[system.cpu.istage2_mmu.stage2_tlb] 763type=ArmTLB 764children=walker 765eventq_index=0 766is_stage2=true 767size=32 768walker=system.cpu.istage2_mmu.stage2_tlb.walker 769 770[system.cpu.istage2_mmu.stage2_tlb.walker] 771type=ArmTableWalker 772clk_domain=system.cpu_clk_domain 773eventq_index=0 774is_stage2=true 775num_squash_per_cycle=2 776sys=system | 766tlb=system.cpu.itb 767 768[system.cpu.istage2_mmu.stage2_tlb] 769type=ArmTLB 770children=walker 771eventq_index=0 772is_stage2=true 773size=32 774walker=system.cpu.istage2_mmu.stage2_tlb.walker 775 776[system.cpu.istage2_mmu.stage2_tlb.walker] 777type=ArmTableWalker 778clk_domain=system.cpu_clk_domain 779eventq_index=0 780is_stage2=true 781num_squash_per_cycle=2 782sys=system |
| 777port=system.cpu.toL2Bus.slave[4] | |
| 778 779[system.cpu.itb] 780type=ArmTLB 781children=walker 782eventq_index=0 783is_stage2=false 784size=64 785walker=system.cpu.itb.walker --- 8 unchanged lines hidden (view full) --- 794port=system.cpu.toL2Bus.slave[2] 795 796[system.cpu.l2cache] 797type=BaseCache 798children=tags 799addr_ranges=0:18446744073709551615 800assoc=8 801clk_domain=system.cpu_clk_domain | 783 784[system.cpu.itb] 785type=ArmTLB 786children=walker 787eventq_index=0 788is_stage2=false 789size=64 790walker=system.cpu.itb.walker --- 8 unchanged lines hidden (view full) --- 799port=system.cpu.toL2Bus.slave[2] 800 801[system.cpu.l2cache] 802type=BaseCache 803children=tags 804addr_ranges=0:18446744073709551615 805assoc=8 806clk_domain=system.cpu_clk_domain |
| 807demand_mshr_reserve=1 |
|
| 802eventq_index=0 803forward_snoops=true 804hit_latency=20 805is_top_level=false 806max_miss_count=0 807mshrs=20 808prefetch_on_access=false 809prefetcher=Null --- 17 unchanged lines hidden (view full) --- 827hit_latency=20 828sequential_access=false 829size=2097152 830 831[system.cpu.toL2Bus] 832type=CoherentXBar 833clk_domain=system.cpu_clk_domain 834eventq_index=0 | 808eventq_index=0 809forward_snoops=true 810hit_latency=20 811is_top_level=false 812max_miss_count=0 813mshrs=20 814prefetch_on_access=false 815prefetcher=Null --- 17 unchanged lines hidden (view full) --- 833hit_latency=20 834sequential_access=false 835size=2097152 836 837[system.cpu.toL2Bus] 838type=CoherentXBar 839clk_domain=system.cpu_clk_domain 840eventq_index=0 |
| 835header_cycles=1 | 841forward_latency=0 842frontend_latency=1 843response_latency=1 |
| 836snoop_filter=Null | 844snoop_filter=Null |
| 845snoop_response_latency=1 |
|
| 837system=system 838use_default_range=false 839width=32 840master=system.cpu.l2cache.cpu_side | 846system=system 847use_default_range=false 848width=32 849master=system.cpu.l2cache.cpu_side |
| 841slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port | 850slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port |
| 842 843[system.cpu.tracer] 844type=ExeTracer 845eventq_index=0 846 847[system.cpu.workload] 848type=LiveProcess 849cmd=hello 850cwd= | 851 852[system.cpu.tracer] 853type=ExeTracer 854eventq_index=0 855 856[system.cpu.workload] 857type=LiveProcess 858cmd=hello 859cwd= |
| 860drivers= |
|
| 851egid=100 852env= 853errout=cerr 854euid=100 855eventq_index=0 856executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 857gid=100 858input=cin | 861egid=100 862env= 863errout=cerr 864euid=100 865eventq_index=0 866executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 867gid=100 868input=cin |
| 869kvmInSE=false |
|
| 859max_stack_size=67108864 860output=cout 861pid=100 862ppid=99 863simpoint=0 864system=system 865uid=100 866useArchPT=false --- 13 unchanged lines hidden (view full) --- 880eventq_index=0 881sys_clk_domain=system.clk_domain 882transition_latency=100000000 883 884[system.membus] 885type=CoherentXBar 886clk_domain=system.clk_domain 887eventq_index=0 | 870max_stack_size=67108864 871output=cout 872pid=100 873ppid=99 874simpoint=0 875system=system 876uid=100 877useArchPT=false --- 13 unchanged lines hidden (view full) --- 891eventq_index=0 892sys_clk_domain=system.clk_domain 893transition_latency=100000000 894 895[system.membus] 896type=CoherentXBar 897clk_domain=system.clk_domain 898eventq_index=0 |
| 888header_cycles=1 | 899forward_latency=4 900frontend_latency=3 901response_latency=2 |
| 889snoop_filter=Null | 902snoop_filter=Null |
| 903snoop_response_latency=4 |
|
| 890system=system 891use_default_range=false | 904system=system 905use_default_range=false |
| 892width=8 | 906width=16 |
| 893master=system.physmem.port 894slave=system.system_port system.cpu.l2cache.mem_side 895 896[system.physmem] 897type=DRAMCtrl 898IDD0=0.075000 899IDD02=0.000000 900IDD2N=0.050000 --- 14 unchanged lines hidden (view full) --- 915IDD4W2=0.000000 916IDD5=0.220000 917IDD52=0.000000 918IDD6=0.000000 919IDD62=0.000000 920VDD=1.500000 921VDD2=0.000000 922activation_limit=4 | 907master=system.physmem.port 908slave=system.system_port system.cpu.l2cache.mem_side 909 910[system.physmem] 911type=DRAMCtrl 912IDD0=0.075000 913IDD02=0.000000 914IDD2N=0.050000 --- 14 unchanged lines hidden (view full) --- 929IDD4W2=0.000000 930IDD5=0.220000 931IDD52=0.000000 932IDD6=0.000000 933IDD62=0.000000 934VDD=1.500000 935VDD2=0.000000 936activation_limit=4 |
| 923addr_mapping=RoRaBaChCo | 937addr_mapping=RoRaBaCoCh |
| 924bank_groups_per_rank=0 925banks_per_rank=8 926burst_length=8 927channels=1 928clk_domain=system.clk_domain 929conf_table_reported=true 930device_bus_width=8 931device_rowbuffer_size=1024 | 938bank_groups_per_rank=0 939banks_per_rank=8 940burst_length=8 941channels=1 942clk_domain=system.clk_domain 943conf_table_reported=true 944device_bus_width=8 945device_rowbuffer_size=1024 |
| 946device_size=536870912 |
|
| 932devices_per_rank=8 933dll=true 934eventq_index=0 935in_addr_map=true 936max_accesses_per_row=16 937mem_sched_policy=frfcfs 938min_writes_per_switch=16 939null=false --- 37 unchanged lines hidden --- | 947devices_per_rank=8 948dll=true 949eventq_index=0 950in_addr_map=true 951max_accesses_per_row=16 952mem_sched_policy=frfcfs 953min_writes_per_switch=16 954null=false --- 37 unchanged lines hidden --- |